SU593212A1 - Digital device for logarithmation of binary numbers - Google Patents

Description

one

The invention relates to the field of computer technology and can be used as a python generator of values of a logarithmic function.

Device 1 is known, allowing us to calculate its logarithms using algorithms digit by digit. It contains a block of permanent memory, adders, registers, control blocks. The disadvantage of such a device is low speed.

The closest of the technical essence and the achieved result to the invention is the device 2, containing the control unit, registers of the high and low bits of the argument, outputs connected respectively to the first and second blocks of the fixed memory, the outputs of which are connected to the first inputs of the adder and switch, respectively , the second input of the adder is connected to the output of the switch, and the output is connected to the input of the output register.

However, such a device with a sufficiently high speed has large volumes of blocks of permanent memory.

The aim of the invention is to reduce the total information capacity of the blocks of the permanent memory, i.e. the reduction of the equipment.

The goal is achieved by the fact that the proposed device additionally introduces a third block of a constant type, a shifter, a shifter control unit, a trigger, which is connected by its input to the output of the character of the adder,

5 the adder is connected to the input of the third block of permanent memory, the output of which is connected through the shifter to the second input of the switch, the control input of the shifter is connected to the output of the shift control unit 10, the first and second inputs of which are connected respectively to the trigger output and the output of the low-order argument register However, the control unit is connected to the control input of the switch.

15 The drawing shows the block diagram of the device.

The device contains registers of the higher 1 and lower 2 bits of the argument, blocks of permanent memory 3-5, control block 6, switch 7, adder 8, output register 9, trigger 10, offset And, block 12 of the shift controller.

The binary logarithm from the normalized argument x () is calculated in the proposed device on the basis of relations

log, (X + X): lOg.X + log. (1 +)

30logs log., X - logj.,

where l; - the number formed by the higher bits of the argument.

x is the number formed by the lower order bits of the argument.

The device works as follows.

At the first stage of operation of the device, the storage and transmission on the registers of the upper 1 and lower 2 bits of the argument, the values of k and k, are transmitted respectively to the inputs of blocks 3 and 4 of the permanent memory, where the tables of logarithms of the higher and lower digits of the argument are stored, and their outputs are taken from the mantissa values (-loga;) and respectively. These values are fed to the inputs of the adder 8, and the contents at the output of the block of permanent memory 4, the log2J; mantissa, passes through the controlled switch 7, which connects the output of the block 4 to the input of the adder 3. At the output of the adder 8 According to, the value of §2x7l; whose mantissa is transmitted to the input of the memory block 5, where the intermediate conversion table is stored. This block performs a table conversion of the mantissa value to the corresponding value.

log, (l +), where q is an integer such that

2- 2-.

The number k satisfies the condition, where n is the number of binary bits of the argument.

The value of the sign bit of the adder 8 when mantiss (-loga;) and log2A; memorized on trigger 10 of the intermediate result.

The shifter control unit 12 is a combinational circuit counting the number of zero bits from the left to the first one bit in the register 2 lower bits of the argument and summing this number with the trigger value 10 of the intermediate result, which gives the value of the required number of shifts q in the shifter 11 to obtain at its output the value of Iog2 () from the input of the value of this shifter log2 (l + 29A; 7). The latter is true in view of the fulfillment of the condition for k, since in this case an approximate equality holds with an accuracy of 2 - (+ 1)

log, (I +) 2-9 log, (1 + 2 x, 1k.

The number log2 (l + xV) formed at the output of the shifter 11 through the controlled switch 7 connecting the outputs of the shifter I to the input of the adder 8 to the adder where the Iog2 value is added (and the logax value sent to the other inputs of the adder from the output of block 3, where the table of logarithms of the high-order bits of the argument is stored. As a result of the addition on the adder, the required

the log2X mantissa value, which is transmitted to output register 9.

Thus the proposed device

converts the normalized value of the argument x to the mantissa value log2X Value

the characteristics of this logarithm is equal to

this is 1.

By minor structural changes, the device described may be

converted to a digital device for calculating logarithms of numbers represented as floating point. To do this, it is sufficient to enter into the composition of the described device an adder of the order in which one would be subtracted from the order of the argument. The result of this operation will be a characteristic of the desired logarithm. Calculations carried out to determine the total information capacity of the blocks of permanent memory used in the device, give the following value.

Q (ha + i) (“- / fe) + 14. 2“ where

: + 1 at k + 1 at.

By comparing the proposed device with the prototype, for example, for the value of n 24, it is clear that if the prototype requires an information volume of 15-222 bits, then for the considered device only 1192 bits are used, i.e., a gain of more than 250 times is obtained.

Claims (2)

1. Baikov V. D., Smolov V. B. “Apparatus realization of elementary functions in a digital computer, from LSU, L., 1975. 2. USSR author's certificate No. 342193, cl. G 06G 7/26, 1972.