SU978146A1 - Function computation device - Google Patents

Description

(54) DEVICE FOR CALCULATION OF FUNCTIONS 51 NX AND COSX

 The invention relates to computing and can be applied in the construction of specialized computing devices.

A device is known that contains two multipliers, the outputs of which are connected to the inputs of the adder, and two memory blocks tl.

The sine and cosine functions are determined based on the ratios

sinCx + Axj sinx - cos dx + dx cosx

cos (x - "- ax) cosx + DX sinx

The sinx and cosx values should be recorded as coefficients in the memory blocks. Here, for x, represented by n bits, the number of stored coefficients N is defined as.

The disadvantage of this device is the need to use a large amount of memory.

The closest in technical essence to the present invention is a device comprising an argument register, memory blocks, two multipliers, an adder and an output register C 2.

A disadvantage of the known device is the increased memory capacity.

required for storing sinx function values.

The purpose of the invention. - reduction in the amount of used memory.

This goal is achieved by the fact that the device for calculating the functions sinx and cosx, containing the first and second multipliers, the first adder and the memory block of coefficients,

10, the first and second inputs of the first adder are connected to the outputs of the first and second multipliers, respectively, contains a switch, an encoder, four adders, a square raising unit, two registers, a third and fourth multipliers, the output of the coefficient memory block is connected to the information input of the switch, control The input input of which is connected to the first output of the encoder, the input of which is connected to the input argument of the device, the first and second outputs of the switch are connected to the first inputs of the second and third total, respectively ditch, the second inputs of which are connected to the second output of the encoder, the third output of which is connected to the first input of the third multiplier, the second input of which is connected to the output

30 of the first register, the output of the third knife’s mind is connected to the first inputs of the fourth adder and multiplier and through the squaring block to the second input of the fourth multiplier and the first input of the fifth adder, the second input of which is connected to the output of the second register, the output of the fourth multiplier is connected to the second input of the fourth adder, the outputs of the second and third adders are connected with the first inputs of the first and second multipliers, respectively, the second inputs of which are connected by the outputs of the fourth and fifth su, respectively Mmators, the output of the first sum of the mat is connected to the second inputs of the second and third adders and the output of the device. The drawing shows the block diagram of the proposed device. The device for calculating the functions sinx and COSX contains switch 1, adders, block 3, squaring, multipliers 4-4, encoder 5, encoder input 6, encoder outputs 7-9, coefficient memory block 10, registers 11 and 12. Encoder 5 contains tn-5) converters of the direct code in an additional one, where n is the width of the NIN argument. Each subsequent converter included in the encoder converts (K-1) the bits of the previous converter, where K is the number of bits at the output of the previous converter, with the K-th bit controlling the next converter. If the K-th bit is O, then the code is converted to additional, if 1, then a direct code is issued. The first output of the encoder is the (n + 1) -th bit of the argument, which determines the calculation mode (s inx or cosx), the second output of the encoder is the output of the K-x bits of the cryptographic converters. Rattor, third output - output (p-5) -d encoder converter. The device works as follows. Let it be necessary to calculate the sin angle of 54 °. At the input b of the device, the code is 110 110 110, corresponding to an angle of 54 °. According to the encoder's signal coming from its output 7, the switch sends the constants A 0.110000 and A 0.001110 coming from the memory block 10 to the adder 2, and the constants A2. 0,011110 and a 0,010111 on the adder 2-,. In .table shows the values of the constants supplied from the memory to the switch i, with an argument width from 0 to 7. Constants 1 I i 0.110000 0.011100 0.010111 0.001110 where A sin 64 ° sin 32 °; 64 ° sin 32; 64 ° cos 32 °; 64 ° sin 32. In general, the constants are as follows. AT sin DG,; cos. A. Where A and are constants defined for the n-bit representation of an argument. The sign bits of the adders 2 and 22 come from encoder 5 on output 8, values O or 1, defining signs for constants, the value O specifies the sign +, 1 sign -. The values defining the signs for the constants are taken from the higher bits, resulting in 5 code patterns in the encoder. Using the characters, in the adder 2, the addition is -0.0011104 and +0.110000, in the adder 2x, the addition is +0.011110 and +0.010111. The code 0.110101 received in the adder 2 is fed to the first input of the multiplier 4, the binary code 0.100010 from the adder 2 2 is fed to the first input of the multiplier 4J. At the same time, block 3 and the first input of the multiplier 4, multiplier 4, receives the number / 3, equal to 0.011111, which is obtained by multiplying in the multiplier 4 a constant number 0.000001, coming from register 12 by the value J,. coming from the output of 9 encoder 5. Thus, cL 100000-dpri x O, ot 065-10000 with X | 1, where Hz is the value of the highest bit. At the output of the squaring block 3, we get the movable code 0.001111, which is fed to the second input of multiplier 4-1, the output of which gives the binary code 0.0001111, corresponding to the cube of the number B. This code, multiplied by the constant for the proposed device 0.000100 is fed to the second input of the adder 2 ,,, the first input of which receives the number B, multiplied by the constant for the proposed device, the number equal to 0.110010. The binary code 0,010111 received from the output of adder 2 is fed to the second input of multiplier 4, where this binary code is multiplied by the binary code 0.110010, coming from adder 2. As a result of multiplication, we obtain a movable code 0,010011 25

At the second input of the adder g receives the binary code 0,011110, obtained as follows. From the output of block 3, the square of the number, equal to 0.001111, is multiplied by the device constant number 0.010010 to the first input of the adder 2, the second input of which receives the Q number 0.111111 constant for the proposed device. The code 0.111011 obtained in adder 2 is multiplied in multiplier 4 j by the code 0.001110 received from adder 2, the number 0,011110 received as a result of multiplication and will be fed to the second input of adder 2, in which after assigning 5 characters to the encoder by the corresponding term - ' det addition, and the output will be an i value of 0.110001, corresponding to sin of the binary number 110110.

We will also consider the device operation when calculating cos 54 ° using an example. When calculating cos 54 ° using the signal 25 of the encoder 5, coming from the control output If, commutator 1 sends the constants A 0.110000 and A4 0.001110 coming from memory 10 to memory adder 2, and the constants A2 30 0.011110 and AZ 0.010111 to the adder 22. The encoder 5 assigns g to output 8 characters for the constants fed to adders 2 and 2. In adder 2, the addition of 35 A is 0.110000 and A is +0.001110, in the adder is 2 2 the addition of A2 is +0.0111110 k AJ +0, 010111. further on, the calculation process is similar to the sine calculation process. In this case, the digitator 5 determines the signs of the code combinations arriving at the adder 5j. The accuracy of the results depends on the magnitude of the representation of the constants.45

Thus, by introducing additional blocks and links into the proposed device, we obtain a positive effect, which makes it possible to reduce by 50 the amount of used memory in comparison with the known device.

Claims (2)

1.Oranian A.M. Hardware methods in digital computing. Minsk, 1977, p. 49-50. 2. Authors certificate of the USSR W 622090, cl. G About F 7/548, 1977 (prototype).