SU919127A1

SU919127A1 - Device for synchronizing cyclic codes

Info

Publication number: SU919127A1
Application number: SU802903152A
Authority: SU
Inventors: Александр Оскарович Гурдус; Евгений Матвеевич Злочевский
Original assignee: Предприятие П/Я А-1251
Priority date: 1980-03-31
Filing date: 1980-03-31
Publication date: 1982-04-07

Description

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Изобретение относитс к импульсной технике и может быть использовано в системах передачи дискретной информации .The invention relates to a pulse technique and can be used in discrete information transmission systems.

Известно устройство блочной синхронизации циклических кодов, содержащее анализатор, дешифратор и генератор тактовых импульсов (ГТИ), выход которого через первый делитель частоты подключен ко входу анализатора .1 .A device for block synchronization of cyclic codes is known, which contains an analyzer, a decoder and a clock pulse generator (GTI), the output of which is connected to the analyzer input through a first frequency divider .1.

Однако устройство имеет высокую веро тность сложной синхронизации.However, the device has a high probability of complex synchronization.

Цель изобретени - уменьшение веро тности сложной синхронизации.The purpose of the invention is to reduce the likelihood of complex synchronization.

Дл достижени цели в устройство блочной синхронизации циклических кодов, содержащее анализатор, дешифратор и генератор тактовых импульсов (ГТИ), выход которого через перпый делитель частоты подключен ко входу анализатора, введены ключ, второй делитель частоты, а также последовательно соединенные переключатель , блок т-разр дных счетчиков, .первый элемент ИЛИ, и второй элемент ИЛИ, выход которого подсоединен к дополнительному входу блока т-разр дных счетчиков, выход генератора ТИTo achieve the goal, a cyclic code block synchronization device containing an analyzer, a decoder and a clock pulse generator (GTI), the output of which is connected to the analyzer input through the first frequency divider, a key, a second frequency divider, and a series-connected switch are entered the first counters, the first OR element, and the second OR element, the output of which is connected to the auxiliary input of the block of t-bit counters, the generator output TI

через второй делитель частоты подсоединен ко второму входу элемента ИЛИ, первый вход которого подключен ко второму входу первого делител частоты и первом входу ключа, ко второму входу которого подключен выход анализатора, а выход ключа через дешифратор подсоединен к первому входу переключател ,ко второму входу которого подключен дополнительный выход генератора ТИ.through the second frequency divider is connected to the second input of the OR element, the first input of which is connected to the second input of the first frequency divider and the first input of the key, to the second input of which the analyzer output is connected, and the output of the key is connected via the decoder to the first input of the switch, to the second input of which is connected additional generator output TI.

На фиг. 1 представлена структурноэлектрическа схема устройства; на фиг. 2 - графики,по сн ющие его работу .FIG. Figure 1 shows a block diagram of the device; in fig. 2 - graphs that show his work.

Устройство содержит анализатор 1, ключ 2, дешифратор 3, переключатель 4, блок 5 т-разр дных счетчиков, первый элемент ИЛИ б, генератор ТИ 7, первый делитель 8 частоты, второй элемент ИЛИ 9 и второй -елитель 10 частоты.The device contains analyzer 1, key 2, decoder 3, switch 4, block 5 of t-bit counters, first element OR b, generator TI 7, first frequency divider 8, second OR 9 element and second frequency selector 10.

Устройство работает следующим образом .The device works as follows.

Claims

The binary information encoded by the cyclic code is input to the analyzer 1 of the code combination, which divides the 30 n-element docic bgls into the i-generating polynomial q (x) of the code used. Key 2 in the search mode of the beginning of the code block (words) is open. The search for the start of a code block of a cyclic (n, k) code begins at time tg. At the moment of time (ntj + + pr), where ty is the symbol duration, the output of the decoder 3 turns on the signal 1 at zero or if the signal of the n-character block starts at the moment t (j. This signal will go through the switch 4 in the first shift register of the block of the 5 counters. At the time point (tj, + Fri) + t, at the output of the decoder 3, the signal indicates zeroing or non-zeroing of the syndrome of the n-character block starting from the time position (t J, -ft () This signal will go through switch 4 to the second shift register block 5 t-bit counters.The signals from the output of the decoder 3, corresponding to the remaining (p-2) time positions of the n-character blocks, go to the corresponding (p-2) shift register of block 5, alternately connected by a switch 4. At the moment {t + 2 p t vt) the signal will again arrive at the first shift register of block 5. This procedure is repeated until the condition is reset in one of the registers to zero the syndrome in S of the polled blocks. If 2 units arrived at the input of one of the t-bit counters of block 5, a signal appears at the output of the first element OR b, which arrives at the second input of the first frequency divider 10 whose frequency is ten (1: n). The first input of this frequency divider receives pulses from the TI 7 generator, and at the output of the first frequency divider, a signal appears, indicating entry into synchronization with n-element code blocks. At the same time, the signal from the first element OR 6 closes the key 2, breaking the connection of the decoder 3 with the analyzer, and through the second element OR b puts all the t-bit counters of unit 5 into the zero state. From analyzer 1, every n clock cycles (by the signal from the output of the first frequency divider 10), binary information is recorded. If during the reception of S p-element binary blocks, the signal at the output of the first element OR b did not follow, v.6. The device did not detect the beginning of any p-element code block, all n p-bit counters of lock 5 are translated to the zero state by the signal coming from the second element OR 9, which receives the signal from the second multiplier frequency divider (1: n S), controlled by the TI generator 7. The search procedure for the start of the n element code lock is repeated. Thus, the proposed device provides the entry into synchronism with the probability of false synchronization V.) the probability of false synchronization without re-asking the blocks is equal to the probability of false synchronization in the prototype, since LS1 ".. The average time for entering synchronization in this case lies within % A "4p St5 ,, where the duration of the n-element block. Claims A block synchronization device for cyclic codes containing an analyzer, a decoder and a clock pulse generator (GTI), the output of which is connected to the analyzer input, via the first frequency divider, in order to reduce the likelihood of false synchronization, a key has been entered the second frequency divider, as well as a series-connected switch, a block of gas meters, the first element OR, and a second element OR, the output of which is connected to the auxiliary input of the block t-bit counters the output of the TI generator is connected via the second frequency divider to the second input of the second element OR, the first input of which is connected to the second input of the first frequency divider and the first input of the key, to the second input of which the analyzer output is connected, and the output of the key via the decoder is connected to the first input of the switch, to the second input of which is connected an additional generator output TI. Sources of information taken into account during the examination 1. USSR Copyright Certificate W 568188, H 04 L 7/08, 1976 (prototyl).

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