SU786040A1 - Discrete information receiver - Google Patents

Description

one

The invention relates to a communication technique and can be used for cycle phasing of discrete information transmission equipment.

A known discrete information receiver comprising two AND elements, a distributor, a block of counters, and a drive, the output of which is connected to the input of the error detection block l.

However, the reliability of this receiver is insufficient.

The purpose of the invention is to increase the reliability of work.

For this purpose, the main and additional logic blocks, the OR element, the trigger and the synchronization block, the outputs of which are connected to the inputs of the OR element, are inserted into the discrete information receiver, which contains two AND elements, a distributor, a counter block and an accumulator. , the output of which is connected to the CQ input of the trigger and the first input of the main logic unit, the first output of which is connected to the input of the distributor. The first output of the distributor is connected to the first input,

The first element And the second input of which is connected to the trigger output and the first input of the second element And the second input of which is connected to one of the inputs of the synchronization unit and the second output of the distributor. The third output of the distributor is connected to the first inputs of additional logic blocks, the second inputs of which

10 is connected to the second output of the main logic unit, the second input of which is connected to the third input of the second element AND, the third inputs of additional logic blocks,

t5 by the output of the error detection block and with the other inputs of the synchronization block, the additional inputs of which are connected to the first outputs of the block of counters, the second outputs of which

20 are connected to the corresponding inputs of the main and additional) from logical blocks, clock inputs of which are connected to the input of the drive. The inputs of the meter block are connected to the first outputs of the additional logic blocks, and the second outputs of the corresponding additional logic blocks are connected to the fourth inputs of the corresponding additional logic blocks.

The drawing shows a structural electrical circuit of the proposed receiver.

The discrete information receiver contains a drive 1, an error detection block 2, a main logic block 3, a distributor 4, an additional logic block 5, a block 6 of counters, a synchronization block 7, element 8 OR, trigger 9 / two elements 10 and 11 I.

Receiver discrete information works as follows.

The information enters into the r. G. Discharge drive 1, from which p. The cyclic tact is transmitted to the error detection unit 2, where the corresponding class C is added to the corresponding P-element combination, and then the resulting combination syndrome is determined. If the resulting syndrome is zero, error detection block 2 generates a signal.

As soon as in block 2 the first zero syndrome is received, the main logic unit 3 will trigger and the clock pulses will start to flow to the distributor 4.

During the following tp-element combinations after the start of the distributor 4, the synchronization unit 7 counts the number of zero syndromes in the analyzed position and gives a signal about the presence or absence of a synchronous state.

If during this period there is zero syndrome at any other position, then additional logic block 5 is triggered, and during the following P – element combinations after starting the block b of counters, synchronization block 7 counts the number of zero syndromes at the analyzed position and gives a signal or no synchronous state at this position.

If at the end of the analysis time t of the combinations after the start of the distributor 4, the corresponding logic block gives a signal about the presence of a synchronous state, then the trigger 9 is triggered and reset to zero. With the first impulse from the distributor 4, a signal is issued and the information from accumulator 1 together with the signal Correctly (Wrong) begins to flow to the user field.

If, after the expiration of the time of the m combinations, after the start of the 4 appropriate allocators, the logical unit does not signal the presence of a synchronous state, then the jpacnreater 4 continues to work in the initial mode, and the corresponding logical unit starts to continue the next m combinations.

If the block of 6 counters has been triggered, the magic block 3 stops passing the clock pulses to the distributor 4 (before the first combination with zero syndrome arrives at the position not included in the synchronization unit 7 being analyzed), the distributor 4 and synchronization block 7 is set to zero condition. If during the analysis of the combinations after the start of the block 6 of the counters, the synchronization block 7 issues a confirmation signal (a signal about the presence of the synchronous state), the trigger 9 is turned on, zeroing and shutdown is performed, the distributor 4 is started, the signal with the first impulse from the distributor is output

5 4 and information from accumulator 1 together with the signal True (False) starts to flow to the receiver. If, during the analysis of m combinations, after the start of block b of counters, synchronization block 7 does not issue a confirmation signal, then block 6 of counters stops issuing clock pulses (until the first combination with zero syndrome belonging to the position that is not included in the number of synchronization blocks 7 arrives) and set to zero.

Claims (1)

1. USSR author's certificate 464979, cl. H 04 L 1/10, 1973 (prototype).