SU932643A1 - Device for block synchronization for group codes - Google Patents

Description

(54) DEVICE BLOCK SYNCHRONIZATION

FOR GROUP CODES

I

The invention relates to communication systems and can be used for

block synchronization of information transmission systems using adjacent-group codes.

A frame alignment device is known that contains the syndromes definition unit sequentially connected, the sync signal syndrome identifier, the delay element, the matching element, the combining element, the error accumulator, the cyclic pulse generator, and the prohibition element whose output is connected to the second input of the error accumulator are connected to the second input of the prohibition element the second input of the coincidence element and the input MeHta delay, as well as the identifier of the corrected error syndromes, included between the input of the identification syndrome clock signal and the second input of combining element Ct.

The disadvantage of this device is the preservation of a high probability of false synchronization.

A block synchronization device for group codes is known, comprising a serially connected input register, an adder and a decoder, a serially connected clock generator and a frequency divider, as well as a code generator, the output of which is connected to the second input of the adder, a decoder whose input is connected to the output of the input register and element and 2.

The disadvantage of this device is that the transition to adjacent classes of group (n, K) -codes with a high code rate provides protection against false synchronization only at a small number of asynchronous positions of code blocks.

The purpose of the invention is to improve the synchronization accuracy.

This goal is achieved in that a block synchronization device for group codes comprising a serially connected input register, an adder and a decoder, a serially connected clock generator and a frequency divider, as well as a code generator, the output of which is connected to the second input of the adder, decoder, input which is connected to the output of the input register, as well as the AND element, the serially connected additional decoder and the OR element, as well as the discriminator of the time error, are entered into the course of which through the OR element is connected to the second input of the frequency divider, the output of which is connected to the combined first inputs of the input register, the AND element and the time error discriminator, the second input of which is combined with the second input of the AND element and the output of the AND element connected to the input of the code generator.

The drawing shows a block diagram of the device.

The device contains an input register 1, a decoder 2, an adder 3. a code generator k, a decoder 5. a clock generator 6, a frequency divider 7, an additional decoder 8 OR element 9, a time error discriminator 10, and an AND 11 element.

The device works as follows.

When transmitting information, code blocks belonging to two adjacent-group codes are used: (n, K-f) -K i

CODE LOW Code R

-1 and

and (n, K23-code with high speed

R.. With

code

match 2. and 2.

By choosing a code, the probability of random satisfaction with a certain combination of symbols formed at the junction of two blocks belonging to one code is equal to zero for the construction of another code.

At the beginning of each information transfer cycle, code blocks belonging to a certain replaceable class of cyclic (n, K) code with a low code rate are transmitted, for which the probability of accidental satisfaction of nonsynchronous phase shifts is equal to the code construction law

zero (i.e. zero probability of false synchronization). The decoder 8 with each shift of the information accumulated in the input n-bit register, gives the results of checking the various phase positions. In the synchronous position, a single signal appears at the output of the decoder 8, which phases the frequency divider 7, controlled by a generator of 6 clock pulses. At. In this case, the signal from the output of divider 7 of the frequency of the multiplicity G: n begins to flow to the control input of input register 1, wrapped it every n cycles (after the end of the code block).

After transmission of one or several blocks of low-speed code, the transfer of information to code blocks belonging to some adjacent class of cyclic (n, Kg) code with high speed kbda for which the probability of false synchronization is zero only for several asynchronous phase shifts belonging to synchronous This results in an increase in the speed of information transmission, since at a constant frequency band of the communication channel, for the same duration of the n-character block more information is transmitted ionic character.

The decoder 2 generates single signals (in synchronous mode), which are fed to the first input element And 1 to the second input of which receives signals from the frequency divider 7.

In the absence of synchronization synchronization at the output of the element 11, a signal appears, the phasing generator 4 of the code.

Claims (2)

The output information is sync O ii; o is summed with the main element of the adjacent class in adder 3 and decoded in decoder 5 When the synchronization fails at the output of decoder 2, the unit signal disappears if the combination of n characters at the junction of code blocks does not comply with the code construction law. At the same time, the phasing signals at the input of the frequency divider 7 and the output of the And 11 element disappear and the zeroing of the input register 1 and the removal of information from the decoder 5 ceases. The decoder 2 begins to produce the results of checks of various phase positions with each shift of information accumulated in the input register 1. When a single signal appears at the output of the decoder 2, indicating that the code combination satisfies the code-building law, the signal at the output of the element 11 is only visible when the second signal arrives at its second input Nala with a divider 7 hour tota. This case corresponds to the correct synchronization. Single signals from the output of the decoder 2 simultaneously arrive at the second input of the discriminator 10 temporary mismatch, the first input of which receives signals from the frequency divider 7. In the discriminator 10 temporal mismatch, an analysis is made of the temporal position of the output signal of the decoder 2 relative to the last signal received from frequency divider 7. If this error is At mn Tc ± i Te, where Vf is the symbol duration, m is an arbitrary integer, is the maximum number of phase shifts at which the probability of false synchronization is zero, then the discriminator output 10 time error rephases the frequency divider 7 in accordance with the temporal position of the output unit signal of the decoder 2 and at the output of the element 11, there is a signal permitting the release of information. If, however, the temporal mismatch exceeds the number of shifts at which the probability of a false synchronization is zero, then this means a false definition of the synchronous position. In this case, the signal at the output of the time error discriminator 10 is absent, rephasing the frequency divider 7 does not occur and the search for the synchronous position continues. Thus, the proposed device, using the properties of adjacent group codes, can significantly reduce the likelihood of receiving false information by reducing the likelihood of false synchronization both at the beginning of a communication session and when recovering synchronism in case of possible failure, during storage. high speed information transfer, i.e. 1 improve timing accuracy. A block synchronization device for group codes comprising a serially connected input register, an adder and a decoder, serially connected clock pulses and a frequency divider, as well as a code generator, the output of which is connected to the second input of a summator, a decoder, the input of which is connected to the output of the input the register, as well as the element I, which is so that, in order to increase the synchronization triciness, sequentially connected additional decoder and NT OR, as well as the time error discriminator, the output of which through the OR element is connected to the second input of the frequency divider, the output of which is connected to the combined first inputs of the input register, the AND element and the time error discriminator, the second input of which is combined with the output of the decoder, while the output element And is connected to the input of the code generator. Sources of information taken § § attention in the examination 1. The author's certificate of the USSR № 569039, cl. H 0 L 7/08, 1976. 2. USSR author's certificate number 98751, cl. H Oi L 7/08, 1973 (prototype). S 00