SU913455A1 - Self-checking fixed storage - Google Patents

Description

The invention relates to storage devices.

Known permanent storage device (ROM) with self-control, containing the drive, the decoder ad 'res, logical elements AND, the elements OR, the adders modulo two and the control unit [11.

The disadvantages of this event are its complexity and low reliability of control with increasing information capacity.

The closest technical solution to this invention is a persistent storage device in self-control, containing an address decoder, w storage blocks, t encoders, hp control units, Ν-bit register-number counter, t-modulo adders, and N elements [21 .

The disadvantages of this device are complexity, since the number of elements And modulators and modulators 2,

2

contained in it, is directly proportional to the number of information bits of the device, the lack of control over the correctness of the address reception, the inability to use as a drive modern integrated circuits (IC) of the ROM, since it requires a signal not only from the drive output, but also from its intermediate outputs, and also, the need for additional equipment when increasing the information capacity, which prevents the use of this device as a unified module.

The purpose of the invention is to provide control of address circuits and simplify the device, as well as to achieve the possibility of using it as a unified module.

This goal is achieved by

that in a self-monitoring read-only memory, containing the drives', the main convolution blocks are

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module two, OR elements and OR-NOT elements, the address inputs of the drives are connected to the outputs of the corresponding elements OR-NOT whose inputs are the device’s address inputs 5, the outputs of the drives are connected to the information inputs of the corresponding basic convolution units two, the outputs of which are connected to the first inputs of the corresponding K elements OR, the second input of the first element OR is connected to the input of the sampling resolution of the first drive, the second input of the second element OR is connected to the resolution input of the 15 ki orogo Drive; the control data accumulator, an additional modular convolution unit, modulo two adders and an AND-OR-NOT element are entered, the first and second inputs of which are connected to the second inputs of the first and second OR elements, respectively, whose outputs are connected to the third and the fourth inputs of the element AND-OR-NOT, the fifth and 25

the sixth inputs of which are connected respectively to the outputs of the first and second modulo-two adders, the first inputs of which are connected respectively to the direct and inverse outputs of an additional convolution unit modulo two, the second input of the first modulo-two adder is connected to the first input of the third adder along the module two and the enable input of the first drive, the second input of the second modulo two is connected to the output of the third modulo-two adder and the enable input of the second drive, the address inputs are additional ADDITIONAL block convolution modulo two are respectively connected to the address inputs of the drives, and the first control input connected to the output of the corresponding OR-NO element, whose input is combined with the second yn additional input ⁴⁵ equals the convolution unit modulo two and is a control input of the device, the address inputs control data accumulator50

They are connected to the address inputs of the device, the sample input is connected to the zero potential bus, and the outputs are connected respectively to the first control inputs of the basic convolution units modulo two and ⁵⁵ inputs of the corresponding OR-NOT elements, whose outputs are connected to the second control inputs of the bases5. four

modulo two convolution blocks.

The drawing shows a functional diagram of the proposed device.

The device contains the first 1 and second 2 drives, each consisting of 2 ^m words for N bits, · the first 3 and second 4 main modules of convolution modulo two, each with (Ν + 1) input, the first 5 and second 6 elements OR, the element AND-OR-NOT 7, the first 8, the second 9 ^{and the} third 10 modulo-two adders, an additional modular convolution block 11, having (M + 1) inputs, a control data accumulator 12 consisting of 2 ^m four-digit words, and OR-NOT elements 13. In addition, informational outputs 14 of the device are designated, inputs 15 and 16 of the sampling resolution, respectively, are first second and second accumulators, indicator output 17, address inputs 18, sample input 19 and device control input 20, additional module convolution address inputs 21 modulo two, second inputs 22 and 23, respectively, of the first and second modulo two modulators, address inputs 24, sample input 25 and outputs 26 of the control data accumulator, first 27 and second 28 inputs and output 29 of the third modulo-two adder.

The device can be implemented on TTL-series integrated circuits and LSI ROM.

The device works as follows.

The drive 12 records the values of the control bits of the words recorded in drives 1 and 2. The information read from the outputs of drives 1 and 2 is minimized in blocks 3 and 4 together with the data of the control bits coming from the outputs of drive 12. Blocks 3 and 4 produce a match signal or inconsistencies of the read information with its control category in the form of the level of a logical one or zero. The adder 10 performs the function of decoding (M + 1) -th digit · address, for which the input 28 is the logical level "1". The signal (MM) -th digit of the address and its inversion, arriving at the second inputs of elements 5 and 6, respectively, allow the passage of signals from the outputs of one of blocks 3 or 4. At the outputs of elements 5

five

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6

and 6 in the absence of a single error in the read information or in the absence of a sample of drives 1 or 2. there is a logical level "1", and in the presence of an error the level of logical "O" is formed. At the outputs of block 11, signals are generated corresponding to the (M + 1) -th digit of the address and its inversion, since block 11 collapses modulo two M from (M + 1) address bits and a check digit. The incoming to the second inputs 22 and 23 of adders 8 and 9 from the input and output of the adder 10 (M + 1) -th digit and its inversion (i.e., the checksum modulo two of one digit and its inversion) are compared with the signals arriving from the outputs of block 11. In case of disparity, adders 8 and 9 form the logical level "1", corresponding to the correct operation of the device, and if equivalent, logical "O". This controls both the correctness of the reception of the address code, and the health of decoding the additional (M + 1) -th digit of the address by the adder 10, because if the address code does not match its own control digit or if the adder 10 fails at the output of both or one of the adders 8 and 9 there is a logical zero level.

If there are 7 levels at the inputs of the AND-OR-NOT element, the logical signal “True” is formed as a logical level “0” at the output 17 of the device.

If there is at least one logical "0" on one of the inputs of the AND-OR-NOT 7 element at its output, i.e. the output 17 of the device, the signal is generated "Invalid" in the form of a logical "1".

If none of the drives 1 and 2 'is selected (inputs 15 and 16 are at a level that does not allow reading), then at the first and second inputs of element 7 there is a logical "1" level and at the output 17 a logical level "0" is formed Signal "True".

Drives 1,2 and 12, blocks 3,4 and 11 convolution modulo two, elements AND 5.6, element AND-OR-NOT 7 and adders 8-10 can be used as a unified module for constructing permanent storage

devices with self-control are larger than in the described device information capacity, for example, 1024 eight-bit words.

5 Technical and economic advantages of the proposed device consist in the fact that it provides control of address circuits and it can be used as a unified module to create two permanent storage devices with self-control based on large integrated circuits.

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Claims (1)

Claim A self-monitoring permanent storage device containing drives, modulo-two convolution main units, OR elements and OR-NOT elements, and the address inputs of the drives are connected to the outputs of the corresponding OR-NOT elements, inputs _{5 of} which are address inputs of the device, the outputs of the drives are connected to the information inputs of the corresponding> modulo convolution main blocks, whose outputs are connected to the first inputs of the corresponding OR elements, the second input of the first OR element is connected to the enable input of the first drive sample the second OR element is connected to the sampling resolution input of the second drive, characterized in that, in order to control the address circuits and simplify the device, it contains a counter drive There are additional data, an additional module of convolution modulo two, modulo-two adders and an AND-OR-NOT element whose first and second inputs are connected to the second inputs of the first and second OR elements, respectively, whose outputs are connected to the third and fourth inputs of the AND- OR NOT, the fifth and sixth inputs of which are connected respectively to the outputs of the first and second modulo-two adders, the first inputs of which are connected respectively to the forward and inverse outputs of the additional convolution unit modulo two, the second input of the first th adder modulo two · connected to the first input of the third adder modulo two and the entry permission sampling first reservoir, the second 9B455 modulo Ί the input of the second adder two is connected to the output of the third modulo-two adder and the enable input of the second drive, the address inputs of the additional convolution unit modulo two are connected respectively to the address inputs of the drives, and the first control input is connected to the output of the corresponding element OR NOT, whose input It is connected with the second control input of the additional convolution unit modulo two and is the control input of the device, the address inputs of the control data accumulator are connected 15 respectively about to address inputs eight devices, the sample input is connected to the zero-potential bus, and the outputs are connected respectively to the first control inputs of the basic convolution blocks modulo two and the "inputs of the corresponding OR-NOT elements whose outputs are connected to the second control inputs of the convolution main blocks modulo two.