SU1274005A1 - Read-only memory with self-checking - Google Patents

Abstract

The invention relates to storage devices and can be used in the construction of permanent storage devices of various structures with built-in controls. The purpose of the invention is to improve the accuracy and efficiency of the device by introducing control, information and address switches, their communication with known device blocks and circuit design of control unit 7. The device contains the accumulators 1,2 and 3, the address switch 4, the control switch 5, the control block 6, the parity formation blocks 7,8 and 9, the information switch. 10, the device's address input II, device control inputs 12-17, device masking input 18, device control input 19, device output 20. Block -6 control contains a group of elements OR NOT, adders-elements H-OR-NOT and an inverter. The introduction of switches and the circuit design of the control unit made it possible to verify the information and address paths when the information structure was changed and to improve the accuracy of determining the location of the fault. 1 hp ff, 2 silt, GCHE “4 ;; About o ate lb.4 10

Description

The invention relates to storage devices and can be used in the construction of permanent storage devices (ROMs) of various structures with built-in controls,

The aim of the invention is to improve the accuracy of control and increase efficiency.

Figure 1 presents the functional diagram of the proposed device; figure 2 is a functional diagram of the control unit,

The device contains drives 1, 2 and 3, address switch 4, control switch 5, control block 6, parity forming blocks 7, 8 and 9, information switch 10, device address input P, device control inputs 12-17, input 18 masking device control input 19, device output 20.

The control unit (figure 2) contains a group of elements OR-NOT 21, adders 22 - 26, elements AND-OR-NOT 27, 28 and inverter 29.

The device works as follows.

Mode with increasing information width of the device. In this case, the address code supplied to input 2, in the presence of enabling signals at the control inputs 12, 13 of drives 1 and 2, gives the information code to the inputs of blocks 7 and 8.

Their other inputs from the outputs of the information switch 10 receive test bits stored in drive 3. The number of information bits of drive 3 is less than the size of drives 1 and 2. (it must first of all store only check bits). The number of words or the address width of accumulator 3 can be greater, equal or less than the address width of accumulators 1 and 2. A smaller number of words in accumulator 3 is a more general case, since it is reduced (when the structure of the device changes in the direction of increasing the number of words). ) cases of equality or more words.

If there is a signal at the input. 13 n outputs of accumulator 3 appear control bits corresponding to several informational words of accumulators 1 and 2. Selection of the required

the check bit is produced by means of an -address signal, which is fed to one of the control inputs of the switch 10, to the other control input B. of which is given a signal that takes it to the active state. In adder 8, modulo two summation occurs with its control bits.

The result in the form of level 1 in the absence of error or O, if any, passes through elements 21 to the inputs of the AND-OR-HE element 28.

In the presence of external control

the address of the address arriving at the input, the adder 9 collapses modulo two with this check bit of the address code bits that pass through the address switch 5

allowed by the signal from input 15. The remaining bits of the address are added modulo two by the adder 26 of block 6. The results of the summation from the output of block 9 are sent to the first, and from the output

Yes adder 26 through an element OR-NOT 27, which is opened by a signal from input 15 - to the second input of adder 22 of block 6. At the output of adder 22 a level O

in the absence of 1

 if there are errors in the adres code, to the external inputs of block 6 in

This mode gives signals that form - in convolution, respectively, 1 and O. Therefore, at the outputs of the adder

24 and 25 levels of O are formed in the absence and 1 in the presence of errors in the address code. When applying to the input 18 of the resolving potential at the output of the element AND-OR-NOT 28 is formed

control signal that characterizes the health of the information and address tract: 1 - OK, malfunctioned.

Claims (1)

In the absence of an external control bit of the address, its value is entered into the drive 3 when programming. The corresponding output of the switch 10 is connected to the input 17. The choice of the required check bit of the address is made similarly to the choice of the check bit of information. In this mode, despite the absence of an external reference bit, the equality of the information path and the address-information switch is checked. In the absence of an external check bit and a limited information volume of the accumulator 3, it is still possible to monitor the information path. For fl. Go to -in 18 serves the forbidding potential, which masks the results of convolution in adders 24 and 25, I AND-OR-HE 28 forms on you during 19 a sign of good condition (malfunction) read out from information drives 1 and 2. When working with an increased information width, without control, with preservation of the total number of words defined by the address width of drives 1, 2, an information code is entered into drive 3. The information outputs of the device are the outputs of drives 1, 2 and information switch 10. Input 16 is supplied with a potential allowing the passage of the address code to the address inputs of drive 3, input 17 is the potential that switches the outputs of switch 10 to the active state, to input 15 potential allowing the address code to pass through the switch 5 to block 9. When the address code is fed to input 11 and the sampling signals to inputs 12 and 13, the information code goes to the outputs of drive 3. Changing the format of the word read from drive 3 is performed using the switch 10, the first control input of which receives the address bit. Information signals are supplied to blocks 7 and 8, from which the modulo-two results pass to the inputs of the adder 24 of block 6. To the other input of the adder 24 from the output of the adder 22, the modulus two signals from the output of block 9 and the address bits minimized in the adder 26 that did not pass through the switch 5. When applied to the 19 level 1 input, the adder 24 generates a check bit of the information and address codes at the device output. Thus, in this mode, an increase in information capacity is provided, as well as a check bit is formed, which accompanies the information to be compiled and to increase the control accuracy when working with receivers of readable information. When working with an increased information bit, without control. with a decrease in the total number of words defined by the address width of accumulator 3, the device’s information outputs are outputs of accumulators I, 2 and 3. A potential allowing the passage of an address code to the address inputs of accumulator 3 is fed to input 16, the potential transmitting the switch 10 exits to the off state, to input 15 a potential that allows the information code to pass through switch 5 to block 9 and sets output 27 of block 7 to level O. At the inputs of adder 24, the results of convolution from the outputs of blocks 7, 8 and through the adder 22 and the HE element 27 from block 9. Thus, the reading of information is also accompanied by the output from the output 20 of the check digit. The operation mode of the device associated with an increase in the number of words or address width of the device, the additional address bit and its inversion are fed to the sample inputs of drives 1 and 2, inputs 17, and one of the external inputs of block 6, respectively. II and inputs of sample 1 and 2 of drives, the information code is read from the selected accumulator 1 or 2 and fed to the output of accumulator 3 to the inputs of blocks 7 and 8. The check bits are read from. accumulator 3 at the address coming through switch 4, opened by a signal from input 1 6 and directly from input 11, Since the number of layers in accumulator 3 is less than in accumulators 1 and 2, control bits for several words stored in accumulators x 1 and 2 The selection of the corresponding control bit is made by the jmmutator J O using the address bits supplied to its control inputs, while the first control input controls the selection of one of the groups of information inputs of the switch 10, Cig al from the input 17 controls the disconnecting switch 10 outputs, respectively. Blocks 7 and 8 fortify the serviceability attribute of the read information that arrives at the AND-OR-NOT 28 block of the 7 through the OR-NOT 19 or 20 element corresponding to the selected drive. A part of the address code bits passes through the control unit 5 opened for them by a signal from input 15 and enters the inputs of block 10. Another group of address bits is minimized modulo two in the adder 26 of block 6. and through element 27 passes along with the result convolutions in block 6 to the inputs of the adder 22. If there is an external control bit of the address supplied to the input 19, the output of the adder 22 will form the sum modulo two of this check bit and a group of address bits (without an additional address bit). This sum, equal to the inversion of the additional address bit, is summed modulo two with the inversion of the additional address bit received by the group of external inputs 4 of block 6, in the adder 24, the direct value of the additional bit received by the group of external inputs 3, is summed up in an adder 23 with a direct value of an extra bit coming from element 27; If there are no errors in the address path of the outputs of adders 23 and 24, O is formed, the incoming element I-IPI-NE 28, which forms a sign of correctness of information and ery chains. In the absence of an external check bit, its value is entered into the drive 3. By using the address bits present at the control inputs of the information switch 10, both the check code of the information code and the check bit of the address code are selected. Thus, the information path and the switch 10 of the device are verified. When working with an increased address resolution, without control, an information code is entered into drive 3. The number of words in the device is equalized with the number of words in the accumulators 1 and 2. Thus, when submitting the address code from the device, the information word is counted, the number of bits of which is increased due to the information capacity of the accumulator 3, When the device operates as a module for building ROM information capacities and structures it is used as a depagafrator of additional address bits, for which 1 5. e to input 17 serves the potential prohibiting the passage of a group of address bits to drive 3, Drive 3 of another module is used as a ROM of control bits of information codes, Outputs of drive 3 (decoder for additional address bits) are connected to external inputs of blocks 6 of both modules. The operation of the ROM occurs in the same way as described above with control at an increased address bit size and does not require additional equipment. This provides both control of the address codes and information, as well as control of the decoder for the additional address bits. Thus, the proposed device provides verification of the information and address paths when the information structure changes, forming the check word readable words, which allows to increase the completeness of control and the accuracy of determining the location of the malfunction when working together with subsequent cascades of information processing. Claim 1, Permanent self-monitoring memory device containing primary and secondary drives, the basic and additional blocks of the parity drivers, the control unit, the inputs of the first group of which are connected to the inputs of the sample of the main drives, and the inputs of the second group - with the outputs of the main and additional blocks of the parity drivers, the outputs of the control unit are the control outputs of the device, the address inputs of the main and additional drives are the address inputs of the device, the outputs of the main and additional drives are the information outputs of the device, the inputs of the main blocks of the imager th parity connected to outputs of the respective osnovngh storage ring, teley about tlichayuschees in that in order to control and accuracy povsh1eni effective capacitance, it was formulated. there are control, information and address switches, and the information inputs of the address switch 71 connected to the address inputs of the device, and the outputs to the additional address inputs of the additional drive, the outputs of which are connected to the information inputs of the first and second groups of the information switch and the information inputs of the first group of the control switch, the information inputs of the second group of which are connected to the address inputs of the device , and outputs-- with additional inputs of an additional block of parity drivers; the control input of the control switch is connected to the first control input The control unit, the second control input of which is the device masking input, is fourth, and the group of control unit inputs is connected to a group of device address inputs, one of which is connected to the first control input of the information switch, the output group of which is connected to additional inputs of main units the parity drivers, the control inputs of the information, address and control switches and the control unit are the fill inputs of the device, 2, The device according to claim. 2, characterized in that the control unit contains a group of elements OR NOT, the parity generators, the elements NOT, .740058 AND-OR-NOT, OR-NOT, and the inputs of the first group of elements OR-NOT groups are the inputs of the first group of the control unit, -a inputs of the second group of 5 elements OR-NOT groups and the first the input of the first driver is the input of the second group of the control unit, the first input of the OR element is NOT the first control input 10 control unit, and the first input of the AND-OR-NOT element is the second control input of the control unit, the second and third inputs of the AND-OR-NOT element are connected to the outputs of the second and third form of parity, and the group of inputs of the AND-OR-NOT elements - with the outputs of the elements of the OR-NOT group, the outputs of the element of the AND-OR-NOT and the fourth parity generator are the control 20 outputs of the block, the input of the fourth parity generator is connected to the input of the second parity generator and the output of the NOT element, whose input is connected to the input of the third form of parity bodies and the output of the first parity generator, the second input of which is connected to the output of the OR-NOT element, the second input of which is connected Nine with the release of the p shaper 0 parity, groups of inputs, first, the third, fourth, and fifth parity formers are the inputs to the third and fourth groups of the control unit, (Rez. 2