SU942142A1 - Redundangy multichannel storage device - Google Patents

Description

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The invention relates to storage devices and can be used in the construction of storage devices of highly reliable computing systems. ,

A well-known redundant multichannel storage device containing the address register, address decoders, drives, word registers, the circuit is equal to-. the code, the AND element, the control unit, the Q element AND THE LI, the group of elements AND by the number of drives, the output register, the additional registers of the word by the number of drives and the bit pattern by. the number of drives fl.15

The drawbacks of the device are high hardware costs and low reliability.

The closest technical solution to the proposed one is a redundant multi-channel storage device containing memory modules, an address register consisting of the modup number register, the output of which is connected to the input of the Moioynfl number decoder and the register of the cell whose output is connected to the inputs the address registers of the module drives, the output register connected to the control unit, the module switching unit (containing the module status register, and the xmmutator), one input of which is connected to the output of Desh Frat (modup numbers, and the output - to the inputs of the storage modules, the correction unit, the outputs of which are connected respectively to the input of the module switching modules in the BUxofbtoMy register, and the inputs to the outputs of the OR block (assembly) inputted into the device, whose inputs are connected to the outputs registers of words of cumulative modules 2.

The disadvantages of this device are low reliability, since it requires significant equipment costs to implement a complex algorithm for obtaining reliable information in the presence of a defect in the memory module and, 1F3939 Me, the hard assignment of the numbers of the memory modules to the address reduces the redundancy efficiency, as well as low speed, since in the presence of failures in the memory modules, the time for retrieving information increases dramatically. The circuit of the invention is to increase the reliability of the device. The goal is achieved by the fact that in a redundant multi-channel memory device, containing in each channel, memory blocks, the address, information and control inputs of which are respectively the address and information inputs and record entries of the device, the registers of memory blocks, the ID element of which connected to the outputs of the memory block, the decoder, the status register and the switches, whose inputs are connected respectively to the outputs of the status register, are introduced in each channel a group of circuits compared to and, the groups of elements AND, the first and second predictive blocks, the comparison circuit, the majority elements and the encoder, the first inputs of the AND elements of the first group are connected respectively to the outputs of the comparison circuits of the group, the first inputs of which are connected respectively to the outputs of memory number registers, informational inputs of which are connected to informational inputs of 1 memory locations, whose access inputs are connected to the outputs of the AND elements of the first group | the second inputs of the comparison circuits of the group are connected to the inputs of the decoder, the address inputs of the memory blocks and the control inputs of the switches, the first inputs of the elements AND of the second group are connected respectively to the outputs of the decoder, and the outputs respectively to the inputs of the strobe registers of memory blocks First , the second and third inputs of the second logic unit are connected respectively to the outputs of the switches and the inputs of the first majority element, the inverse output of which is connected to the fourth one, the second input of the second logic unit ka, the outputs of which are connected respectively to the control inputs of the first logic unit, the inputs of which are connected to the outputs of the OR element, and the output is connected to the first input of the comparison circuit and the first input of the second major element, the second input of which is connected to the second input of the comparison circuit the output and inputs of the first majoritarian 2 rtOro of the element are connected respectively to one of the inputs of the encoder, the other inputs of which are connected respectively to the other inputs of the encoder and the outputs of the comparison circuits of all channels & the second and third inputs of the second major element of each channel are connected respectively to the inputs of the second major elements of other channels, the second inputs of the first and second groups AND, the outputs of the saffer and the second major elements VL5pots, respectively, the access input, the gate input, the output outputs of the failed channels and the device information outputs . In addition, each first logic block is made containing prohibition elements and OR elements according to the number of device bits, the first inputs of the OR elements are connected respectively to the outputs of the prohibition elements, the inverse inputs of which and the second inputs of the OR elements are respectively the first and second control inputs of the first logical block, the inputs of which are the power of the direct inputs of the elements of the prohibition, and the output - the outputs of the elements OR. Moreover, each second logic element is made containing AND elements, the first inputs of which are respectively the first, second and third inputs of the block, the second inputs of the AND elements are combined and are the fourth input of the block, the outputs of the AND elements are the outputs of the block. FIG. 1 shows a functional diagram of the device; in fig. 2 and 3 are functional diagrams of embodiments of the first and second logical blocks, respectively; in fig. 4-functional scheme of the encoder. The device consists (Fig. 1) of the first 1, second l. and the third 1 identical channels, each of which contains memory blocks, registers 3i-3 numbers of memory blocks, group comparison circuits 4jj-4 yj, the first and second 6, -6y, the group of elements AND, the decoder 7, the element OR 8 , the first logic block 9, the U comparison circuit, the first major element 11, the state register 12, the switches, the second major element 14, the second logic unit 15 and the encoder 16. In FIG. 1, the address inputs 17 are marked, the information inputs 18 and the outputs 19 , gating inputs 20, access inputs 21, device recording inputs 22, switch outputs c, the outputs of the comparison circuits and the outputs of the indications of the failed device tapes. The first logical block (FIG. 2) contains prohibition elements 26 and OR 27. The second logical block (FIG. 3) of each channel contains AND elements with outputs, respectively. FIG. 3 denotes outputs and ZOE second logical unit. The encoder (Fig. 4) contains the elements And 31-33. Register 12 (Fig. 1) is divided into and sections, where and is the number of blocks 2 pa mi in each channel of the device. The device works as follows. Consider a variant of the device with four memory blocks (Fig. 1) and, accordingly, four three-bit sections of the register 12. First, when all the memory blocks 2 -2j (Fig. 1) are intact, the device is initially configured, i.e. sending in all channels 1 units to all bits of all sections of the register 12. The addresses of the blocks 2, the memory are recorded as follows. Two (for example, older) bits of the address input 17. Each channel 1 is fed to the input of the decoder 7, at one of the outputs of which a signal is generated, and unlocks the corresponding element AND Q 6. At the input 2O, a signal is generated which passes through the corresponding element AND 6, arrives at the gating input of one of the registers, in which the assigned address for the corresponding block is written to the information inputs of one of the registers 3 -3 from two (for example, older) input bits 18. Thus, the physical block numbers 2 memory are not fixed to their address, at the same time sections of register 12 are fixed to addresses of blocks 2 by connecting their outputs to inputs of 1Y-13l switchboards, which pass signals to their outputs from corresponding inputs. in accordance with the contents of the two higher-order address bits. Information is recorded into the device as follows. Signals are provided to inputs 21 and 22, and an address code and information for recording, respectively, to inputs 17 and 18. The older two bits of the addresses address memory block 2, while the remaining bits indicate the cell address in memory block 2. The older two bits of the address are fed to the second inputs of the comparison circuits, the first inputs of which receive codes from the corresponding registers 3i-3. The output signal produces only one of the schemes 4-4 and unlocking the corresponding element AND,. Thus, the access signal is sent only to that of the blocks, in which information is recorded in the corresponding cell. When reading information, the signal at input 22 is not generated, and the information from the corresponding cell of the corresponding block 2 -2 is received through the element OR 8 to the information. block 9 input. When the blocks in each channel 1 are healthy, there are one units in all bits of register 12 before accessing devices, so in this case, single signals are sent to the corresponding inputs of the majority element-11, block 15 and encoder 16 from the switch outputs. On the inverse output of the majority element 11 and on the corresponding. In this case, there is no signal at the input of block 15, and a signal is present at the direct output of element 11 and the corresponding input of the encoder 16. In the absence of a signal at the inverse output of element 11, elements And (Fig. 3) are closed, so signals are absent at the outputs of block 15 (Fig. 1) and, respectively, at the control inputs of block 9. At the same time, information from the information input of block 9 is fed to its output and, respectively, through the second major element 14 to the output 19. It should be noted that at the inputs and outputs of the element 11 there are ODD signals, and on each of the inputs and outputs of the element 14 there is a multi-bit information. In addition, information from the output of the BPO: ku 9 arrives at the first input of the circuit Yu comparing its channel .l and the corresponding neighboring channel 1. At the same time, if, for example, in the first channel 1 in blocks 2 (-2j, a failure occurs then, at outputs 24 and 242. DF circuits in the first 1 and in the second 1 canaps, signals are generated that arrive at the sixth and seventh inputs of the encoders 16 in all the canapes 1–3 of each canape

,, In encoders 16, the epithets of AND 3133 (FIG. 4) are opened by the first input with a signal from the output of the majority epement 11, and by the second output signals from the outputs 2ЗУ-23 3 (FIG. 4) of the switches, (FIG. 1). On the third and fourth input, only element I 31 (Fig. 4) is opened with signals from outputs 24. and S (Fig. 1) comparing the first 1 and second 2 channels. Thus, in the event of a failure in the first channel 1, a signal is generated only at output 25 (FIG. 1) of the sign of failed channel 1. Similarly, the signal is generated at output 25, j (25a) if one of the blocks 2j-2j in the second 1 fails ( third l) channel. After that, the code HE is entered into the corresponding section of register 12, where O means the failure of a particular block 2 in the first channel l-f.

If, when referring to block 2 (Fig. 1), the second canape l fails, then there is some probability

generating a signal at output 25 instead of outputting 2 5o a sign of a failed channel 1l. At the output 25, the signal is not generated, since zero from the output of the first discharge of the first section of register 12 through the switch 13 (output 23) is fed to the second input of the And 31 element and prohibits its triggering. The generation of a signal at the output of 25 in the output of the output of 252 occurs if in the second channel l. a failure of the same type and in the same bit occurs, and in the first channel 1. Otherwise, the signals are also generated at the output 25a; and at the output of 25 l in the canal D channel X | -1z If a failure in the first channel 1 and produces a signal (O or), which coincides with the true signal in the healthy channel Ij, and in the second channel 12. a failure occurs that generates the opposite signal (or ), the signal is generated at output 25. Thus, the presence of a second failure is detected promptly, and for reliable localization of the failed channel X (, 1- or 1, per-channel verification is required, and the address at input 17 indicates both the block address and the cell address in block 2, -2, which gave birth to marriage, if In the first section of the first l channel and the second l channel, a code OO1 is set in the first section of the register 12. In this case, when accessing the blocks 2, a signal appears only at the output of the switch 13j. And 28 (Fig. 3) and only at its output 29 in each channel C there is a signal, and in the first channel If this signal through the second output ZOa. (Fig. 3) of block 15 (4 mg. 1) is fed to the control input of the block 9 and, respectively, to the first inputs of the elements OR 27 (FIG. 2), while for all bits, units are generated at the output of block 9 (Fig. 1). In the second channel 1, the signal through output 3Q, (Fig. 3) of block 15 is fed to the control input of block 9 and, accordingly, to the inputs of the prohibition of elements 26 ((. 2), therefore in the Second Canape 1 (Fig. 1), the output of block 9 zeros are issued for all bits. In the third channel 1h, output 29 (Fig. 3) is not active, therefore signals at the outputs of block 15 (Fig. 1) are absent, and at the output of block 9 there is a code read from block 2 that goes to outputs 19 of all channels, (fig. 1). since at their inputs, connected by inter-channel communication outputs of the first 1 and second 1 channels are present with responsible units and buy.

No signals are generated at the outputs, since there is no signal at the inverse output of element 11 (Fig. 1) and, accordingly, at the first inputs of And 31-33 elements (Fig. 1) of the encoder 16 (Fig. 1).

To allow test control of the failed channel when the device operates per channel, the addressing of the failed, for example, memory 2, is changed, so that this failed bpoc 2 is addressed to the second section of the i2 register.

Claims (2)

The feasibility of the proposed device lies in the fact that it maintains operability with multiple failures in memory blocks, and the read time of information in the presence of failures does not increase, thereby increasing its reliability and performance compared with the prototype. Claim 1, Redundant multi-storage device containing in each canape memory locations whose address, information and control inputs are respectively address and information inputs and device write inputs, memory block number registers, OR element whose inputs are connected to the outputs of the memory blocks, the decoder, the state register and the switches, whose inputs are among the same, respectively, with the outputs of the state register, which differs in that, with a circuit to increase the reliability of the device rather, it comprises in each settee group comparison circuits, groups of AND gates, first and second logic blocks, comparing circuit, majority elements and interposer, the first vhrdy member and the first group are connected respectively to the outputs of circuits comparing groups per) - stems inputs. which are connected respectively to the outputs of the memory register registers, the information inputs of which are connected to the information inputs of the memory blocks, the inversion inputs of which are connected respectively to the outputs of the AND elements of the first group, the second inputs of the group comparison circuits are connected to the inputs of the decoder, the address inputs of the memory blocks and the control the inputs of the switches, the first inputs of the elements of the second group are connected respectively to the outputs of the decoder, and the output. dy - respectively, to the gating inputs of registers of memory block numbers, first, second and third inputs of the second lagic block are connected respectively to the switch outputs and to the inputs of the first major element, the inverse output of which is connected to the fourth input of the second logic block whose outputs are connected respectively . to the control inputs of the first logic unit, the inputs of which are connected to the outputs of the OR element, and the output is connected to the first input of the comparison circuit and the first input of the second major 94 210 element, the second input of which is connected to the second input of the comparison circuit, the forward output and the inputs of the first major element are connected respectively to one of the inputs of the encoder, the other inputs of which are connected respectively to the other inputs of the encoder and the outputs of the comparison circuits of all channels, the first, second and third inputs of the second major e The elements of each channel are connected respectively to the inputs of the second, major elements of other channels, the second inputs of the first and second elements and the L groups of the encoders and the second major elements are the off input, the gating input, the output of the channel failure attributes and the device information outputs, 2. Device pop. 1, distinguished with. By the fact that each first logic block contains prohibition elements and OR elements - by the number of device bits, the first inputs of the OR elements are connected respectively to the outputs of the aianpeta elements, the inverse inputs of which and the second inputs of the} OR elements are respectively the first and second control the inputs of the first logical block, whose inputs are the direct inputs of the prohibition elements, and the inputs to the outputs of the OR elements. 3. The device according to PP, 1 and 2, of which there is the fact that each second logical element contains the elements AND ,. the first inputs of which are respectively the first, second and third inputs of the block, the second inputs of the elements AND the combination and are the fourth input of the block, the outputs of the AND elements are the outputs of the block. Sources of information taken into account at. examination 1. Author's certificate of the USSR No. 385319, kp. 11 C 29/00 1972. 2. Authors certificate, No. 439О20, cl. G 11 C 29/00, 1972 (prototype). Phage 2