SU841059A1 - Error-correcting storage device - Google Patents

Description

(54) STORAGE DEVICE WITH CORRECTION

ERRORS

one

This invention relates to memory devices.

It is known a memory device with error correction short to, using the method (2k4-1) -fold reservation with majority voting and consisting of 2k + 1 memory blocks, the same outputs of which are fed to the inputs of the majority elements "k + 1 of 2k + 1, corrective to errors 1.

. The disadvantage of this device is an excessive amount of equipment.

The closest in technical essence to the invention is a memory device containing storage modules, an address register consisting of a register of a module number and a register of a cell number whose outputs are connected to the inputs of the address modules of the storage modules, a word register whose outputs are connected to information inputs accumulative modules, the decoder of the module noupler, the outputs of which through the switching unit of the modules are connected to the control inputs of the accumulating modules, the elements OR, the inputs of which are connected s to the outputs of word registers of accumulative modules, block

correction, the outputs of which are connected to the inputs of the output register, and the inputs to the outputs of the OR elements, and the control unit 2.

The disadvantages of this device are the high hardware costs, leading to an increase in the cost of the device, and an increase in the sampling time when an error is detected.

The purpose of the invention is to simplify the device.

The goal is achieved by the fact that in a memory device with error correction containing drives, input number register, address register, decoder, OR element, correction unit, output number register and control unit, one of the outputs of the address register and the number input register are connected respectively to the address, and one of the informational inputs of the drives, the control inputs and informational outputs of which are connected respectively to the outputs of the decoder-and the inputs of the OR element, the output of which is connected to the input the correction block, one of the outputs of which are connected to one of the inputs of the output number register.

the control inputs of the drives are connected to one of the outputs of the control unit, the shaper of the control CHfins and the group of adders, AND and OR elements are entered, and the inputs of the shaper of the control signals are connected to one of the outputs of the input number register, and the outputs of the other informational drives of the accumulators and the first inputs of the adders the first group, the second inputs of which are connected to other outputs of the input number register, and the outputs - to the first inputs of elements AND of the first group, the outputs of which are connected to one of the inputs Combo OR groups whose outputs are connected to the inputs of the decoder, the first inputs of elements AND of the second group are connected to other outputs of the address register, and the outputs to other inputs of the elements of OR group and the first inputs of adders of the second group, the second inputs of which are connected to other outputs of the correction unit, and the outputs - with other inputs of the output number register; the second inputs of the AND elements are connected to the other outputs of the control unit.

The drawing shows a block diagram of a memory device with error correction having a multiplicity of t (t is an integer, with t 1).

The device contains the address register 1 consisting of the register of the accumulator number 2 and the register of the cell number 3, the input register 4 numbers, the driver 5 control signals, the first group of adders 6 modulo two, the first 7 and second 8 groups of elements AND, the group of elements OR 9 , the decoder 10, the control unit 11, the accumulators 12, the element OR 13, the second group of modulators 14 modulo two, the correction unit 15 and the output register of the 16th number. One of the outputs of registers 1 and 4 are connected respectively to the address and one of the information inputs of the drives 12. One of the outputs of block 15 is connected to one of the inputs of register 16.

The control inputs of the accumulators 12 are connected to one of the outputs of block 11. The inputs of the imaging unit 5 are connected to one of the outputs of the register 4, and the outputs to the other information inputs of the accumulators 12 and the first inputs of the adders 6, the second inputs of which are connected to the other outputs of the register 4, and the outputs with the first inputs of the elements And 7, the outputs of which are connected to one of the inputs of the elements OR 9, the outputs of which are connected to the inputs of the decoder 10. The first inputs of the elements And 8 are connected to the other outputs of the register 1, and the outputs to the other inputs of the elements OR 9 andthe first inputs of adders 14, the second inputs of which are connected to other outputs of block 15, and the outputs with other inputs of register 16. The second inputs of elements And 7 and 8 are connected to other outputs of block 11.

The storage device operates as follows.

When writing, the contents of the lower bits from register 4 are fed to the imaging unit 5, where, in accordance with the applied

Correctional (n, k) code forms pc to the control bits. Thus formed p check bits together with the contents p of the high bits of register 4 arrive at the inputs of adders 6, where the accumulator number 12 is formed. From the output of adder 6, if there is a control write signal, elements AND 7 and element OR 9 pass this information to the decoder 10, which selects the respective corresponding drive 12, and the lower bits of the memorized word from register 4, together with the check bits from shaper 5, are written into the cell of this drive 12 at the address set in the address register of this accumulator according to the register number of the cell number 3.

When reading information from the register of accumulator 2 in the presence of a read signal, the bit from the AND control unit is transmitted through the elements AND 8 and the OR 9 element is fed to the inputs of the decoder 10, where the accumulator 12 is selected and the address register of the selected cell the drive enters the address of the cell in which the read word is stored. The read word through the elements OR 13 enters the inputs of the block 15 correction, where

0, detection and correction of errors is performed in accordance with the correction ability of the correction code used for this purpose. Older nc bits of the corrected word, together with the contents of register 2, are fed to the inputs of adders 14, (which restore their true value. Minor bits of the corrected word from the outputs of the correction block 15, together with the restored nq bits of the higher bits from the outputs of adders 14 arrive at register 16.

Thus, the introduction of the pilot of the control signals, two groups of modulo-two adders, two groups of AND elements, and a group of p OR elements with the following:; moreover, the corrections that occur during storage of information without memorizing the check bits , which simplifies the error correction procedure, reduces the amount of equipment and the sampling time.

Claims (2)

Invention Formula An error-correcting memory device containing drives, an input number register, an address register, a decoder, an OR element, a correction unit, an output number register, and a control unit, with one of the outputs of the address register and the input number register being connected to the address and one of the information inputs, respectively. drives, control inputs and information outputs of which are connected respectively to the outputs of the decoder and the inputs of the OR element, the output of which is connected to the input of the correction unit, one of the outputs of which It is connected to one of the inputs of the output register number, the control inputs of the accumulators are connected to one of the outputs of the control unit, characterized in that, in order to simplify the device, it contains a driver of control signals and groups of adders, elements AND and OR, and the inputs of the driver of control signals are connected to one of the outputs of the input number register, and outputs to other information inputs of the drives and the first inputs of the adders of the first group, the second inputs of which are connected to other outputs of the input gist numbers, and outputs - with the first inputs of elements AND of the first group, the outputs of which are connected to one of the inputs of the elements OR of the group, the outputs of which are connected to the inputs of the divider, the first inputs of the elements AND of the second group are connected to other outputs of the address register, and the outputs to other inputs of the elements OR of the group and To the first inputs of the adders of the second group, the second inputs of which are connected to other outputs of the correction unit, and the outputs to other inputs of the output number register, repeat the inputs of the And elements connected to the other outputs of the control unit. Information sources, taken into account in the examination 1 US Patent No. 3458860, cl. G 06 F 11/10, 1970. 2. USSR author's certificate No. 618799, cl. G 11 C 29/00, 1976 (prototype).