SU892705A1 - Device for automatic measuring of dynamic characteristics of quick-action analogue-digital converter - Google Patents

Description

(54) DEVICE FOR AUTOMATIC MEASUREMENT

DYNAMIC CHARACTERISTICS OF POWERFUL ANALOG-DIGITAL CONVERTERS The invention relates to computing and electrical engineering and can be used to calibrate the ADC in the mode of changing the input signal. A device is known for automatically measuring the characteristics of analogue-digital converters containing successively a; a; a main digital setpoint unit and a first code-voltage converter, two comparison elements, a second code-voltage converter, a code processing unit, the first input of which is connected to the output of a controlled analog-to-digital converter, and the first output is connected to the indicator input, a linearly rising voltage generator, two keys, two triggers, five AND elements, and a sum and an additional digital setpoint block, with the output of the linearly increasing voltage generator connected to the first inputs of both comparison elements and to the first input of the first key, the second input of which is connected to the output of the first element I, and the output connected to the output of the second key and to the input of the controlled analog -digital converter, the output of the first converter code-voltage is associated with the second input of the first comparison element, the first input of the adder and the first input of the second key, the second input of which is connected to the second input of the second element, the second input of the adder, through the second code-voltage converter, is connected to the first input of the third element, and through the additional code-setting additional unit serially connected to the second converter, to the output of the fourth element, and the output of the adder connected to the second input of the second element of the equation, the outputs of both elements of the comparison are connected to the corresponding inputs of the first trigger, the output of which is connected to the first inputs of the first and second elements AND, the second The input of the first element is connected to the second input of the third element I and the first output of the second trigger, the second input of the second element I is connected to the second inputs of the fourth and fifth elements I and the second output of the second trigger whose input is connected to the second output of the code processing unit, the third output which is connected to the first input of the fourth element I, the output of which is connected to the input of an additional digital setpoint block, the second input of the processing unit of the codes is connected to the output of the third element I, and the third to the output of the fifth lementa And, the first input coupled to an output of the main unit digital statute ki EIJJ. However, using the known device, it is impossible to determine the dynamic characteristics of analog-to-digital converters with an arbitrarily varying input signal, since in this case it is impossible to calculate the signal increment for a known period of time — the conversion cycle time. The purpose of the invention is to expand the functional capabilities. The goal is achieved by the fact that the device for automatic measurement of dynamic characteristics of high-speed analog-digital converters contains a base set block, a code voltage converter, two comparison elements, a code processing block, a registration block, the output of the digital set block being connected to the transducer input code - voltage and to the first input of the processing unit, the second input of which is connected to the first output of the controlled analog-digital converter, the first output of the block brabotki codes coupled with the first. the input of the registration unit, the first inputs of the comparison elements are interconnected, a block for selecting the operating mode, a zone setting unit and a matching element, a driver are inserted, the code-voltage converter output is connected to the input of the zone setting unit, the outputs of which are connected to the second inputs of the elements compare the outputs of which are connected to the first and second inputs of the coincidence element, the third outputs through the driver 5 are connected to the second output of the controlled analog-to-digital converter, the third output of which dinene with the third input of the coincidence element, the fourth input of which is connected to the first inputs of the comparison unit through the mode selection unit, and the output is connected to the third input of the code processing unit, the second output of which is connected to the first input of the digital setpoint unit, the fourth input is connected to the second output of the last and to the Start bus, the input of the controlled analog-digital converter is connected to the first inputs of the elements and the input signal bus, and the second input of the registration unit is connected to the third Mu output code processing unit. In addition, the code processing block contains two forwarders, three flip-flops, two counters, a code entry node, a generator, an OR element, a reversible counter, a code comparison node, two AND elements, a register, and the first block input is connected to the first input of the code recording node, the second input of which is connected to the output of the OR element, and the output through the reversible counter is connected to the first input of the code comparison node, the second input of which is connected to the register output, and the output to the first inputs of the first driver and the first element AND, the second input to expensively connected to the generator, the third input is to the first input of the second element Nick the output of the first trigger, while its first output is connected to the first input of the counter, and the second output is connected to the counting input of the reversing counter, the summing input of which is connected to the direct output of the second trigger and to to the second output of the block, and the input of the subtraction is connected to the inverse input of the second trigger, the single input of which is connected to the output of the second element I, and the zero input to the zero inputs of the first and third triggers, to the first input p The driver and the output of the first driver, the second input of which is connected to the fourth input of the block and the first input of the second counter, the second input of which is connected to the third input of the block and the single input of the third trigger, its output is connected to the second output of the block, and the second input of the first counter The first 5 output of which is connected to the first output of the block, and the second output is connected to the second input of the second element AND and the first input of the OR element, the second input of which is connected to the single input of the first trigger, the second input regis pa and through the second driver - with output of the third flip-flop, said third input Dr. Regis connected to the second input unit, the output - to the second input code comparing unit. Fig. 1 shows a block diagram of a device for automatically measuring the dynamic characteristics of high-speed analog-to-digital converters; in fig. 2 time diagram. The device contains a code-voltage converter (PKN) 1, a zone setting unit 2, a controlled analog h-digit converter (LS1 3, a match element 4, comparison elements 5 and 6, a code processing block 7, a registration block 8, a digital setpoint block 9 , driver 10, mode selection block 11, code processing block consists of drivers 12 and 13, flip-flops 14, 15, 16, code entry node 17, reversible counter 18 of code comparison node 19, AND elements 20 and 21, register 22, element 23, generator 24, counters 25 and 26. At the output of the digital-analogue trans. Overvoltage 1 forms a voltage and, which, through the zone setting unit 2, enters the inputs of the comparison elements 5 and 6. At that, the input voltage of the element 5 is UQ -t-AU, and the input of the element 6 is UQ -db. It is comparable to the static error of the controlled ADC, i.e. very little. The second inputs of elements 5 and 6 of the comparison and the input of the controlled ADC are input either deterministic or random. It is necessary that this signal repeatedly passes through a given zone in order to obtain the required number of samples. This imposes certain limitations on the random input signal, in particular the lower bound of the spectrum of this signal must be sufficiently high. In order to increase the accuracy in the device, elements are used compared with memory and the third output of the controlled ADC is connected via the I 5 shaper to the third inputs of the comparison elements. The shaper is introduced in order to precisely combine the ADC reference time with the moment of comparing the comparison elements. In this case, a pulse is actually taken from the third output of the ADC, which appears somewhat earlier than the time of reference, for example, the start pulse of the ADC. The device works as follows. On the Start command, in block 9 of the digital setpoint, a code is set corresponding to the starting point of the input signal range at which measurements will be made. At the output of the transducer 1, a voltage, Ho-Elements 5 and 6, appears, and the matching element 4 forms the input signal monitoring system. The ADC performs multiple measurements. If at the time of issuance of the code. (when a pulse of the Output of data appears) of the monitored ADC, the input signal falls into the 2li zone, then unity appears at the output of the 4th element. By this signal, the output code is rewritten into the register 15 of the code processing unit 7. The UQ code pre-recorded in block 7 is subtracted in this block from the output code of the controlled ADC. The code difference is the ADC error in dynamic mode. If a deterministic signal acts at the input of a controlled ADC, for example, a linearly varying voltage, then in this case multiple measurements are made and their results are averaged. As a result, an average value of the error of the controlled ADC is obtained in the dynamic mode at a given rate of change of the input signal at a given scale point. This value is recorded in the registration unit 8, after which the device goes to the following UQ value and repeats the measurements, etc. If the input of the controlled ADC acts random input signal. In addition to the code reading and averaging functions, the code processing unit will perform more complex operations, such as selecting the maximum error or obtaining the error distribution function, etc. Obviously, the proposed device works with a random input signal, since it doesn’t matter whether the input signal enters the 2 jSi zone from above or below (J, if only this moment coincides with the moment of appearance of the pulse Data output. I Consider the device operation according to the Time Diagram (FIG , 2). The input signal, generally random, arriving at the inputs of the elements of the test, repeatedly passes through the zone 2. E. The value of this zone can be commensurate with the sensitivity threshold of the elements of the comparison, i.e. very small. controlled by ADC with an by the momentum logging at the input. The pulses of the moments of counting coinciding with the moments of transition of the analog storage unit to the storage mode are produced (5 request for comparison elements, which memorize their state at these moments. Coincidence can be very accurate, since the aperture times of the elements of comparison and analog the storage unit is commensurate and can be fractions of a nanosecond. The device operates in this mode until the time of the poll of the comparators coincides with the time of passage of the input signal through the zone, For example, the time t in Fig. 2 At this point, logical units appear at the outputs of the comparison elements and, entering through element 4, matches in the code processing block allow the code to be written from the output of the controlled ADC to the register at time point -tj since this code corresponds to the value of the input signal at time T. Thus, the proposed device selects only a few of all moments of reference, which reduces the speed of the circuit. However, this disadvantage does not play a primordial role, and since the proposed device is designed to determine the dynamic characteristics of high-speed ADCs, the moments t will appear quite often. Let us consider in more detail the operation of block 7 digital processing. The measurement starts on the Start signal, which resets the triggers 16, 15, 14 and the counters 26, 25. The signal from the output of the trigger 14 prevents the pulses from the generator 24 from passing through the coincidence element 20. At time point b, a unit appears at the output of element 4, which converts flip-flop 16 into one state and writes 58 to counter 26. This difference is fed to a driver 13, at the output of which a short pulse is formed. The code from the output of the controlled ADC is rewritten to the register 22, the trigger 14 is transferred to the unit state, allowing the passage of pulses from the generator 24 to the counting input of the reversing counter 18 and to the counting input of the counter 25. Simultaneously, a pulse from the output of the imager 3 through the element OR 23 set The code using the code entry node I7 is written to the reversible counter 18, which immediately starts working on the subtraction. The reversible counter code is compared with the register code 22 using the code comparison node 19. Let's say the register code is 22 more. The counting is performed until the group of bits of the counter 25 is inaccurate. At the moment of overflow, the pulse from the output of this counter through the element OR 16 again writes the original code into the reversible counter. This impulse, the passage through the coincidence element 21, translates the trigger 15 into a single state, thus providing the addition mode of the reversible counter 18. The counting begins again. When the codes are equal, the zero signal from the output of the code comparison node 19 prohibits the passage of pulses from the generator through the coincidence element 20. This signal, via driver I2, triggers the triggers 14, 15 and 16, i.e. all the main nodes are again transferred to the idle state of the pulse from the output of the coincidence element of device 4. When the second pulse from the output of element 4 of coincidence arrives, everything progresses in a similar way, and in the counter 25 the measurement results are summarized. The capacity of the counter 26 is selected in accordance with the number of measurements that need to be made at a given value of U. If this counter overflows, the digital setting block 9 sets the code corresponding to the new value) Uo- At the same time, the average error value of the monitored ADC is output from the output of the counter 25. in dynamic mode at a given point of the scale. After this, a new measurement cycle is performed with the new U. Obviously, with this implementation

The processing unit of the codes at the input of the controlled ADC should operate a deterministic signal having approximately the same rate of change at time t. With the random nature of the input signal, the code processing unit 7 should be constructed differently, although its basic nodes will remain the same. For example, in block 7 nodes may be present to select the maximum error, etc.

When determining the dynamic characteristics of an ADC in many cases, especially with a random input signal, it is necessary to determine the characteristics separately at positive, negative, and randomly varying rates of change in the input signal.

To provide this opportunity, a mode selection block 11 is added to the proposed device, containing a series-connected differentiating circuit and a null organ. If at the moment t the rate of change of the input signal has the desired sign, then the unit from the output of block 11 permits the operation of the device.

Thus, the invention makes it possible to determine the dynamic characteristics of an ADC directly under operating conditions or in the mode closest to these conditions.

In addition, due to the accurate synchronization of the moments of reference with the moments of the survey of comparison elements, the measurement accuracy is improved. The use of elements of comparison with memorization makes it possible to virtually eliminate the effect of a change in the delay time of comparison elements on the measurement accuracy. In the known device, such a mode of operation is synchronous while maintaining accuracy.

The use of a mode selection block allows the functionality of the proposed device to be expanded.

Claims (2)

Invention Formula . A device for automatic measurement of dynamic characteristics of high-speed analog-to-digital converters, containing a digital setpoint unit, a voltage converter, two comparison elements, a code processing unit, a recording unit, the output of the digital setting unit being connected to the code-voltage converter input and to the first input of the unit processing codes, the second input of which is connected to the first output of the monitored analog-to-digital converter, the first output of the code processing unit is connected to the first input One registration unit, the first inputs of the comparison elements are connected to the meld with, 10 1 WHT, in order to expand the functionality, a mode selection block, a zone setting unit and a matching element, a driver are introduced. Moreover, the output of the code-1J converter is connected to the input of the zone setting unit, the outputs of which are connected to the second inputs of the comparison elements, the outputs of which are connected to the first and second inputs of the same match, and the third outputs are connected to the second output of the controlled analog digital converter, the third output of which is connected to the third input of the element 25 matches, the fourth input of which is connected to the first inputs of the comparison elements through the mode selection block, and the output is connected to the third input of the code processing block, the second EO output of which is connected to the first input of the digital setpoint unit, the fourth input is connected to the second output of the last one and to the Start bus, while the input is controlled by analog-digital J converter is connected to the first inputs of the comparison elements and the input signal bus, and the second input of the registration unit is connected to the third output of the code processing unit.  2. The device according to claim 1, characterized in that the processing unit codes contain two shapers, three flip-flops, two counters, a code entry node, a generator, an OR element, a reversible counter, a code comparison node, two AND elements, a register, and the first input of the block is connected to the first input of the code entry node, the second input of which is connected to the output of the  OR, and the output through the reversible counter is connected to the first input of the code comparison node, the second input of which is connected to the register output, and the output to the first inputs of the first driver and the first element AND, the second input of which is connected to the generator, the third input to the first input of the second element I and the output of the first trigger, while its first output is connected to the first input of the counter, and the second output is connected to the counter input of the reversible counter, the sum of which input is connected to the forward output of the second trigger and to the output of the block, and the input of the subtraction is connected to the inverse input of the second TjHirrepa, whose single input is connected to the output of the second element I, and the zero input to the zero inputs of the first and third triggers, to the first input of the register and the output of the first imager, the second input of which connected to the fourth input of the block and to the primary 1L4 input of the second counter, the second input of which is connected to the third input of the block and to the single input of the third trigger, its output connected to the second output of the block and the second input of the first counter, first output Which is connected to the first output of the block, and the second output is connected to the second input of the second element AND and the first input of this OR, the second input of which is connected to the single input of the first trigger, the second input of the register and through the second driver to the third the register input is connected to the second block input, and the output is connected to the second input of the code comparison node. Sources of information taken into account in the examination I. USSR author's certificate No. 606204, cl. H 03 K 13/17, 19.04.74. KodUo Uo L m J Uo-uu ppusn rwj o- / 7 f4 about one ffodug YU 7 v V f HOft & g f / Jf CF  w 1 and, --t-vr-irt-