SU1723561A1 - Four-threshold extrapolating method for determining time position of video pulses and device - Google Patents

Abstract

The invention relates to measurement technology and can be used in information processing systems. The aim of the invention is to improve the accuracy of determining the temporal position of asymmetrical video pulses with nonlinear fronts and decays. The method involves forming a time scale and fixing the maximum value of the video pulse. The method is provided by linear approximation of the front by two points of intersection by the front of the first and second next thresholds, linear approximation of the decrease by two points of intersection by the decrease of the third and fourth next thresholds, extrapolations obtained directly to the intersection of the abscissa axis and selecting the video pulse as the time position The arithmetic mean of the intersection points / Description of the device implementing the method is provided in the specification. 2 s and 1 z.p. f-ly, 2 ill. ate with

Description

The invention relates to measurement technology and can be used in information processing systems.

The purpose of the invention is to improve the accuracy of determining the temporal position of asymmetrical video pulses with nonlinear fronts and decays.

The technical essence of the method lies in the fact that they form a time scale, fix the maximum value of the video pulse Am, form four following thresholds U1 Ai Am, Ua DgAt, Cs Az Am and Ud Hell Am. moreover, 0 At Dg 1 and 0 Y4 Az .1, where Ai - Az are relative measurement levels, shift the video impulse by time tc not less than the time to reach the maximum value by the video impulse,

successively compare the values of the front of the shifted video pulse with the first and second next thresholds, at the moments of coincidence form the first and second signals of coincidence, which fix the values of the times ti and t2 on the time scale, respectively, successively compare the values of the decrease of the shifted video pulse with the third and fourth next thresholds, at the moments of coincidence, the third and fourth coincidence signals are formed, which fix the time values of Tz and t4 on the time scale, respectively, and determine the temporal position in ideo pulse from addiction

Кч ti - Ai t2, / b - / U ta ° 2 (A2-Ai) + 2 (Лз-Л4).

V |

GO GO SL O

where Ai, A2, Az, Al are relative measurement levels;

ti is the time at which the front of the shifted video pulse crosses the first threshold;

t2 is the time at which the front of the shifted video pulse of the second follow threshold crosses;

m3 is the time when the decay of the shifted video impulse of the third following threshold crosses;

t / is the time of intersection by the decay of the shifted video impulse of the fourth follow threshold;

tc is the video pulse displacement time.

The method is provided by linear approximation of the front by two points of intersection by the front of the first and second next thresholds, linear approximation of the fall by two points of intersection by the fall of the third and fourth next thresholds, extrapolation obtained by direct to intersection with the abscissa axis and choosing temporary the position of the video pulse of the arithmetic average of the intersection points.

The purpose of the device for carrying out the method is to improve the accuracy of determining the temporal position of the video pulses.

A functional diagram of an apparatus for carrying out the method is shown in FIG. one; Fig. 2 is a functional block diagram of the memory block.

The device (Fig. 1) contains input 1 for supplying the detection threshold voltage, input 2 for applying the voltage of the video pulse, input start bus and input stop bus, comparator 3, differentiation element 4, delay element 5, trigger 6, generator 7 pulses, trigger 8, key 9, peak detector 10, amplitude quantizer 11 containing voltage dividers 12 and 13, consisting of series-connected resistors 12.1-12.3 and 13.1-13.3 (Rt, R2. Ra and R4, RB. Re) respectively, the values of which are related by systems of equations:

RI 1 R -,

Ri + R2 + Rs Ri + R5 + Re

Ri + R2 + R3; 2 Al Ri + S + Re -

 - 1 2 p. j p. i ri. 1 k

Ri + R2 Rs

Ri H-Rs-H- Re

where A1, A2, Azya4 are relative measurement levels, and comparators 14-17, element 18, delay elements 19, 20, elements 21-21, counter 25 pulses, block 26 pa

0

five

0 5

0

5 0 5

0

five

m ti, differentiation elements 27-30, elements NOT 31-32, delay element 33, element OR 34, elements AND 35-39, register 40, group of elements AND 41, adder 42, triggers 43-46, element 47 of delay, group elements AND 48, element OR 49, output group 50.1-50. t, where t is the number of bits of the adder 42.

The input 1 of the supply voltage of the detection threshold is connected to the first input of the comparator 3.

The input voltage supply voltage 2 is connected to the second input of comparator 3 and to the signal input of key 9. The output of comparator 3 is connected to the input of differentiation element 4 and to the control input of key 9, the output of which is connected to the signal input of peak detector 10 and to the input of element 19 delay, the output of which is connected to the second input of the amplitude quantizer 11, the output of the peak detector 10 is connected to the first input of the amplitude quantizer 11, the first output of which is connected to the input of the differentiation element 27, the second output - to the movement of the differentiation element 28, the third output is to the input of the differentiation element 29, and the fourth output is connected to the input of the differentiation element 30.

The output of the differentiation element 4 through the delay element 5 is connected to a single input of the trigger 6, the direct output of which is connected to the first inputs of the And elements 35-39.

The outputs of the differentiation elements 27 and 28 are connected to the second inputs of the And 35 and 36 elements, respectively, and the outputs of the differentiation elements 29 and 30 are connected to the second inputs of the And 37 and 38 elements, respectively, through the HE elements 31 and NO 32. The output of the HE element 32 is connected with the second input element and 39.

The outputs of the And 35-38 elements are connected to the single inputs of the flip-flops 43-46, respectively, the zero inputs of which are combined and connected to the output of the OR element 34, and the direct outputs of the flip-flops are connected to the second inputs of the And 21-24 elements, respectively, the first inputs of which are combined and connected to the output element and 18.

The output of element 39 is connected to the input of element 47 of the delay, the tap of which is connected to the zero input of trigger 6, and the output is connected to the obnu ing input of the peak detector 10 and the combined first inputs of elements of the group of elements 48.

Input bus Stop device is connected to the input of the delay element 33 and the zero input of the trigger 8, direct output

which is connected to the first input element And 18.

The output of the pulse generator 7 is connected to the second input of the TVI element, the output of which through the subcontractor delay element 20 is connected to the counting input of the pulse counter 25, the whip-up input of which is connected to the output of the delay element 33, and the information outputs are connected to the address inputs of the memory block 26 .

The outputs of the elements And 21-24. connected respectively to the second, first, third and fourth readings of the memory block 26, whose information outputs are connected to the inputs of the OR 34 element and the first group of the accumulator of the adder 42, whose information outputs are connected to the second inputs of the corresponding elements of the And 48 group of elements whose outputs are connected with the outputs 50.1-50.pl device and connected to the inputs of the element OR 49. the output of which is connected to the zeroing input of the adder 42, and with the second inputs of the group of elements And 41. The first inputs of which are connected to the corresponding stvuyu- conductive informational outputs of the register 40, and outputs connected to a second group of inputs of the adder 42.

The input bus Start device is connected to a single trigger input 8.

The amplitude quantizer 11 contains two resistive dividers 12 and 13 of voltage and four comparators 14-17. Voltage dividers consist of series-connected resistors 12.112 .3 and 13.1-13.3 (Ri, R2, R3 and Ri, Rs, Re). Resistors Рз and RS are connected to the first input of the amplitude quantizer. The common point of the resistors Ra and Ra is connected to the first input of the comparator 14, the output of which is connected to the first output of the amplitude quantizer.

The common point of the resistors Ri and R2 is connected to the first input of the comparator 15, the output of which is connected to the second output of the amplitude quantizer.

The common point of the resistors RS and Re is connected to the first input of the comparator 16f whose output is connected to the third output of the amplitude quantizer.

The common point of resistors R4 and Rs is connected to the first input of the comparator 17, the output of which is connected to the fourth output of the amplitude quantizer.

The second inputs of the comparators 14-17 are combined and connected to the second input of the amplitude quantizer.

Resistors RI and R4 are connected to the zero bus device.

The memory block 26 (FIG. 2) contains address inputs 51.1-51. K, where is the pulse counter 25 pulses, read inputs 52-55, decoder 56, the first group of 2k registers 57, the second group of 2 registers 58, the third a group of 2k registers 59 and a fourth group of 2k registers 60, the first union of 2k groups of elements AND m elements AND 61 in each group, the second union of 2k groups of elements m elements AND 62 in each group, the third union of 2k groups of elements And according to elements And 63 in each group, the fourth union of 2k groups of elements And m elements And 64 each group, a group of m OR elements 65 and the group of information outputs 66.1-66.m memory block.

The address inputs 51.1-51.k of the memory block are connected to the corresponding inputs of the decoder 56, the readings inputs 52-55 are connected to all the first inputs of the And 61-64 elements, respectively, each i-th output of the decoder 56 is connected to all the second inputs of all And 61 elements -64 1st group of elements, j-th (J ..... t), the bit output of the 1st register 57 is connected to the third input of the j-th element AND 61 of the i-th group of elements, j-th bit the output of the 1st register 58 is connected to the third input of the j-ro element AND 62 of the 1st group of elements, the j-th bit output of the i-ro register 59 is connected to the third input of the j-ro element This AND 63 of the 1st group of elements, the j-th bit output of the 1st register 6.0 is connected to the third input of the J-ro element AND 64 of the i-th group, the elements with the same name AND 61-64 of all the groups are combined with the corresponding element OR 65 of the group, the outputs of the elements of the OR 65 group serve as information outputs 66.1-66.rn of the memory block.

Inputs 52-55 are the first, second, third and fourth inputs of memory block 26,

The device works as follows.

In the initial state, the input threshold voltage is applied to the detection threshold. At the output of the comparator 3 there is a zero level, which locks the key 9. At the output of the peak detector 10 there is a zero voltage level.

Triggers 6.8 43-46 - in the zero state.

The zero voltage levels from the direct outputs of the flip-flops 43-46 are locked at the second inputs, respectively, And 21-24. Elements. . , -;

Pulse counter 25 is reset and is designed to perform the function of the address counter of memory block 26, in which: i-th

register 57 entered additional code number:

A2ATM / 2 (A2-Ai). In the 1st register 58 is an additional code number:

(-1) AiAT-i / 2 (A2-Ai). in the 1st register 59-additional code number:

(-1) А4АТ: ч / 2 (Лз- &), in the 1st register 60-additional code of the number:

Az AT 1/2 (Az-A4), where l-1 ... 2k;

k is the counter size of 25 pulses;

AT is the period of the pulse generation of the generator of 7 pulses.

An additional code of the value of the number (-1) tc is entered in register 40 and in adder 42, where tc is the delay time of delay element 19.

Chains of initial installations of elements on diagrams are not shown.

When it arrives at the input bus. The start of the triggering pulse, the trigger 8 switches to one state. A unit level from its direct output opens the element And 18 and pulses from the output of the generator 7 pulses arrive at the counting input of the counter 25 pulses.

Each value of the pulse counter 25 is monitored by forming a unit level at the corresponding output of the decoder 56 of the memory block 26.

When the voltage of the front of the video pulse input to input 2 exceeds the voltage of the detection threshold, a single level is generated at the output of comparator 3. From a single voltage drop by the differentiation element 4, a pulse / input to the input of the delay element 5 is formed.

The unit level from the output of the comparator 3 closes the switch 9, which ensures that the voltage of the video pulse arrives at the inputs of the delay element 19 and the peak detector 10.

Peak detector 10 captures the maximum value of video pulses Am and supplies it to the first input of amplitude quantizer 11. At this, the voltage of the first tracking threshold U1 At Am, which is fed to the first input of the comparator 15, is formed at the common point of resistors Ra and Ra form the voltage of the second tracking threshold Ua fa Am, which is fed to the first input of the comparator 14, at the common point of the resistors Re and Rg, the voltage of the third tracking threshold 11zAm Am. which is fed to the first input of the comparator 16, at the common point of the resistors RS and RQ, the voltage of the fourth follow gyur U4 Az Am, which is fed to the first input of the comparator 17, is formed.

In the delay element 19, the video pulse is delayed by a time tc not less than

the time to reach their maximum value, measured by the level of the detection threshold,

The delay time of the delay element 5 is shorter than the delay time of the delay element 19 at the switching time of the trigger 6. The pulse from the output of the delay element 5 switches the trigger 6 to the unit state, the unit level from which output unlocks the AND 35y39 elements.

Delayed in the delay element 19, the video pulse arrives at the second input)) of the comparators 14-17.

The device in the case when AI Aa A2

 Az, works as follows.

When the voltage of the front of the shifted video pulse coincides with the voltage of the first following threshold, a single positive voltage drop is formed at the output of the compressor 15, from which the differentiation element 28 forms a positive polarity pulse that passes through the AND 36 element and switches the trigger 44 to a single state the A single level from the direct output of the trigger 44 unlocks the element And 22. The next nearest pulse from the generator output 7 pulses passes through the elements 18 and 22 and goes through the first input to

the read input 52 of the memory block 26 reads an additional code from the N th register 57, where AND is the current value of the counter of 25 pulses, which through the AND group of elements AND 61 and elements OR 65 enters

to the inputs of the adder 42, in which the value is generated

JiAllL-t 2 (A2-Ai) tc 2 (A2-Ai) tc

with AT h ti.

The output pulse of the element 18 is delayed by the delay element 20 at the time of sampling information from the memory block 26,

after which it increases the counter value of 25 pulses per unit.

At the same time, a single level is set at the {1 + 1) -m output of the decoder 56.

The pulses from the information outputs 66.1-66.rn of the memory block 26 are combined with the OR element 34, and the generated pulse zeroes the trigger 44, the zero level from the direct output of which is blocked by the AND 22 element.

When the voltage of the front of the shifted video pulse coincides with the voltage of the fourth following threshold, a single positive voltage drop is formed at the output of the comparator 17, from which the differentiation element 30 forms a positive polarity pulse. The pulse inverted in the HE 32 element is quenched by AND 38–39 diode isolation circuits.

When the voltage of the front of the shifted video pulse coincides with the voltage of the second following threshold, a single positive voltage drop is formed at the output of the comparator 14, from which the differentiation element 27 forms a positive polarity pulse, which, passing through the AND 35 element, switches the trigger 43 to a single state the

The unit level from the direct output of the trigger 43 unlocks the element I 21.

The next closest pulse from the output of the generator 7 pulses through the elements 18 and 21 through the second input is fed to the read input 53 of the memory block 26, finds an additional code from the la register 58, where 2 is the current value of the counter 25 pulses, and gives it through the group of elements And 62 and the elements OR 65 at the inputs of the adder 42, in which the value is fixed .. ..; .

A2ti

Ai ATJ2

2 (A2-AO 2 (A2-Ai)

2 (As-Ai) tc

-tc

where 2 AT t2.

The pulses from the information outputs 66.1-66.m of memory block 26 are combined with the OR element 34, and the generated pulse zeroes the trigger 43, the zero level from the direct output of which blocks the 21 element. When the voltage of the front of the shifted video pulse coincides with the voltage A third positive threshold voltage is generated at the output of the comparator 16, from which a positive polarity pulse is formed by the differentiation element 29, which is inverted by the HE 31 element and quenched by a diode isolation circuit. element and 37.

When the voltage drop of the shifted video pulse coincides with the voltage of the third following threshold, a single negative voltage drop is formed at the output of the comparator 16,

of which by the differentiation element 29 a negative polarity pulse is formed. This pulse is inverted by the HE element 31 and, through the element 37, switches the trigger 45 to one state. The unit level from the direct output of the trigger 45 unlocks the element I 23.

The next closest pulse from the output of the generator 7 pulses through the elements 18 and 23 and through the third input enters the input 54 of the memory block 26, reads the additional code from the 3-th register 59, where 3 is the current value of the counter 25 pulses, and gives it through the 1z-th group of elements And 63 and the element OR 65 at the inputs of the adder 42, in which the value is formed

A2ti-Ait2

2 (A2-Ai) 2 (A2-A4)

A4t3

2 (Az-A4)

-tc

- tc

25 30

35

40 45 50 55 Where Is AT t3.

The pulses from the information outputs 66.1-66.rn of the memory block 26 are combined with the OR element 34, and the generated pulse zeroes the trigger 45, the zero level from the direct output of which is blocked by the AND 23 element.

When the voltage drop of the shifted video pulse coincides with the voltage of the second following threshold, a negative negative voltage drop is formed at the output of the comparator 14, from which the differentiation element 27 forms a negative polarity pulse, the further propagation of which is blocked by the I 35 element.

When the voltage decay of the shifted video pulse coincides with the voltage of the fourth following threshold, a single negative voltage drop is formed at the output of the comparator 17, from which differentiation element 30 forms a negative polarity pulse that is inverted by the HE element 32 and through the AND 39 element enters the element input 47 delay and through the element And 38 switches the Trigger 46 to one state.

A single level from the direct output of the trigger 46 unlocks the element And 24.

The next closest pulse from the output of the generator 7 pulses through the elements 18 and 24 and through the fourth input enters the input 55 of the memory block 26, reads an additional code from (4th register 60, where U is the current value of the pulse counter 25, and delivers it through the 14th group of elements AND 64 and the element OR 65 at the inputs of the adder 42, in which the value of the temporal position of the video pulse is formed

A2T.1

A4t3

+

AzDT14

(Az-AO 2 (Az-A4) 2 (Az-A4)

A2 T1 / 1 t2. AZ t4 - A4 t3 ...

- tc -

2 (A2-A |) 2 (Az-A4)

 tc

where is AT M 14.

The pulses from the information outputs 66.1-66.m of memory block 26 are combined with the OR element 34, and the generated pulse zeroes trigger 46, the zero level from the direct output of which blocks And 24.

The pulse from the retraction of the delay element 47, delayed by the response time of the trigger 46, zeroes the trigger 6.

The zero level from its direct output locks the AND 35-39 elements.

When the voltage decay of the shifted video pulse coincides with the voltage of the first following threshold, a negative negative voltage drop is generated at the output of the comparator 15, from which the differentiation element 28 forms a negative polarity pulse, the further propagation of which is blocked by the locked element I 36.

The pulse from the output of the delay element 47, which is totally delayed for the pulse pulse generator 7, plus the execution time of the addition operation in the adder 42 zeroes the peak detector 10, reads the temporal position code of the video pulse from the information outputs of the adder 42 and issues to the outputs 50.1-50, m device.

The pulses from the outputs of the group of elements AND 48 are combined by the element OR 49, and the generated pulse zeroes the adder 42, reads the additional code of the value (-1) tc from the register 40 and through the group of elements AND 41 enters it into the adder 42.

At the moment when the voltage drop of the video pulse coincides with the voltage of the detection threshold, a negative negative voltage drop is generated at the output of the comparator 3, from which the differentiation pulse 4 generates a negative polarity pulse entering the delay element 5.

The zero level at the output of the comparator 3 locks the key 9.

A negative polarity pulse from the output of the delay element 5 is quenched by diode isolation in the input circuit of trigger 6. The device is prepared to determine the time position of the next video pulse.

Upon completion of measurements, a signal is sent to the input bus Stop device, which nullifies trigger 8 and arrives at

input element 33 delay.

The zero level from the direct output of the trigger 8 locks the element I 18.

The signal from the output of the element 33 of the delay, the delay which is longer

the delay of element 20 for the duration of the transition process in the counter 25 pulses, zeroes the latter.

As a result, the device is in its original state.

The invention makes it possible to reduce the error in determining the temporal position of a video pulse.

Claims (2)

1. A four-threshold extrapolation method for determining the temporal position of video pulses, in which a time scale is formed, compare video pulse levels, create comparison signals, and record the value times on the time scale, at the same time, form the maximum value of the video pulse Am, form the first Lh At Am and the second U2 - A2 At ate the thresholds, and O. AI A2 1, where AI, A2 is the first and second relative measurement levels, shift the video pulse by a time tc not less than the time it takes the video pulse to reach its maximum value, compare the value of the front of the shifted video pulse with the first follow threshold, at the moment of level matching, form the first comparison signal, which fix the time value ti on the time scale, compare the value of the front of the shifted video pulse with the second follow threshold, at the time of comparison, form the second comparison signal, which fix the time value m. time scale, characterized in that, in order to increase accuracy 0 determining the temporal position of asymmetrical video pulses with nonlinear fronts and decays, form the third Oz Az Am and fourth 1) 4 AzAt following thresholds, with 0 A / Az 1, where Az and XA 5 are the third and fourth relative measurement levels, compare the drop value a shifted video pulse with the third following threshold, at the time of the comparison, a third comparison signal is generated, which the time value is fixed on the time scale, the value of the decay of the shifted video pulse is compared with the fourth following threshold, at the moment of comparison, the fourth comparison signal is formed, which is fixed the time value q on the time scale, and the temporal position of the video pulse is determined from - h ti -Ai t2, Dz 14 - An t3 to 2 (-Ai) + 2 (h-4) 2. A device for determining the temporal position of video pulses, comprising a comparator, three differentiation elements, five elements of support, four triggers, a key, a peak detector, a generator of pulses, an amplitude quantizer, six elements I. Two elements OR, two elements NOT, a group of elements And, a pulse counter, a memory unit, an adder, a voltage supply input for the detection threshold, a video voltage supply input, a Start bus and a Stop bus, with the detection voltage input input connected to the first compact input a, the second input of which is connected to the input voltage supply of the video pulse and to the signal input of the key, the output of which is connected to the input of the peak detector, the output of which is connected to the first input of the amplitude quantizer, the second input of which through the first delay element is connected to the output of the key, the control input of which connected to the output of the comparator and the input of the first differentiation element, the output of which through the second delay element is connected to the single input of the first trigger, the direct output of which is connected to the first inputs Dami first, second and third elements And the second input of the last of which is connected to the output of the first element is NOT, the first and second outputs of the amplitude quantizer are connected to the inputs of the second and third differentiation elements, respectively, the outputs of the first and second elements And are connected to the single inputs the second and third triggers, the zeroing inputs of which are combined and connected to the output of the first element IL1 / K and the direct outputs are connected to the second inputs of the fifth and sixth elements And, first Their inputs are combined and connected via the fifth delay element to the counter input of the counter and to the output of the fourth element I, the first input of which is connected to the forward output of the fourth trigger, the single input of which is connected to the Start bus, and the zero input is connected to the Bus Stop the device and, through the fourth delay element, to the counter zeroing input, the information outputs of which are connected to the address inputs of the memory block, the outputs of which are connected to the inputs of the first OR element and the first group of information inputs ora, the outputs of which are connected to the second inputs of the first group of elements I. The first inputs of which are combined and connected via the third delay element to the output of the third element I, and the outputs connected to the output buses of the device and through the second element OR to the zeroing input of the adder, the output of the generator is connected to the second input of the fourth element And, the outputs of the fifth and sixth elements And are connected respectively to the first and second inputs of the memory block, characterized in that, in order to improve the accuracy of determining the temporal position of vyid In addition, two differentiation elements, four AND elements, two triggers, the second group of AND elements and a register are added, the third output of the amplitude quantizer is connected to the input of the second element HE, the output of which is connected to the second input of the seventh element And, the output of which is connected to a single input of the fifth trigger, the zero input of which is connected to the output of the first OR element, and the direct output is connected to the second input of the ninth element 14, the output of which is connected The third output of the amplitude quantizer is connected to the input of the first element NOT, the output of which is connected to the second input of the eighth element And, the output of which is connected to the single input of the sixth trigger, the zero input of which is connected to the output of the first element OR, and the direct output is connected to the second input of the tenth element AND, whose output is connected to the fourth input of the memory unit, the output of the second differentiation element is connected to the second input of the second element This And, the second input of the first element And is connected to the output of the third differentiation element, the output of the third delay element is connected to the zero input of the first trigger, and the output is connected to the zeroing input of the peak detector, the first inputs of the ninth and tenth And elements are combined and connected to the fourth output element I, the first inputs of the seventh and eighth elements AND are combined and connected to the direct output of the first trigger, the information outputs of the register are connected to the first inputs of the second group of elements AND whose outputs are connected cheny to the second group of the adder inputs, and second inputs are combined and connected to the output of the second OR gate. 3, The apparatus according to claim 2, characterized in that the amplitude quantizer containing the first resistive voltage divider consists of series-connected resistors Ri, R2, RS, the values of which are connected by a system of equations; Ri / (Ri + R2 + Rs) Ai, R2 / (Rt + R2 + Ra) A2-Ai, Ra / (Ri + R2 + R3) 1-A2, and two comparators, the free terminal of the resistor Ri is connected to the common bus, the common point of resistors Ri and R2 is connected to the first input of the first comparator, the common point of resistors R2 and Pz is connected to the first input of the second the comparator, the second inputs of the comparators are combined and connected to the second input of the amplitude quantizer, the first input of which is connected to the free output of the resistor Rs, 0 five 0 the outputs of the first and second comparators are connected to the first and second outputs of the amplitude quantizer, the second resistive divider of the series-connected resistors R4, RS, Re is introduced. whose values are related by the system of equations: R4 / (R4 + Rs + Re) A / j, Rs / (R4 + RB + R6) Az-Ao, Re / (R4 + Rs + Re) 1-Az, as well as the third and fourth comparators, moreover, the free terminal of the resistor Re is connected to the first input of the amplitude quantizer, the common point of the resistors Re and RS is connected to the first input of the third comparator, the common point of the resistors RS and R4 is connected to the first input of the fourth comparator, the free output of resistor R4 is connected to the common bus, the second inputs of the third and fourth comparators are combined and connected to the second input of the amplitude quantizer, and the outputs are connected to the third and fourth outputs amplitude go quantizer. 1