SU888327A2 - Pulse-width modulator - Google Patents

Description

The invention relates to electrical engineering and can be used to modulate the control pulses of thyristor pulse-width transducers of direct current (TPPT) for electric direct current drives of electric rolling stock and electric vehicles. St. 758t63 describes a pulse-width modulator containing a master oscillator, (I-Hn + n) bit binary clock counter, t-bit decoder with two inputs, t-bit register counter, comparison node, control node and driver the duration of the enable pulses, the output of the master oscillator is connected to the clock input of a binary counter, the outputs of the m m bits of which are connected to one input of the decoder, the other input of the decoder is connected to the output of the register counter and one of the inputs of the comparison node, the second input Comparison node - with the input terminal of the device and the bit input of the register counter, the control input of which is connected to one output of the control node, the inputs of the latter are connected to the outputs of the binary counter and the output of the reference node, the other output of the control node is connected to one output terminal of the modulator and the second output terminal of the modulator is connected to the output of the decoder T via a duration driver. The disadvantage of this modulator is that the register is controlled according to the result of the comparison of the task and the state of the counter-register of the previous period. If the register-counter status in the previous period was equal to or greater than the task, and the task is increased at the beginning of the subsequent period before register-counter management, a new task will be written into the counter register, instead of increasing the register counter by one after each period, the most dramatically worsened tracking accuracy.

The aim of the invention is to improve the accuracy of tracking tasks.

The goal is achieved by introducing into the proposed pulse width modulator a t-bit register connected to the input terminal, output connected to the register counter, and the control input to the third output of the control unit.

The drawing shows a structural diagram of the modulator.

The modulator contains a master oscillator 1 (1 + m + n) -digit binary clock counter 2, a decoder with two inputs 3, t bit register in the direction of the older discharge, the comparison node 5 control unit b, the driver duration 7 pulses control unlocking TPPT, input pin 8, output pins 9 and 10, and t-bit register 11,

The output of master oscillator 1 is associated with a clock input of binary counter 2, the outputs of which m bits are associated with the bits of one input of the decoder 3. The bits of the second input of the decoder 3 are associated with the bits of the output of the register counter. The output of the register counter is also connected to one input of the comparison node 5. The other input of the comparison node 5 and the bit inputs of the register counter are connected to the bit outputs of register 11, the bit inputs of which are connected to the input terminal 8 of the device. The outputs of all bits of binary counter 2 and comparison node 5 are connected to the inputs of control node 6, one output of which is a connection; the output terminal 10 of the device, and the remaining two outputs of the control unit 5 are connected respectively to the control inputs of the register-counter 4 and the register 11. The output of the decoder 3 is connected via the output device 7 to the output terminal 9 of the device.

The device works as follows.

When the output pulses of the master oscillator 1 are applied to the clock input of the binary counter 2, the pulses appear at the bit outputs of the latter, and the pulse repetition frequency at the output of this bit is twice the frequency of the pulses at the output of the subsequent bit. The output pulses from the average m bits of the binary counter 2 are applied to the bits of one of the inputs of the decoder 3. In accordance with the state of the register-account S of the pickup, the output pulses of which are fed to the bits of the second input of the decoder 3, the output of the decoder 3 appears pulses with a frequency determined by the frequency of the highest bit

0 average m bits of the binary counter, 2, and duration t − j fT 2 P4Ti where f is the control duty cycle, T is the pulse repetition period at the output of the higher bit of the average m times 5 rows of the binary counter 2; P4 O 1J 2, ..., (2 -1) - register counter status 4.

During the time ti (Tr2. T), the comparison unit 5 performs a comparison of the states of the register-counter 5 and the register 11.

At the beginning of the subsequent period, over a period of time t T, depending on the output signal of the node of comparison 5, rewriting (recording) of the task in binary code from register 11 in the register-counter is performed, if in the previous period , ..., {2 1) - the state of the register 1 1 -, an increase in the state p of the register-counter k by one with a maximum delay if

 Rd- Pir

After the end of the control process of register-counter 4 in the same time interval r, the task in binary code is rewritten (written) from input 8 to register 11.

Low power control pulses of the control panel, control pulses of the registrar counter k (set O and write or count input) and control pulses of register 11 (set o and write) are generated from the output pulses of the binary counter 2 by the node

5 control 6 successively during time C-, and the period of the control pulses of the counting input of the register counter is formed with the period if, and the control pulses of the installation O and the record of the register counter k are formed in each period T, if p R. The control pulses of the register 11 are formed in each. home period T. Low power pulses of the control of the FETS are fed to the output terminal 10 of the device, and low power pulses of the control of unlocking the FPCs, the duration of which is formed to form The duration of 7 from the output pulses of the decoder 3, and the beginning of the pulses at the output of the shaper 7 coincide with the beginnings of the pulses at the output of the decoder 3, therefore the time delay between the beginnings of the low-power pulses of the control for unlocking and damping of the TFCs is t Г-Т.

From the foregoing, it follows that the comparison of the states of the register-counter k and the register 11 and the change of the state of the register-counter k are performed at the same state of the register 11 (since the control pulses of the register 11 by the control node 6 are generated after the generation of the control pulses) counter k, the investigator but the device is devoid of the disadvantage inherent in the prototype.

Claims (1)

1. USSR author's certificate W, cl. H 02 R 13/16, 03.02.78.