SU817976A1 - Device for control of thyristorized pulse-width converter - Google Patents

Description

(54) DEVICE FOR CONTROLLING THYRISTOR LATER-PULSE CONVERTER

The present invention relates to electrical engineering, in particular, to converter technology, and can be used to modulate the control pulses of thyristor DC-DC converters for DC electric drives.

A device for the discrete control of converters is known, comprising a master oscillator, a counter, and a decoder.

This device is intended for discrete control of single-phase or multi-phase converters 1.

The closest in technical essence to the present invention is a device that ensures the stability of a step change in the relative time delay between the control pulses of a DCFB, comprising a master oscillator, a w-bit binary clock counter, a two-input decoder, a reversible control hc-bit control counter. controls (in general, the last two nodes are a binary code transducer), and the output amplifiers of the shifted and unshifted sequence pulses. The output of the master oscillator is associated with a clock input of a binary clock counter, the bit outputs of which are associated respectively with the bits of the first input of the decoder, the bits of the second input of which are connected to the outputs of the reversible counter. The output amplifier of the non-shifting sequence is connected to one of the outputs of the binary clock counter, and the output amplifier of the shifted pulse sequence is connected with the output of the decoder 2.

The main disadvantage of this device is that the smoothness of the discrete control of the duty cycle depends on the parameters of the elements of the thyristor converter and is limited by the switching frequency of the converter. In some cases, an increase in the smoothness of regulation is achieved by reducing the switching frequency of the converter, which leads to an increase in the current ripple of the active-inductive load of the converter, thereby reducing the efficiency of the converter.

The purpose of the invention is to increase the smoothness of discrete control. The goal is achieved by the fact that the device is equipped with a gp-bit register in the direction of the higher bit, a driver for controlling the register with a meter and low-power control signals for CTPT, a driver for controlling the duration of the control for unlocking the CTPT, and a t-bit binary clock counter with 1 junior and a senior clock counter for 1 min. dami, the task converter is supplied with a low-order bit, and the t-bits of the second input of the decoder through the t-bit register-counter are associated respectively with the higher-order outputs x m bits of the task converter, the input of the latter is connected to the device input, and the outputs of all (t + 1) bits of the converter of the task and outputs of all (1 + w + 1) bits of the binary clock counter. are associated with the inputs of the pulse driver control, one output of which is connected to the control input of the register-counter, and the second output is connected to one output of the device, and the output of the two-input decoder is connected to the other output of the device through the duration generator.

The drawing shows a block diagram of the device.

The device contains a master oscillator 1, (1 + m + 1) -bit binary clock counter 2, gp-bit decoder 3 with two inputs (t + 1) -discharge converter 4 tasks in binary code, t-bit register - counter 5 in the direction of the higher bit, driver 6 for control pulses, register counter 5 and low-power pulses for control of the DCFL, driver 7 for the duration of pulses for the control of the TCFL, input terminal 8 and output pins 9 and 10.

The output of the master oscillator 1 is associated with a clock input of a binary counter 2, the outputs of the middle m bits of which are respectively associated with the m bits of one input of the decoder 3 m bits of the second input of the decoder 3 respectively are associated with m bits of the output of the counter counter 5, the bit inputs of which are respectively associated with the m most significant bits of the converter 4 tasks. The transducer input 4 of the task is connected to the input output 8 of the device, and the outputs (m + 1) of the transducer bits 4 and (1 + m4-1) the bit outputs of the clock counter 2 are connected to the inputs of the ramp 6. One output of the ramp 6 is connected with the control input of the register-counter 5, and another output of the imaging unit 6 with the output terminal 9 of the device, the output output 10 of the device through the imaging unit 7 of the duration associated with the output of the decoder 3.

The device works as follows.

. When the output pulses of the master oscillator are applied to the clock input of the binary counter 2, the pulses appear on the discharge outputs of the latter, and the pulse repetition frequency of this bit is twice as large as the frequency of the next discharge pulses. The output pulses from the average m bits of counter 2 are applied to the corresponding bits of one input of de-selector 3. In accordance with the state of register-counter 5, the output pulses of which are fed to the bits of the second input of decoder 3, the output of decoder 3 appears frequency (1 + t) -th bit of binary counter 2 and duration

Ta GT 2 Pa-T,

Y is the adjustment ratio;

where T is the pulse repetition period at the output of the (I + m) -th, bit of the binary counter 2; , 2, ...,) - register-counter state

during the period T. The end of the output pulses of the decoder 3 coincides with the end of the period T.

The shaper 7 of the duration of the output pulses of the decoder 3 generates the duration of low-power control pulses unlocking converters, the beginning of which coincides with the beginning of the pulses at the output of the decoder 3 and falls on the output terminal 10 of the device.

The task (potential, angle, etc.) acting on the input terminal 8 of the device, the transformer 4 tasks converts, c to potentials of (t + 1) -digit binary code, according to which at the beginning of the period T and during the time tg T shaper 6 from the output pulses of all (1 + m - l 1) bits of the watch counter 2 sequentially form low-power converter blanking control pulses, which are fed to the output terminal 9 of the device, and register-counter control pulses 5 Oh, write and counting by the entrance). Moreover, if the setpoint at the output of the converter 4, the binary code has an even number (i.e., the low-order input "O") of the shaper 6, the control pulses of the counting input of the counter-counter 5 are not generated, and at the beginning of each period T. ti, the task is erased and recorded in register counter 5 from the upper m bits of the converter 4 tasks, therefore, at the output of the decoder 3, pulses with a constant duration appear in accordance with the 5 state of the senior m bits of the converter 4 tasks

Claims (2)

 4-T, where Pii is the state of the most significant m bits of the converter 4 tasks in decimal code. If the job at the output of the converter 4 tasks in the binary code is an odd number and less than the maximum (i.e., the output of the lower bit "1, and the output of at least one bit from the higher gp bits" O), the control driver 6 the input of the register-counter 5 with a period of 2T (i.e. with a period of pulses at the output of the high bit of the counter 2) and for one of the 2T periods it only rewrites the task from the high-order m bits of the converter 4 tasks in the counter-register 5 , and during the second period other than restart B produced an increase in state-register 5 the counter by one, thus the output of the decoder 3 in the first period is by pulse duration ,, PP, .T. and during the second period, tsz gz + (PA + 1) T, gdeT 2 -T is a step of discrete change in the duration of the output pulses of the decoder 3. The average duty cycle is 5Gsr (Gz, 1) / 2T 2 (P 4 + 0, five). If the maximum reference (i.e., at the outputs of all bits of the converter 4, task "1"), the shaper 6 generates blanking control pulses with a period of 2T, and the control pulses of the counting input of the register-counter 5 are not formed, therefore during each period only the dubbing is performed tasks from the upper m bits of the converter 4 tasks to the register counter 5, thus at the output of the decoder 3 pulses with a duration of (2-1) T (1-2 T) appear, and since the low power control signals for damping TPPT at the output terminal 9 devices n O are with a period of 2T, then for one period of every two periods the transducer controlled by the device remains open (i.e., is not quenched), hence the average duty cycle at maximum setting is ftp.ma () 2T (, 5 ) 2 It follows from the above that the device has a discrete control smoothness that is twice as large compared to the known one (the discrete variation in the duty cycle is halved and equals Du 0.5-2 with the same switching frequency and maximum number of bits Dov decoder 3. Only at the maximum and minimum settings, the switching frequency is halved, while at the other setting values, the switching frequency remains constant and equal to the maximum possible. The average value of the duty cycle is obtained by varying the duty cycle at adjacent discrete levels with a period of 2T. By increasing the number of bits of the binary counter 2 and converter 4 by setting one more, respectively, and by a corresponding change in the driver circuit 6, the smoothness of the discrete duty cycle control can be increased fourfold. The invention is a device for controlling a thyristor pulse-width converter, which contains its master oscillator, a binary binary clock counter whose clock input is connected to the output of the master oscillator, a two-input w-bit decoder, which m bits of the first input are connected With the corresponding outputs of a binary clock counter, and a t-bit converter of a task, characterized in that, in order to increase the smoothness of the discrete control, a t-bit register counter is inserted into the counter it has a higher-order bit, a register-counter control pulse generator and a low-power thyristor converter quench control pulse, a thyristor converter unlocking pulse width generator, a t-bit binary clock counter, and a lower-order binary converter, the bits of the second input of the decoder through the register counter are connected to the outputs of the m higher bits of the task converter, the input of which is connected to the input of the device and the outputs ( t + 1). the transducer bits of the reference and the outputs (I + m + 1) of the bits of the motor clock counter are connected to the inputs of the control pulse generator, one output of which is connected to the control input of the register-counter, and one output of the device, and the other output of the device through the duration generator associated with the output of the decoder. Sources of information taken into account during the examination 1. USSR author's certificate number 242290; cl. H 02 R 13-16, 1973. 2. USSR author's certificate number 564704, cl. H 02 R 13/16, 1974.