KR100390384B1 - Pulse width modulator and arbitrary frequency generator using pulse distribution technique - Google Patents

Abstract

The present invention relates to a pulse width modulator using a pulse dispersion technique for improving the resolution and minimizing ripple of a pulse-width modulator and an arbitrary frequency generator having a minimum flow. Since the generated pulse-width resolution is limited to one cycle unit of the clock frequency, the modulation scheme as shown in FIG. 3 is used to introduce the double modulation concept to overcome this problem. It has a long cycle and a large ripple value. Accordingly, the present invention does not increase the resolution of the individual pulse-width in order to increase the resolution of the generated pulse-width despite the limitation of the clock frequency in the digital pulse-width modulation, but the average pulse-width of successive pulses. To provide a way to increase the resolution of the. It consists of one N-bit + N-bit adder 101, one N-bit latch 102, one M-bit + one-bit adder 103, and an M-bit pulse-width modulator 104 to form a pulse width. It is possible to increase the resolution of the average pulse width by regularly varying but distributing the pulses with different widths rather than concentrating them. In addition, the present invention applies the pulse dispersion technique to the power control method as it is, and also to the arbitrary frequency generator, timing generator and the like.

Description

Pulse width modulator and arbitrary frequency generator using pulse distribution technique

The present invention relates to a pulse width modulator using a pulse dispersion technique for improving resolution and minimizing ripple of a pulse-width modulator and an arbitrary frequency generator having a minimum flow.

In the electronic circuit field, pulse-width modulation is widely used for various purposes. Conventionally, analog methods have been used a lot in generation methods, but digital methods have been used in recent years.

In the pulse-width modulation, as shown in FIG. 1, a triangular wave voltage called a carrier signal (b) and a reference signal (a) necessary for determining a pulse-width are compared with each other through a comparator (1). It produces a pulse output (c) having a width.

On the other hand, in the digital method, as shown in FIG. 2, the initial value setting type down counter which sets the pulse width data as the initial value by the switching frequency a and counts down according to the clock frequency b to output the count state c. (11) and the comparator 12 which performs the pulse output d by comparing the output c of the down counter 11 with the reference level '0', which is the desired pulse repetition frequency, The switching frequency (a) is determined and a high frequency signal during the period of the switching frequency (a), that is, a clock frequency (b) is used to generate a desired pulse-width by counting the pulse-width data.

In the analog method, since the comparison of the triangular wave and the reference signal is performed continuously, there is no problem in use because the resolution of the generated pulse-width is very high.

However, in the digital method, since the pulse-width is generated by counting the clock frequency, the resolution of the generated pulse-width is limited to one cycle unit of the clock frequency.

For example, when the pulse-width modulated signal is used for D / A conversion, the resolution of the D / A value is limited due to the limitation of the resolution of the pulse-width.

If the desired switching frequency in Fig. 2 is 100KHz and the desired resolution is 1/256 of the switching frequency (corresponding to 8-bit data in binary), the required clock frequency is 100KHz × 256 = 25.6MHz. This clock frequency is not difficult to implement as a general digital IC. However, if the desired resolution is 1/65536 (16-bit data in binary), the required clock frequency is about 6500 MHz, which is not feasible as a general digital IC.

In this case, the clock frequency is used as it is 25.6MHz, but if the width of each pulse is 256 pulse periods and properly changed, a similar effect can be obtained.

If the desired resolution of the pulse-width is 1/2 ^{(M + N)} , the pulse-width data can be represented as a binary number of M + N bits. For convenience, the M-bit data is called upper data and the N-bit data is called lower data. The resolution of higher data is determined by the clock frequency. That is, the clock frequency is selected to be 2 ^M times the switching frequency. Resolution for subdata is achieved by varying the width of the various pulses at regular intervals. In other words, the pulse-width is varied with 2 ^N pulses as a cycle.

Consider the case of FIG. The values of M and N can be chosen arbitrarily, but for the sake of convenience, it is assumed here that they are all four. Suppose the desired pulse-width is for example three clocks. If you put a value of '2' in the counter, you get a pulse-width of 3 clocks (the difference between '1' is counted down to the '0' state of the down counter). If you enter a value of 3, you get a pulse-width of four clocks. If you put some number in the counter but give 16 pulses, the first one puts '3' and the remaining 15 pulses put '2' (Fig. 3 (b)). Will be 3 + 1/16 clocks. If you put '3' in the first two pulses and '2' in the rest, 3 + 2/16 clocks will be obtained (Fig. 3 (c)). If you put '3' in the first three pulses and '2' in the rest, you will get a 3 + 3/16 clock (Fig. 3 (d)). If you put '3' in the first eight pulses and '2' in the rest, you will get 3 + 8/16 clocks (Fig. 3 (e)). Thus, '3' and '2 in 16 cycles. 'Can be placed properly to obtain an average pulse-width of 1/16 between 3 and 4 clocks. That is, the average resolution can be increased by appropriately varying the pulse-width generated without increasing the clock frequency. This can be thought of as the concept of double modulation.

However, one problem in the method of FIG. 3 is that the period of variation of the pulse-width value is long. For example, if the switching frequency is 100KHz and you want to implement 16-bit resolution with a clock of 25.6MHz, the period of fluctuation of the pulse-width value is very low because 100KHz / 256 = 390Hz because the lower data is 8 bits, or 256. Becomes When the pulse is converted into a DC voltage proportional to the pulse-width for the purpose of a D / A converter or the like, a low frequency variation component, that is, a ripple component appears. In particular, the ripple value is greatest when the lower data value is in the middle (1/2).

In the present invention, in order to digitally perform pulse-width modulation in order to increase the resolution of the generated pulse-width despite the limitation of the clock frequency, the resolution of the individual pulse-width cannot be increased, but the average pulse of successive pulses. We want to provide a way to increase the resolution of the width.

1 is a conventional analog pulse-width modulator

Figure 2 is a conventional digital pulse-width modulator

Figure 3 is a method for increasing the resolution by varying the conventional pulse-width

4 is a conventional dispersion method of pulses having different pulse-widths

5 is a configuration diagram of a pulse width modulator using the method for generating distributed pulses of the present invention.

6 illustrates an example of a dispersion pulse according to FIG. 5.

7 is a case of controlling power using an AC power source as another application example of the present invention.

(a) Circuit composition

(b) conventional methods

(c) the method of the present invention

8 illustrates an arbitrary frequency generator and a timing generator as another application example of the present invention.

<Description of the symbols for the main parts of the drawings>

101, 201: N-bit + N-bit adder

102, 202: N-bit latch

103,203: M-bit + 1-bit adder

104: M bit pulse width modulator

204: frequency divider

Therefore, the present invention provides a method of minimizing the variation period and the ripple value of the pulse-width value as shown in FIG. Compared with FIG. 3, when the value of '3' is one (FIG. 4B), it is the same. However, when the value of '3' is two, as shown in (c) of FIG. 4, the pulses are not placed continuously but one is distributed every eight pulses. In the case of three, one is placed every 16/3 = 5 as shown in FIG. If eight, skip one by one as shown in (e) of FIG. This minimizes the pulse-width fluctuation period and ripple. Of course, one or fifteen is the same. At eight, however, the period of change or ripple value is significantly reduced. In the case of one or fifteen, the variation period has a small period and a small ripple value in the method of FIG.

The present invention proposes a method for obtaining a distributed pulse in real time. As shown in Fig. 5, the configuration of the present invention includes one N-bit + N-bit adder 101, one N-bit latch 102, one M-bit + one-bit adder 103 and an M-bit pulse-. Width modulator 104.

The N-bit + N-bit adder 101 uses the lower data N bits for the pulse width resolution control as the first input A and the output Q of the N-bit latch 102 as the second input B. It is configured to add two inputs (A + B), feed back to the input D of the N-bit latch 102, and output a carry signal CO when an increase occurs by the addition.

The N-bit latch 102 receives the addition output A + B of the N-bit + N-bit adder 101 to the data input D and receives the switching frequency to the clock CK by the switching frequency. And latches the add output of the adder 101 and inputs the latched output to the second input B of the adder 101.

The M-bit + 1-bit adder 103 has a higher output M bit for pulse width resolution control as a first input A, and a carry output CO of the N-bit + N-bit adder 101 as a second input. The input B is configured to output a sum A + B obtained by adding two inputs.

The M-bit pulse width modulator 104 receives the output (A + B) of the M-bit + 1-bit adder 103 to the data input (D) to stabilize based on the clock frequency to form a pulse width signal of M bits Configured to pulse output.

Detailed operation principle is as follows.

N-bit + N-bit adder 101 adds two inputs A and B, and the added value A + B is fed back to N-bit latch 102 to switch back to the latch output by the switching frequency N-bit + N-bit adder ( Since it is input to the second input B of 101, the adder 101 adds the lower data for each pulse, and the carry signal CO is generated when the added value exceeds the N-bit value.

Here, for convenience, the case of N = 4 bits will be described. For example, if the lower data is '1', as shown in (b) of FIG. 6, 1 is added to every pulse, so that the pulse-width is '1' only when the rounding occurs once after 15 pulses and the rounding occurs. It will go out with a large value. If the lower data is '2', as shown in (c) of FIG. 6, two pulses are added to each pulse, causing a rounding to occur every eight pulses. If it is '3', rounding occurs every 5 pulses as shown in (d) of FIG. 6. If it is '8', as shown in (e) of FIG. 6, the floating occurs once every two pulses. If '15', as shown in (f) of FIG. 6, the rounding will continue to occur once every 16 pulses. In this way, the desired dispersed pulse can be obtained. The same is true for M = N = 8 bits and in any case.

Therefore, the same distributed pulse as described with reference to FIG. 4 can be obtained, and the same dispersion effect can be obtained by using the adder 101 and the latch 102 without using a ROM. The present invention for generating such distributed pulses can be usefully applied to a D / A converter.

Another application area is as follows.

7 illustrates a case where power is controlled using an AC power source. Fig. 7A is a simple configuration circuit diagram. It is to control the power supplied to incandescent lamp or heater by turning on / off the load every one cycle of AC power. ZERO CROSSING control method has the advantage of generating less noise than phase control method. The control cycle can usually be 256 cycles, but for the sake of simplicity, this description will be given as 16 cycles. Fig. 7 (b) shows a conventional method in which ON pulses are crowded between ON pulses and OFF sections are crowded between OFF sections. Therefore, long control cycles can cause flickering and large power fluctuations. Fig. 7 (c) shows that the ON pulse is properly distributed as the method of the present invention. This method minimizes flickering and minimizes power fluctuations.

Another application is an arbitrary frequency generator or a timing generator. As shown in FIG. 8, if a major clock frequency is counted and a random frequency lower than that is generated, only a frequency divided by an integer value is generally generated. However, by applying the principles of the present invention, not only integers but also arbitrary frequencies divided by values below the decimal point can be produced. 8 shows one divider 204 for dividing a clock frequency into an arbitrary value, one N-bit + N-bit adder 201, one N-bit latch 202, and one M-bit + 1. It consists of a bit adder 203.

When dividing the input clock frequency f1 into the desired division ratio, the data after the decimal point (N bit data) of the divided data is input to the first input A, added with the second input B, and rounded up (A + B). An N bit + N bit adder 201 that outputs a carry signal CO when generated; The addition output A + B of the N-bit + N-bit adder 201 is input to the data input D and the random frequency f2 output is input as a clock signal CK to latch the N-bit + N input. An N bit latch 202 for outputting to the second input B of the bit adder 201; When the input clock frequency f1 is divided by the desired division ratio, the integer portion (M bit data) of the divided data is used as the first input A, and the carry signal CO of the N bit + N bit adder 201 is supplied. An M-bit + 1-bit adder 203 which is inputted as the second input B and outputs a value A + B obtained by adding two inputs; The frequency divider 204 is configured to divide the input clock frequency f1 based on the output of the M-bit + 1-bit adder 203 and output a desired frequency f2.

In the case of dividing the clock frequency f1 in this manner, an integer value of the divided data is added in a dispersed state by applying a dispersion pulse to the decimal point value of the divided data. Then, the generation frequency is a value obtained by dividing the clock frequency by an integer multiple. Whenever a rounding occurs due to data below the decimal point, the integer value is increased by '1' so that the desired frequency is accurately obtained. Of course, values below the decimal point work, so that the period of the generated frequency fluctuates slightly every moment (this is called jittering). However, the average value of the generated frequencies is exactly obtained. For example, if the clock frequency is 10MHz, one period is 100ns. In order to obtain any frequency, the divided data is determined. The divided data will be represented by the integer part and the decimal part. With the data of the integer part, the period of the generation frequency can be made in units of 100ns. In order to obtain a more accurate frequency, data below the decimal point should be reflected. If this part is selected as 8 bits, the period of the generated frequency can theoretically be exactly 100ns / 256.

As described in detail above, the present invention improves the average pulse-width resolution of consecutive pulses in order to increase the resolution of the generated pulse-width in spite of the limitation of the clock frequency in digitally performing pulse-width modulation. By providing a method that can improve the resolution of the pulse width without increasing the clock frequency.

In addition, by applying the technique of the present invention to the power control circuit can minimize the flicker and the power fluctuations can be minimized.

In addition, by applying the technique of the present invention to the arbitrary frequency generator, there is an effect that can generate any very precise frequency in terms of average frequency. In other words, it is possible to generate a desired frequency, but to generate a frequency sampled (quantized) with a clock frequency, which frequency can also be used as an arbitrary timing generator.

Claims (3)

The lower data N bit, which is the fractional part of the pulse width control data for the pulse width resolution control, is input to the first input A, and the second input B is added to output the sum value A + B. An N-bit + N-bit adder 101 for outputting a carry signal CO when a rounding number is generated by addition; The add output A + B of the N-bit + N-bit adder 101 is input to the data input D, the switching frequency is input to the clock CK, and the add output of the adder 101 is switched by the switching frequency. The N-bit latch 102 for latching and inputting the latched output to the second input B of the adder 101; The upper data M bit, which is an integer part of the pulse width control data for the pulse width resolution control, is used as the first input A, and the carry output CO of the N bit + N bit adder 101 is used as the second input B. M-bit + 1-bit adder (103) for receiving the input and outputting the sum (A + B) of the two inputs; M-bit pulse width modulator that receives the output (A + B) of the M-bit + 1-bit adder 103 to the data input (D) and stabilizes based on the clock frequency to output the pulse with the desired pulse width signal of M bits Pulse width modulator using a pulse dispersion technique, characterized in that consisting of (104). In the frequency generator that divides the clock frequency to generate an arbitrary frequency, When dividing the input clock frequency f1 into the desired division ratio, the data after the decimal point (N bit data) of the divided data is input to the first input A, added with the second input B, and rounded up (A + B). An N bit + N bit adder 201 that outputs a carry signal CO when generated; The addition output A + B of the N-bit + N-bit adder 201 is input to the data input D and the random frequency f2 output is input as a clock signal CK to latch the N-bit + N input. An N bit latch 202 for outputting to the second input B of the bit adder 201; When the input clock frequency f1 is divided by the desired division ratio, the integer portion (M bit data) of the divided data is used as the first input A, and the carry signal CO of the N bit + N bit adder 201 is supplied. An M-bit + 1-bit adder 203 which is inputted as the second input B and outputs a value A + B obtained by adding two inputs; A pulse dispersion technique comprising a divider 204 for dividing the input clock frequency f 1 based on the output of the M-bit + 1-bit adder 203 and outputting a desired frequency f 2. Arbitrary frequency generator. delete