JPH0263221A - Digital/analog converter - Google Patents

Abstract

PURPOSE:To improve response speed by using L pieces of pulses whose period is MT in place of a pulse with a period of NT (T is a clock period) in order to obtain a resolution N (N=ML). CONSTITUTION:L-cycle (N=ML) of pulse width modulation waves with a resolution of M are used and a digital input value (k) to a counter 6 is selected to be k=LXa+b (0<=a<M, 0<=b<L), then a pulse width modulation signal outputted from a 1st pulse width modulator 11 is a pulse whose duty is a/M in the L cycles and a pulse whose duty is (a+1)/M in the remaining b-cycle in the L cycles to be generated and the processing above is repeated. Then the pulse width modulation signal is smoothed by a low pass filter 4 to obtain an analog signal corresponding to a digital input signal. Thus, the conversion speed is quickened.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to improving the conversion speed of a digital-to-analog converter (hereinafter referred to as a DA converter) using a pulse width modulation method.

<Prior Art> Conventionally, a pulse width modulation type DA converter is well known in that it is a simple circuit, monotonous, and can realize a high-resolution A converter. FIG. 3 is a block diagram showing an example of a conventional pulse width modulation type DA converter. 10 is a pulse width modulator, and a counter 11 counts a reference operating clock given from the outside. The counter supplies a count value to a comparator 12, and when the count value is 0, it supplies a signal ZERO to a flip-flop yp13.

The comparator 12 compares a set value (digital input signal) k given from the outside with the count value of the counter 11, and outputs a match signal when they match.

The flip-flop 13 is reset by this coincidence signal,
It is set by the ZERO signal.

FIG. 4 is a diagram showing a time chart of operations in such a configuration. The counter 11 counts the reference operation clock with a period N, and when the value does not become O, the signal ZERO is output.
Take out and set flip frog 13. and,
When the count value of the counter 11 becomes equal to the set value,
The flip-flop 13 is reset by the match signal output from the comparator 12.

As described above, a duty pulse of /H is generated. This pulse width modulation output is averaged by a low-pass filter 20 to obtain an output voltage (digital-to-analog conversion value) of kE/N (where E is the peak value of the pulse).

<Problems to be Solved by the Invention> In such a pulse width modulation type DA converter, the output is determined as the average value of pulses with a period of NT, where T is the tarok period. In order to sufficiently attenuate the output ripple, it is necessary to make the cutoff frequency of the low-pass filter 14 in the output section sufficiently lower than the frequency (1/NT) of the pulse width modulated wave, and the response speed of the DA converter The problem is that it limits the

Furthermore, when attempting to increase the resolution N, the period NT of the pulse width modulated wave also increases proportionally, resulting in a problem that the conversion speed decreases.

In short, in the conventional pulse width modulation type DA converter,
It had the drawbacks of low conversion speed and poor responsiveness.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pulse width modulation type DA converter with good responsiveness and high conversion speed, in order to eliminate such drawbacks.

Means for Solving the Problems> In order to achieve such objects, the present invention counts a reference operation clock given from the outside and outputs a pulse width modulation signal corresponding to a digital value given from the outside. a first pulse width modulator; a low-pass filter for smoothing the output of the pulse width modulator; a counter to which a digital input signal is preset and which counts up a given reference operating clock; when a load signal is given; a register that stores the output value of the counter and supplies its upper bit to the first pulse width modulator; and a register that counts an externally supplied reference operating clock and generates a pulse width modulation signal corresponding to the lower bit of the register. a second pulse width modulator for output; means for controlling a reference operating clock input to gate the pulse width modulated signal output from the second pulse width modulator to provide to the counter; and the reference operating clock and load. The present invention is characterized in that it includes a control circuit configured to generate a signal and generate a load signal every 1-th reference operation clock.

In the present invention, a pulse width modulated wave with resolution M is used for one cycle (N=ML), and the digital input value k to the counter is expressed as follows: k=L×a×, where 0≦a<M, O When ≦b < L, the pulse width modulation signal output from the first pulse width modulator is a pulse of duty a/M in the (L-b) cycle of the L cycle, and a pulse of duty a/M in the b cycle of the remaining L cycles. Now, a pulse of duty (a+1)/M is generated, and this is repeated.

This pulse width modulation signal is smoothed with a low pass filter,
Obtain an analog signal corresponding to a digital input signal.

<Example> Embodiments of the present invention will be described in detail below with reference to the drawings.

In the present invention, in general, in order to obtain the resolution N, the resolution M
Using a pulse width modulated wave with L cycles (N = ML), the set value (digital input value) k to the counter is k = L x a + b However, when 0≦a<M, O≦b<L, The (L-b) cycle in the L cycle is controlled to generate a pulse of duty a/M, and the b cycle of the other cycles is controlled to generate a pulse of duty (a+1)/M. As a result, the same resolution can be obtained with a period of a pulse width modulated wave that is twice as long as that of a conventional pulse width modulator.

FIG. 1 is a diagram showing the main part of an embodiment of a pulse width modulation type DA converter according to the present invention. Here, the digital input signal is 6-bit data (k), and the resolution is 8 bits.
(3 bits), that is, N=8. The case where L=8 will be explained as an example. In the figure, 1 and 2 are equivalent to the conventional pulse width modulator shown in FIG. The first pulse width converter 1 receives the upper three bits (a) of the register 3 as input and generates a pulse of duty a/8.

This output is averaged by a low-pass filter 4 and output.

The second pulse width modulator 2 receives the lower three bits (b) of the register 3 as input and generates a pulse with a duty of b/8.

5 is a gate which is an AN between the output of the second pulse width modulator 2 and the reference operating clock CLK given from the control circuit 7.
This is an AND gate that takes D.

A counter 6 has a digital input signal k set as an initial value by the rise of a load signal LOAD outputted from the control circuit 7, and counts the reference operation clock inputted through the gate 5. Register 3 stores the value of counter 6 at the rising edge of load signal LOAD.

The control circuit 7 generates the reference operating clock CLK and the load signal LOAD, and the LONID signal is generated every eight clocks of the reference operating clock.

The operation in such a configuration will be explained next with reference to the time chart of FIG. 2.

Now, digital human power k is 20 (24 oct in octal)
), so initially a=2°b=4.

When the control circuit 7 issues a load signal LOAD, the counter 6 is set to an initial value of 24 oct, and at the same time, the register 3 is also loaded with 24 oct (010100 in binary). As a result, the first pulse width modulator 1 is given the upper three bits of 24 oct, ie, 010. As a result, the output PWM1 of the pulse width modulator 1 becomes a pulse with a duty of 2/8.

On the other hand, the second pulse width modulator 2 is given the lower three bits of 24 oct, that is, 100. In this state,
When four reference operating clocks are input to the second pulse width modulator 2, a match signal is output from the comparator inside the pulse width modulator 2, and as a result, as shown in (7) in FIG. 8 pulses are output. The output PWM2 of the pulse width modulator 2 controls the reference operating clock CLK at the gate 5, and provides four taroks to the counter 6 as shown in (8) in FIG. This results in
The counter 6 counts up 8 clocks from the initial value of 24 oct to reach 300C1.

When the next load signal LOAD is issued, the register 3 is loaded with the count value 30 oct (011000) of the counter 6, and the counter 6 is again loaded with 24 act.

This time, the upper 3 bits of 011 are sent to the first pulse width modulator 1.
is given to the pulse width modulator 2, and the lower 3 bits of 00
0 is given. Because of this, the output of the pulse width modulator 1 becomes a pulse with a duty of 3/8. On the other hand, the output of the second pulse width modulator 2 becomes O, so the value of the counter 6 remains unchanged at 240Ct.

When the next load signal LOAD comes in eight clocks after the second load signal is generated, the same state as the beginning occurs.

The above operation is repeated, and the first pulse width modulator 1 alternately outputs duty 2/8 pulses and duty 2/8 pulses.

Therefore, when the output PWMI of the pulse width modulator 1 is averaged by the low-pass filter 4, 1/2 (2/8+
3/8) E=20E/64 output is obtained. That is, an analog output corresponding to the digital input value 20 is obtained.

If the digital input value is another value, analog conversion is performed in the same manner as above.

In the embodiment, the first pulse width modulator is the same as the conventional pulse width modulator, but by using this as the pulse width modulator part of the present invention, the pulse width modulation period can be further shortened. , it can also be made faster.

<Effects of the Invention> As explained in detail above, the present invention has the following effects.

In order to obtain a resolution N, five pulses (N
=ML), the cutoff frequency of the low-pass filter in the output section can be increased, and the response speed of the DA converter can be improved.

[Brief explanation of the drawing]

Fig. 1 is a main part configuration diagram showing an embodiment of a pulse width variation type DA converter according to the present invention, Fig. 2 is a time chart for explaining the operation, and Fig. 3 is a conventional pulse width modulation method. FIG. 4 is a time chart for explaining the operation of the DA converter of FIG. 3. DESCRIPTION OF SYMBOLS 11... First pulse width modulator, 2... Second pulse width modulator, 3... Register, 4... Low pass filter, 5... Gate, 6... Counter, 7 ...Control circuit.

Claims (1)

[Claims] A first pulse width modulator that counts an externally applied reference operating clock and outputs a pulse width modulation signal corresponding to an externally applied digital value; a low-pass filter for smoothing; a counter to which a digital input signal is preset and up-counts a given reference operating clock; and a counter that stores the output value of the counter when a load signal is given, and stores its upper bits as the first clock. a register to be applied to the pulse width modulator; a second pulse width modulator that counts a reference operating clock applied from the outside and outputs a pulse width modulation signal corresponding to the lower bits of the register; means for controlling a reference operating clock input to the counter by gating a pulse width modulated signal output from a modulator; A control circuit configured to generate a pulse width modulated wave with a resolution of M is used for L cycles (N=ML), and the digital input value k to the counter is expressed as follows: k=L×a+b, where 0≦a <M, 0≦b<L, the output of the first pulse width modulator is a pulse with a duty of a/M in the (L-b) cycle of the L cycle, and a pulse with a duty of a/M in the b cycle of the remaining L cycles. A digital-to-analog converter characterized in that a pulse of (a+1)/M is generated.