JP2004208037A - Spread spectrum clock generating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a spread spectrum clock generating circuit where a spectrum can sufficiently be spread with a simple constitution. <P>SOLUTION: A spread spectrum clock generating circuit is provided with a frequency phase comparator 12 detecting a phase difference between a reference clock CLK and a generation clock CK, a charge pump 13 generating a charge/discharge signal in accordance with the detected phase difference, a loop filter 14 generating a difference signal corresponding to the charge/discharge signal, a spread spectrum modulation circuit 19 modulating the difference signal and generating a spread spectrum modulation signal and a clock generator 20 generating the clock CK of a frequency corresponding to a spread spectrum signal. The spread spectrum modulation circuit 19 generates the spread spectrum modulation signal whose amplitude changes to a plurality of different amplitudes. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a spread spectrum clock generation circuit that generates a clock signal whose period fluctuates by a small amount in order to reduce electromagnetic wave radiation.
[0002]
[Prior art]
2. Description of the Related Art In recent years, as semiconductor devices have become faster and more highly integrated, electromagnetic wave radiation from the devices has become a problem. As the operating frequency increases, the wavelength of the signal becomes shorter, and the wiring length inside the connection circuit or the substrate becomes almost the same as the wavelength of the high-frequency signal. Radiation increases rapidly. Electromagnetic radiation of an electronic device using a semiconductor element that operates with a high-speed clock causes adverse effects such as a malfunction due to mutual interference between electronic devices and interference with a communication device.
[0003]
In order to solve such problems, in electronic equipment where electromagnetic radiation is a problem at present, measures such as reducing the electromagnetic radiation by improving the circuit layout etc. and reducing the leakage of electromagnetic waves to the surroundings by shielding the electromagnetic waves, etc. Has been done. However, there is a problem that it is difficult to sufficiently perform shielding for reducing electromagnetic wave radiation since portable devices and the like are required to be reduced in size and weight.
[0004]
Therefore, it has been practiced to spread the clock by slightly changing the operation clock of the semiconductor device to reduce electromagnetic wave radiation, and a spread spectrum clock generation (SSCG) circuit for generating such a clock has been developed. Proposed. (JP-A-2000-101424, etc.)
FIG. 1 is a diagram illustrating a configuration example of a conventional SSCG circuit. This example is a circuit that generates a clock CK having a frequency M / N times that of a reference clock CLK using a PLL (Phase Locked Loop) circuit. This circuit includes a 1 / N divider 11, a frequency phase comparator 12, a charge pump (CP) 13, a loop filter 14, a voltage controlled oscillator (VCO) 17, a 1 / M divider 18, a modulator 15, a voltage It comprises an adder circuit 16. The frequency phase comparator 12 detects the phase difference between the 1 / N frequency-divided CLK and the 1 / M frequency-divided CK, and outputs a signal for controlling the CP 13 according to the phase difference.
The CP 13 outputs a signal for charging and discharging the loop filter 14 according to the phase difference, and a difference voltage corresponding to the phase difference is generated at one end of the loop filter 14. In a conventional clock generation circuit that does not perform spread spectrum, this difference voltage is applied to the VCO 17, and a clock having a constant cycle is generated accordingly. However, in the SSCG circuit, the modulator 15 outputs a spectrum modulation signal that fluctuates at a predetermined cycle with a small amplitude as shown in FIG. 2, and the voltage addition circuit 16 adds the spectrum modulation signal to the difference voltage to add the VCO 17 Is applied. As a result, the cycle of the generated clock CK fluctuates in a predetermined cycle around a cycle M / N times the cycle of the reference clock CLK. The rate of change of the period and the cycle of the change are determined by the spectrum modulation signal generated by the modulator. Note that the response time of the PLL circuit is set sufficiently longer than the cycle of the spectrum modulation signal.
[0005]
Generally, a triangular wave as shown in FIG. 2 is used as the spectrum modulation signal. However, when a triangular wave is used, peaks are generated at both ends of the spectrum width generated by diffusion, so that there is a problem that electromagnetic wave radiation in this portion increases.
[0006]
Therefore, JP-A-7-235862 and JP-A-9-98152 disclose using a waveform as shown in FIG. 3 as a spectrum modulation signal. As a result, the above-mentioned peak is reduced, and electromagnetic wave radiation is reduced.
[0007]
Japanese Patent Application Laid-Open No. 8-292820 discloses a configuration in which the period of a spectrum modulation signal is randomly changed. Electromagnetic radiation is reduced by randomly changing the period.
[0008]
[Patent Document 1]
JP-A-2000-101424 (whole)
[Patent Document 2]
JP-A-7-235862 (FIG. 3)
[Patent Document 3]
JP-A-9-98152 (FIG. 3)
[Patent Document 4]
JP-A-8-292820 (whole)
[0009]
[Problems to be solved by the invention]
However, it is not easy to generate a waveform as shown in FIG. 3, and there is a problem that a circuit for generating such a waveform is large in scale and high in cost.
[0010]
Also, if the cycle of the spectrum modulation signal is changed at random, the cycle of the generated clock may change greatly in a short time. This is not preferable in terms of the operation of the SSCG circuit. In addition, when the generated clock is used in a logic circuit or the like, there is no problem in operation if the rate of change with respect to time is small even if the range of change is large. .
[0011]
SUMMARY OF THE INVENTION It is an object of the present invention to realize a spread spectrum clock generation circuit that can further reduce electromagnetic wave radiation with a simple configuration.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, a spread spectrum clock generation circuit according to the present invention is characterized in that a spread spectrum modulation circuit modulates a difference signal to generate a spread spectrum modulation signal whose amplitude changes to a plurality of different amplitudes. . It is desirable that the cycle of the spread spectrum modulation signal changes sequentially in each cycle.
[0013]
FIG. 4 is a diagram showing the principle configuration of the spread spectrum clock generation circuit according to the present invention. As shown in FIG. 4, the spread spectrum clock generation circuit of the present invention generates a charge / discharge signal in accordance with a frequency / phase comparator 12 for detecting a phase difference between a reference clock CLK and a generated clock CK, and a detected phase difference. A charge pump 13, a loop filter 14 for generating a difference signal, a spread spectrum modulation circuit 19 for modulating the difference signal to generate a spread spectrum modulation signal, and a clock for generating a generation clock having a frequency corresponding to the spread spectrum modulation signal In the spread spectrum clock generation circuit including the generator 20, the spread spectrum modulation circuit 19 generates a spread spectrum modulation signal whose amplitude changes to a plurality of different amplitudes.
[0014]
FIG. 5 is a diagram illustrating the principle of the present invention. In the conventional SSCG circuit, a spread spectrum modulation signal of a triangular wave that changes at a constant period as shown in FIG. 2 is added to the difference signal. Therefore, as shown in FIGS. 5B and 5C, the spectrum component has a problem that both sides of the spectrum are higher than the central portion, and that the electromagnetic wave radiation in this portion does not decrease. On the other hand, in the present invention, as shown in FIG. 5A, the amplitude of the spread spectrum modulation signal is changed. The spectrum component in this case is as shown in FIG. 5D in which the spectrum in the case of small amplitude in FIG. 5B and the spectrum in the case of large amplitude in FIG. 5C are combined. Part of both ends becomes lower.
[0015]
As described above, according to the present invention, the amplitude of the spread spectrum modulation signal changes in a plurality of different periods, so that both ends of the spectrum can be made lower than in the case where the amplitude is constant, and electromagnetic wave radiation can be further reduced. Can be reduced. Further, it is desirable that the amplitude of the spread spectrum modulated signal changes every period so as not to cause a sudden change between adjacent periods. For example, as shown in FIG. 5A, when the spread spectrum modulation signal changes to a positive or negative level around the zero level, the amplitude is changed when the signal is at the zero level. If the minimum level is constant, the amplitude is changed at the minimum level. Thus, the level of the spread spectrum modulated signal does not change abruptly on the way, and the cycle-to-cycle jitter, which is the difference between the periods of adjacent clock pulses, is small. Therefore, even when the generated clock is used for a logic circuit or the like, there is no problem in circuit operation.
[0016]
FIG. 5A shows a combination of two types of amplitudes, a large amplitude and a small amplitude, but it is also possible to combine three or more types of amplitudes.
[0017]
Further, the cycle of the spread spectrum modulation signal may be sequentially changed to a plurality of different cycles in accordance with the amplitude.
[0018]
A voltage controlled oscillator (VCO) can be used as the clock generator. When a VCO is used as a clock generator, a spread spectrum modulation signal generated by a spread spectrum modulation circuit is added to a differential voltage generated at one end of a loop filter to obtain a spread spectrum modulation signal. Apply.
[0019]
When a VCO is used as a clock generator, the spread spectrum modulation circuit can be realized by an analog circuit or a digital circuit. When the spread spectrum modulation circuit is implemented by an analog circuit, for example, an analog modulator generates a spread spectrum analog voltage signal that changes to a plurality of different amplitudes, and a voltage addition circuit adds the spread spectrum analog voltage signal to the difference signal. I do. The analog modulator is realized by including a capacitor, a constant current source that switches between a state in which the capacitor is charged with a constant current and a state in which the capacitor discharges a constant current, and a switching control circuit that changes a switching cycle of the constant current source. it can.
[0020]
When the spread spectrum modulation circuit is implemented by a digital circuit, the digital control circuit continuously changes between a maximum value and a minimum value, and at least one of the maximum value and the minimum value becomes a plurality of different values for each cycle. A digital control circuit that generates an output code that changes in order, a voltage digital-to-analog conversion circuit that generates a spread spectrum voltage signal according to the output code, and a voltage addition circuit that adds the spread spectrum voltage signal to the difference signal. realizable.
[0021]
The present applicant discloses in Japanese Patent Application No. 2002-266631 that a voltage-current conversion circuit converts a differential voltage into a differential current signal without using a VCO, and a current variable circuit performs spread-spectrum modulation on the differential current signal to obtain a current oscillator. A configuration for applying a spread spectrum modulation signal to (ICO) is disclosed, and the present invention is also applicable to this.
[0022]
When the present invention is applied to the configuration disclosed in Japanese Patent Application No. 2002-266631, a voltage / current conversion circuit for converting a difference voltage into a difference current signal is further provided, and an ICO is used as a clock generator. A spread spectrum modulation circuit, a digital control circuit that continuously changes between a maximum value and a minimum value, and generates an output code in which at least one of the maximum value and the minimum value sequentially changes to a plurality of different values in each cycle, A current variable circuit that is provided between the voltage-current conversion circuit and the current-controlled oscillator and that generates a spread-spectrum current modulation signal by modulating the difference current signal according to an output code.
[0023]
The current variable circuit is realized by including a digital-to-analog conversion current circuit that converts an output code into a spread spectrum current signal of an analog signal and adds it to a difference current signal. It is desirable that the current variable circuit further includes a low-pass filter that removes a high-frequency component.
[0024]
The spread spectrum modulation circuit includes a digital control circuit that generates a spectrum modulation code whose value sequentially changes in a predetermined cycle and a level change code that sequentially changes to a plurality of different values in a predetermined cycle, and a voltage-current conversion circuit. And a current control oscillator, a first current variable circuit that modulates a current signal having a predetermined ratio of the difference current signal according to a spectrum modulation code, and amplifies an output of the first current variable circuit according to a level change code. It can also be realized by providing a second current variable circuit, and adding the output of the second current variable circuit to the difference current signal. Also, with this configuration, it is possible to change the level first, in which case the first current variable circuit amplifies the current signal of a predetermined ratio of the difference current signal according to the level change code, and Modulates the output of the first current variable circuit according to the spectrum modulation code.
[0025]
The digital control circuit includes a plurality of frequency dividers having different division ratios for dividing the clock, a switching controller for sequentially selecting outputs of the plurality of frequency dividers, and an up / down counter for counting the selected divided clock. This is realized by providing a counter that counts the frequency-divided clock and switches between the up operation and the down operation of the up / down counter at every predetermined count.
[0026]
Further, the digital control circuit can be realized by a computer system under program control.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 6 is a diagram showing a configuration of a spread spectrum clock generation (SSCG) circuit according to the first embodiment of the present invention. As shown in the figure, a circuit for generating a clock CK of M / N times the reference clock CLK using a PLL circuit in the same manner as the circuit shown in FIG. 1, and the amplitude of the spread spectrum modulation signal generated by the modulator 22 However, it differs from the conventional example in that it changes sequentially.
[0028]
As shown in FIG. 6, in the SSCG circuit of the first embodiment, the control circuit 21 generates an output code as shown in FIG. In the first cycle, the output code increases in value from the intermediate value to the first maximum value, then decreases to the first minimum value, and increases again. Then, when the intermediate value is reached, the next second period is entered. The value increases from the intermediate value to the second maximum value, then decreases to the second minimum value, and increases again. Then, when the intermediate value is reached, the first cycle is started again and the same operation is repeated thereafter. In this example, the first and second periods also differ in the length of one period.
[0029]
The modulator 22 is a voltage analog-to-digital converter (VDAC), and converts an output code into an analog voltage signal. As a result, a spread spectrum modulated analog voltage signal whose amplitude and period change for each period is obtained. If the voltage signal does not change smoothly due to the voltage change width corresponding to the minimum bit of the output code, smoothing is performed using a low-pass filter. The voltage adding circuit 16 adds a spread spectrum modulated analog voltage signal to a difference voltage generated at one end of the loop filter 14. Thus, the voltage applied to the VCO 17 changes with a small amplitude, and the amplitude and the cycle change every cycle. Therefore, the frequency (period) of the clock CK generated by the VCO 17 changes continuously within a small range within each period, and the maximum and minimum values of the frequency within the period change every period. Furthermore, the period itself will also change.
[0030]
The control circuit 21 can be realized by a computer system controlled by a program such as a microcomputer or a DSP. In this case, the output code can be changed according to external control.
[0031]
The control circuit 21 can be realized by a digital logic circuit or the like. FIG. 8 is a diagram showing the configuration and operation of the control circuit 21 implemented by a digital logic circuit.
As shown in FIG. 8A, the control circuit 21 includes an up / down counter 23 for counting clocks and a switching counter 24 for controlling the up / down counter 23. The up / down counter 23 outputs the count value in an n-bit binary code. As shown in FIG. 8B, the switching counter 24 counts the clock, and switches the up-counting operation and the down-counting operation of the up / down counter 23 when the count value reaches a predetermined value. Switching is performed in the order of 14, 13, and 12, and thereafter, this operation is repeated. As a result, an output code that changes as shown in FIG. 7 is obtained as a control output. It is desirable that the minimum value output as the control output is zero, but the count value is not particularly limited and may be any value. For example, a first cycle in which the minimum value is 0 and the maximum value is 15 and a second cycle in which the minimum value is 1 and the maximum value is 14 may be alternately repeated. For example, any value may be used as long as the first cycle in which the minimum value is 5 and the maximum value is 30 and the second cycle in which the minimum value is 7 and the maximum value is 28 are alternately repeated. However, if the minimum value is not zero, an offset component unrelated to PLL control and spread spectrum is added to the voltage signal applied to the VCO, which is not desirable from the viewpoint of control.
[0032]
Further, the voltage level output from the modulator 22 in accordance with the code is set in accordance with the variation rate of the spread spectrum modulation with respect to the difference voltage generated at one end of the loop filter 14.
[0033]
FIG. 9 is a diagram showing the configuration of the SSCG circuit according to the second embodiment of the present invention. In the first embodiment, the spread spectrum modulated analog voltage signal is generated by digital processing. In the second embodiment, the spread spectrum modulated analog voltage signal is generated by analog processing.
[0034]
FIG. 10A is a diagram showing a circuit configuration of the switch switching control circuit 31 and the analog circuit modulator 32 of FIG. 9, and FIG. 10B is a diagram showing an operation of the analog modulator. As shown in FIG. 10A, in this circuit, a capacitance element having a capacitance value C1 is provided, and one end of the capacitance element is connected to the ground. The portion indicated by reference numeral 33 is a current source circuit for supplying (charging) or flowing out (discharging) a current equal to the current I flowing from the constant current circuit to or from the capacitor by the current mirror circuit. Control switches between charging and discharging. When the current source circuit is charged, the capacitor is charged with the current I, and the voltage at the terminal of the capacitor (analog modulator output voltage) increases. Next, when the current source circuit is discharged, the current I is discharged from the capacitor, and the output voltage of the analog modulator decreases. Since the capacitance value and the current value are constant, if the lengths of the charging time and the discharging time are changed, the maximum voltage and the minimum voltage change. Therefore, as shown in FIG. 10B, when the voltage reaches an intermediate value during the increase, the voltage reaches the maximum voltage VH1 when charging is performed for the charging time t1 corresponding to a 周期 cycle. Next, when discharging is performed for the discharging time 2t1, the voltage becomes the minimum voltage VL1. Next, when charging is performed for the charging time t1, the voltage becomes the intermediate voltage. Further, when charging is performed for a charging time t2 shorter than t1, the voltage becomes the maximum voltage VH2 smaller than VH1. Next, when discharging is performed for the discharging time 2t2, the voltage becomes the minimum voltage VL2 higher than VL1. Next, when charging is performed for the charging time t2, the voltage becomes an intermediate voltage. Hereinafter, the same operation is repeated.
[0035]
In this way, a spread spectrum voltage signal whose amplitude changes every cycle is obtained. Also in the second embodiment, both the amplitude and the period of the spread spectrum voltage signal change. In order to generate a spread spectrum voltage signal in which only the amplitude changes and the cycle does not change, for example, a constant current source for charging or discharging different currents is provided in the circuit of FIG. What is necessary is just to switch the power supply to perform. In this case, the switch switching circuit 31 may switch between charging and discharging at a constant cycle.
[0036]
Here, an example of switching to two amplitudes has been described, but it is also possible to switch to three or more amplitudes.
[0037]
FIG. 11 is a diagram showing a configuration of an SSCG circuit according to a third embodiment of the present invention, which is an embodiment in which the present invention is applied to the configuration disclosed in the aforementioned Japanese Patent Application No. 2002-266631. As shown in FIG. 11, it has a configuration similar to that of the circuit of the first embodiment shown in FIG. 6, and uses a voltage-current converter (VDAC) instead of the voltage adding circuit 16, the VCO 17, the control circuit 21, and the modulator (VDAC) 22. -I conversion) circuit 42, a current digital-to-analog converter (IDAC) 43, a current oscillator (ICO) 44, and a control circuit 41. The VI conversion circuit 42 converts a terminal voltage (difference voltage) of the loop filter 14 into a difference current signal. The IDAC 43 corresponding to the current variable circuit performs spread spectrum modulation on the difference current signal according to the output code from the control circuit 41, and applies the modulated spread spectrum modulated current signal to the current oscillator (ICO) 44.
[0038]
FIG. 12 is a diagram showing a circuit configuration of the frequency phase comparator, and FIG. 13 is a diagram showing a configuration of the charge pump circuit 13. These circuits can be used in the first to third embodiments. Since these circuits are widely known, description thereof is omitted here.
[0039]
FIG. 14 shows a circuit configuration of a VI conversion circuit used in the third embodiment, FIG. 15 shows a configuration of an ICO circuit used in the third embodiment, and FIG. 16 shows a circuit of an IDAC circuit used in the third embodiment. The configuration is shown. These circuits are disclosed in Japanese Patent Application No. 2002-266631, and a detailed description thereof will be omitted, and only relevant operations will be described.
[0040]
The control circuit 41 of the third embodiment is constituted by the logic circuit shown in FIG. 8, generates a control code as shown in FIG.
[0041]
As shown in FIG. 16, the IDAC 43 has a current mirror circuit composed of transistors Tr11 to Tr15, Tr20 and Tr30 to Tr3n. By appropriately setting the size of the transistors as shown in FIG. A current of 90% of the current Iref output from the I conversion circuit 42 flows, a current of 10% of Iref flows in Tr3n, a current of (20 × 1/2 ⁿ⁻² )% of Iref flows in Tr32, A current of (20 × 1/2 ^{n -1} )% of Iref flows through Tr31, and a current of (20 × 1 / ²ⁿ )% of Iref flows through Tr30. When the Tr4n to Tr40 are turned on by the bit data / D0 to / Dn of the output code, a current flows through the corresponding Tr3n to Tr30. Therefore, when all of Tr4n to Tr40 are made non-conductive, a current amount of 90% of Iref flowing through Tr20 is output. A current flows through Tr3n to Tr30, and a current amount of about 110% of Iref is output. That is, by setting the bit data / D0 to / Dn of the output code to an appropriate value, an appropriate amount of current between 90% and about 110% of Iref is output. Therefore, if n = 3, the current amount can be changed by about 1.4% in 15 steps from 90% to about 110% of Iref according to the 4-bit output code of / D0 to / D3. .
[0042]
Therefore, by applying the output code of the up / down counter 58 that changes as shown in FIG. 8B to the IDAC 43 of FIG. 16, the current is between 90% and 108.6% of Iref in the first cycle. In the second period, it changes by about 1.4% from 91.4% to 107.2% of Iref. Note that the period differs between the first period and the second period by about 7%.
[0043]
Since such a current is applied, the ICO 44 repeatedly increases and decreases the frequency (period) by about 1.4% and about ± 10%, and generates a clock CK whose change width and cycle change.
[0044]
In the third embodiment, the number of transistors used for IDAC modulation is four (n = 3), and the output code is also four bits. However, the number of transistors used for IDAC modulation and the output code If the number of bits is increased and the code changes in 15 steps, that is, if only a part of the range of values that can be represented by the output code is used for modulation, the range of variation will be reduced accordingly.
[0045]
Further, in the IDAC shown in FIG. 16, a current of 90% of Iref flows as a base portion by TR20, and 20% of Iref can be changed by a set of TR30 to Tr3n and TR40 to Tr4n. This makes it possible to perform high-resolution modulation by reducing the number of transistors. However, like the IDAC of FIG. 20 described later, Tr12, Tr14, Tr20 are deleted, the Tr size ratio of Tr13 is set to 1, then n is increased, and the output current can be changed with high resolution over the entire range. It may be.
[0046]
In any case, the change range and resolution of the IDAC can be set arbitrarily. For example, if the change amount corresponding to the minimum bit is 0.1%, 97% to 100% can be set in the first cycle. It is also possible to change only the amplitude without changing the period, for example, by changing the period by 0.2%, and by changing the second period from 97.8% to 99.3% by 0.1%.
[0047]
FIG. 17 is a diagram showing the configuration of the SSCG circuit according to the fourth embodiment of the present invention. The SSCG circuit of the fourth embodiment differs from the control circuit 41 of the third embodiment in that a control circuit 45 for generating a code as shown in FIG. 7 by a microcomputer or a DSP is provided. The third embodiment differs from the third embodiment in that an IDAC with a low-pass filter is used.
[0048]
As described in the first embodiment, it is possible to easily generate a code as shown in FIG. 8 by using a computer system controlled by a program such as a microcomputer or a DSP. If the memory capacity of the computer system is sufficient and a large number of codes can be generated, it is also possible to select a code to be output according to a use situation. Furthermore, it is also possible to rewrite the program according to the use situation and to output a desired code.
[0049]
The IDAC of FIG. 18 is a circuit in which a low-pass filter (LPF) composed of a resistor R and a capacitor C is provided in a current output unit of the IDAC of FIG. 16, and the output is further output by a current mirror circuit. . With this circuit, a change in output current caused by a change in the minimum bit / Dn of the output code is smoothed, and glitches (noise) can be reduced. When a current signal having a glitch is supplied to the ICO, the ICO outputs a high-frequency signal according to the glitch. Therefore, a problem occurs in that the PLL is out of the locked state and cannot be converged to the reference frequency. However, if the IDAC with LPF is used, such a problem does not occur.
[0050]
FIG. 19 is a diagram showing the configuration of the SSCG according to the fifth embodiment of the present invention. In the first to fourth embodiments, the amplitude and the period of the spread spectrum modulated signal are changed. As described above, it is possible to change the amplitude without changing the period by changing the IDAC to a high resolution. However, in the fifth embodiment, the amplitude is changed without changing the period by another method.
[0051]
As shown in FIG. 19, the SSCG of the fifth embodiment is different from the fourth embodiment in that a first IDAC 51, a second IDAC 52 and a control circuit 53 for controlling them are provided, and the output of the VI conversion circuit 42 is branched to obtain a spectrum. The spread-modulated signal is added to the output of the original VI conversion circuit 42 and applied to the ICO 44.
[0052]
FIG. 20 is a diagram illustrating a configuration of the first IDAC 51, and FIG. 21 is a diagram illustrating a configuration of the second IDAC 52. The first IDAC 51 is obtained by removing Tr12, Tr14 and Tr20 in the IDAC of FIG. 16 and changing the Tr size ratio of Tr13 to X. The current input Iref is changed from zero to Iref (1-1 / ²ⁿ ) / X. It can be controlled with n bits. Similarly, the second IDAC 52 can control the current input Iref with m bits from Iref / (2 ^m Y) to Iref / Y. Therefore, amplification can be performed at an arbitrary gain within this range by appropriately setting the Y and m-bit control codes.
[0053]
In the fifth embodiment, according to the control code output from the control circuit 53, the first IDAC 51 performs spread-spectrum modulation on a current of 1 / X of Iref with a fixed amplitude and a period as in the conventional case. The second IDAC 52 performs amplification at a constant amplification rate during one cycle of the spread spectrum modulation, and changes the amplification rate when the cycle changes. As a result, a spread spectrum modulated signal whose period is constant and whose amplitude changes only every period is obtained. The spread spectrum modulation signal may be added to Iref from the VI conversion circuit 42 and applied to the ICO 44 (just connect a signal line).
[0054]
Note that the arrangement of the first IDAC 51 and the second IDAC 52 may be reversed, amplification may be performed by changing the amplification factor in each cycle, and the amplified current signal may be subjected to the same spread spectrum modulation as in the related art.
[0055]
(Supplementary Note 1) A frequency / phase comparator that detects a phase difference between the reference clock and the generated clock;
A charge pump that generates a charge / discharge signal according to the phase difference detected by the frequency phase comparator,
A loop filter that generates a difference signal according to the charging signal;
A spread spectrum modulation circuit that modulates the difference signal to generate a spread spectrum modulation signal,
A clock generator that generates a generated clock having a frequency corresponding to the spread spectrum modulated signal,
The spread spectrum clock generation circuit according to claim 1, wherein the spread spectrum modulation circuit generates a spread spectrum modulation signal whose amplitude changes to a plurality of different amplitudes. (1)
(Supplementary note 2) The spread-spectrum clock generation circuit according to supplementary note 1, wherein the spread spectrum modulated signal has a plurality of different periods along with the amplitude.
[0056]
(Supplementary note 3) The spread-spectrum clock generation circuit according to supplementary note 1, wherein the spread-spectrum modulated signal has an amplitude that sequentially changes every period. (2)
(Supplementary Note 4) The spread spectrum clock generation circuit according to supplementary note 1, wherein the clock generator is a voltage controlled oscillator. (3)
(Supplementary Note 5) The spread spectrum modulation circuit includes an analog modulator that generates a spread spectrum analog voltage signal that sequentially changes with a plurality of different amplitudes, and a voltage addition circuit that adds the spread spectrum analog voltage signal to the difference signal. 5. The spread spectrum clock generation circuit according to claim 4, further comprising: (4)
(Supplementary Note 6) The analog modulator changes a capacitance, a constant current source that switches between a state in which the capacitance is charged with a constant current, and a state in which the constant current is discharged from the capacitance, and a switching cycle of the constant current source. 6. The spread spectrum clock generation circuit according to claim 5, further comprising a switching control circuit. (5)
(Supplementary Note 7) The spread spectrum modulation circuit continuously changes between a maximum value and a minimum value for each cycle, and at least one of the maximum value and the minimum value sequentially changes to a plurality of different values for each cycle. Supplementary note 4 comprising: a digital control circuit that generates an output code; a voltage-to-digital converter that generates a spread-spectrum voltage signal according to the output code; and a voltage addition circuit that adds the spread-spectrum voltage signal to the difference signal. 2. A spread spectrum clock generation circuit according to claim 1. (6)
(Supplementary Note 8) A voltage-current conversion circuit that converts the difference signal, which is a voltage signal, into a difference current signal, is further provided.
The clock generator is a current controlled oscillator,
The spread spectrum modulation circuit continuously changes between a maximum value and a minimum value for each cycle, and generates an output code in which at least one of the maximum value and the minimum value sequentially changes to a plurality of different values for each cycle. And a current variable circuit that is provided between the voltage-current conversion circuit and the current-controlled oscillator and that modulates the difference current signal according to the output code to generate a spread-spectrum current modulation signal. 2. The spread spectrum clock generation circuit according to claim 1. (7)
(Supplementary note 9) The spread-spectrum clock generation circuit according to supplementary note 8, wherein the current variable circuit includes a current digital-to-analog conversion circuit that converts the output code into a spread-spectrum current signal of an analog signal and adds the current code to a difference current signal. (8)
(Supplementary Note 10) A voltage-current conversion circuit that converts the difference signal, which is a voltage signal, into a difference current signal, is further provided.
The clock generator is a current controlled oscillator,
The spread spectrum modulation circuit,
A digital control circuit that generates a spectrum modulation code whose value sequentially changes at a predetermined cycle and a level change code that sequentially changes to a plurality of different values at the predetermined cycle,
A first current variable circuit that is provided between the voltage-current conversion circuit and the current control oscillator and modulates a current signal having a predetermined ratio of the difference current signal according to the spectrum modulation code;
A second current variable circuit for amplifying an output of the first current variable circuit in accordance with the level change code, wherein the output of the second current variable circuit is added to the difference current signal. Spread clock generation circuit.
[0057]
(Supplementary Note 11) A voltage-current conversion circuit that converts the difference signal, which is a voltage signal, into a difference current signal, is further provided.
The clock generator is a current controlled oscillator,
The spread spectrum modulation circuit,
A digital control circuit that generates a spectrum modulation code whose value sequentially changes at a predetermined cycle and a level change code that sequentially changes to a plurality of different values at the predetermined cycle,
A first current variable circuit that is provided between the voltage-current conversion circuit and the current-controlled oscillator and amplifies a current signal having a predetermined ratio of the difference current signal according to the level change code;
A second current variable circuit that modulates an output of the first current variable circuit according to the spectrum modulation code, and adds an output of the second current variable circuit to the difference current signal. Spread clock generation circuit.
[0058]
(Supplementary Note 12) The digital control circuit includes a plurality of frequency dividers having different frequency division ratios for dividing a clock, a switching controller for sequentially selecting outputs of the plurality of frequency dividers, and a selected frequency-divided clock. 12. The apparatus according to claim 7, further comprising: an up / down counter that counts, and a counter that counts the divided clock and switches between an up operation and a down operation of the up / down counter at every predetermined count. Spread spectrum clock generation circuit. (9)
(Supplementary Note 13) The spread spectrum clock generation circuit according to any one of Supplementary Notes 7, 8, 10 and 11, wherein the digital control circuit is a computer system under program control. (10)
[0059]
【The invention's effect】
As described above, according to the present invention, it is possible to realize a spread spectrum clock generation circuit capable of performing good spread spectrum with a simple configuration.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration example of a conventional spread spectrum clock generation (SSCG) circuit.
FIG. 2 is a diagram showing a modulator output (spread spectrum modulation signal) in a conventional example.
FIG. 3 is a diagram showing another example of a modulator output (spread spectrum modulation signal) in a conventional example.
FIG. 4 is a diagram showing a principle configuration of the present invention.
FIG. 5 is a diagram illustrating the principle of the present invention and is a diagram illustrating an example of a spread spectrum modulation signal according to the present invention.
FIG. 6 is a diagram illustrating a configuration of an SSCG according to the first embodiment of the present invention.
FIG. 7 is a diagram showing an output (change of code) of the control circuit in the first embodiment.
FIG. 8 is a diagram showing a configuration and an operation of realizing the control circuit of the first embodiment by a logic circuit.
FIG. 9 is a diagram illustrating a configuration of an SSCG according to a second embodiment of the present invention.
FIG. 10 is a diagram illustrating a circuit configuration and operation of an analog modulation circuit according to a second embodiment.
FIG. 11 is a diagram illustrating a configuration of an SSCG according to a third embodiment of the present invention.
FIG. 12 is a diagram illustrating a circuit configuration of a frequency phase comparator.
FIG. 13 is a diagram showing a circuit configuration of a charge pump circuit.
FIG. 14 is a diagram showing a circuit configuration of a voltage-current conversion (VI conversion) circuit.
FIG. 15 is a diagram showing a circuit configuration of a current control oscillation circuit (ICO).
FIG. 16 is a diagram showing a circuit configuration of a current digital-to-analog converter (IDAC).
FIG. 17 is a diagram illustrating a configuration of an SSCG according to a fourth embodiment of the present invention.
FIG. 18 is a diagram showing a circuit configuration of an IDAC with a low-pass filter.
FIG. 19 is a diagram showing a configuration of an SSCG according to a fifth embodiment of the present invention.
FIG. 20 is a diagram showing a circuit configuration of a first IDAC of a fifth embodiment.
FIG. 21 is a diagram showing a circuit configuration of a second IDAC of the fifth embodiment.
[Explanation of symbols]
11 1 / N frequency divider 12 frequency phase comparator 13 charge pump circuit 14 loop filter 16 voltage adding circuit 17 VCO
18 1 / M frequency divider 19 spread spectrum modulation circuit 20 clock generator 21 control circuit 22 modulator (VDAC)

Claims (10)

A frequency-phase comparator for detecting a phase difference between the reference clock and the generated clock;
A charge pump that generates a charge / discharge signal according to the phase difference detected by the frequency phase comparator,
A loop filter that generates a difference signal according to the charging signal;
A spread spectrum modulation circuit that modulates the difference signal to generate a spread spectrum modulation signal,
A clock generator that generates a generated clock having a frequency corresponding to the spread spectrum modulated signal,
The spread spectrum clock generation circuit according to claim 1, wherein the spread spectrum modulation circuit generates a spread spectrum modulation signal whose amplitude changes to a plurality of different amplitudes. 2. The spread spectrum clock generation circuit according to claim 1, wherein the amplitude of the spread spectrum modulation signal changes sequentially in each cycle. 2. The spread spectrum clock generation circuit according to claim 1, wherein said clock generator is a voltage controlled oscillator. 4. The spread spectrum modulation circuit according to claim 3, further comprising: an analog modulator configured to generate a plurality of spread spectrum analog voltage signals varying sequentially with different amplitudes; and a voltage addition circuit configured to add the spread spectrum analog voltage signal to the difference signal. 2. The spread spectrum clock generation circuit according to 1. The analog modulator is a capacitor, a constant current source that switches between a state in which the capacitor is charged with a constant current and a state in which the constant current is discharged from the capacitor, and a switching control circuit that changes a switching cycle of the constant current source. The spread spectrum clock generation circuit according to claim 4, further comprising: The spread spectrum modulation circuit continuously changes between a maximum value and a minimum value for each cycle, and generates an output code in which at least one of the maximum value and the minimum value sequentially changes to a plurality of different values for each cycle. 4. The digital control circuit according to claim 3, further comprising: a voltage digital-to-analog conversion circuit that generates a spread spectrum voltage signal corresponding to the output code; and a voltage addition circuit that adds the spread spectrum voltage signal to the difference signal. 5. Spread spectrum clock generation circuit. A voltage-current conversion circuit that converts the difference signal, which is a voltage signal, into a difference current signal,
The clock generator is a current controlled oscillator,
The spread spectrum modulation circuit continuously changes between a maximum value and a minimum value for each cycle, and generates an output code in which at least one of the maximum value and the minimum value sequentially changes to a plurality of different values for each cycle. And a current variable circuit that is provided between the voltage-current conversion circuit and the current-controlled oscillator and that modulates the difference current signal according to the output code to generate a spread-spectrum current modulation signal. The spread spectrum clock generation circuit according to claim 1. 8. The spread spectrum clock generation circuit according to claim 7, wherein the current variable circuit includes a current digital-to-analog conversion circuit that converts the output code into a spread spectrum current signal of an analog signal and adds the output code to a difference current signal. The digital control circuit includes a plurality of frequency dividers having different division ratios for dividing a clock, a switching controller for sequentially selecting outputs of the plurality of frequency dividers, and an up / down controller for counting the selected divided clock. 8. The spread spectrum clock generation circuit according to claim 6, further comprising a counter, and a counter that counts the frequency-divided clock and switches between an up operation and a down operation of the up / down counter at every predetermined count. 8. The spread spectrum clock generation circuit according to claim 6, wherein said digital control circuit is a computer system controlled by a program.

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