JP2018148450A - Oscillator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an oscillator capable of improving an effective frequency spread while suppressing low-frequency noise in an audible band.SOLUTION: An oscillator 10 having a frequency spread function includes an oscillation circuit 101, a counter 2, a logic circuit 3 and a DAC (D/A converter) 4. The oscillation circuit 101 generates an oscillation signal CLK of an oscillation frequency having a rise/fall component rising and falling at one cycle and an offset component for each cycle and outputs the signal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an oscillator having a frequency spreading function.

  Conventionally, in a DC-DC converter, when the switching frequency is fixed, there is a problem that noise due to switching is concentrated on the frequency and its harmonics. Therefore, conventionally, an oscillator having a frequency spread (spread spectrum) function is provided in a DC-DC converter.

  A configuration example of an oscillator having a frequency spreading function is shown in FIG. An oscillator 10 illustrated in FIG. 1 includes an oscillation circuit 101, a counter 2, a logic circuit 3, and a DAC (D / A converter) 4. The oscillation circuit 101 includes a one-shot circuit 1, an error amplifier 5, a current mirror circuit CM, a transistor Q1, a resistor R1, a capacitor C1, a comparator CP1, and a transistor M1. The oscillation circuit 101 generates and outputs a clock signal CLK (oscillation signal).

  The current mirror circuit CM includes a transistor Tr1 and a transistor Tr2. Both transistors Tr1 and Tr2 are configured by p-channel MOSFETs. The gates of the transistors Tr1 and Tr2 are connected to the drain of the transistor Tr1. The sources of the transistors Tr1 and Tr2 are connected to the application terminal of the power supply voltage Vdd.

  The drain of the transistor Tr2 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to a ground potential application end. A connection point between the drain of the transistor Tr2 and one end of the capacitor C1 is connected to the drain of the transistor M1 configured by an n-channel MOSFET. The source of the transistor M1 is connected to a ground potential application terminal.

  The connection point between the drain of the transistor Tr2 and one end of the capacitor C1 is also connected to the non-inverting input terminal (+) of the comparator CP1. The inverting input terminal (−) of the comparator CP1 is connected to the application end of the reference voltage VREF.

  The output of the comparator CP1 is input to the one-shot circuit 1. The one-shot circuit 1 is a circuit that outputs a one-shot pulse that is set to a high level for a certain time at the timing when the output of the comparator CP1 rises to a high level. The one-shot circuit 1 outputs a clock signal CLK as a one-shot pulse.

  The clock signal CLK is input to the gate of the transistor M1 and also input to the counter 2. The digital output of the counter 2 is input to the DAC 4 via the logic circuit 3. The DAC 4 converts the input digital signal into a reference voltage RTREF, which is an analog signal, and outputs it to the non-inverting input terminal (+) of the error amplifier 5.

  The output of the error amplifier 5 is input to the gate of a transistor Q1 configured with an n-channel MOSFET. The drain of the transistor Q1 is connected to the drain of the transistor Tr1. The source of the transistor Q1 is connected to the inverting input terminal (−) of the error amplifier 5 together with one end of the resistor R1. The other end of the resistor R1 is connected to a ground potential application end.

  The operation of the oscillator 10 having such a configuration will be described. The voltage RT generated at the source of the transistor Q1 is controlled to match the reference voltage RTREF by a circuit including the error amplifier 5 and the transistor Q1. A current I1 is generated by the voltage RT and the resistor R1. That is, the current I1 is proportional to the reference voltage RTREF.

  The current I1 is generated by the current I1 being mirrored by the current mirror circuit CM1. The current I2 flows through the capacitor C1. The capacitor C1 from which the charge has been discharged is charged by the current I2. At this time, the voltage of the capacitor C1 rises at a speed proportional to the current I2.

  When the voltage of the capacitor C1 rises and reaches the reference voltage VREF, the output of the comparator CP1 rises to a high level, and the one-shot circuit 1 outputs a clock signal CLK that is kept at a high level for a certain time. The transistor M1 is turned on by the clock signal CLK, and the capacitor C1 is discharged. Thereby, the frequency (oscillation frequency) of the clock signal CLK is proportional to the reference voltage RTREF.

  The counter 2 advances the count by using the rising of the clock signal CLK to the high level as a trigger. The counter 2 outputs a count value (digital signal) obtained by increasing the count and inputs the count value (digital signal) to the DAC 4 via the logic circuit 3, and the input (digital signal) of the DAC 4 changes. The DAC 4 D / A converts the changed input signal and outputs the changed reference voltage RTREF to the error amplifier 5. Thereby, the frequency of the clock signal CLK is changed.

  By repeating such an operation, the oscillator 10 can change the frequency of the clock signal CLK for each period.

  An example of the related art related to the above is disclosed in Patent Document 1.

Japanese Patent Laid-Open No. 2006-76918

  Here, FIG. 8 shows a configuration example of the counter 2, the logic circuit 3, and the DAC 4 in the oscillator 10. The counter 201 shown in FIG. 8 corresponds to the counter 2, the DAC 401 corresponds to the DAC 4, and the XOR circuits 301 </ b> A to 301 </ b> D constitute the logic circuit 3.

  The counter 201 outputs a count value consisting of 5 bits of bit0 to bit4. The DAC 401 receives a digital signal composed of 5 bits of bit0 to bit4. The counter 201 directly inputs bit4, which is the most significant bit, to bit0, which is the least significant bit of the input of the DAC 401, and inputs it to one input terminal of each of the XOR circuits 301A to 301D. The counter 201 inputs other bits bit0 to bit3 to the other input terminals of the XOR circuits 301A to 301D, respectively. The outputs of the XOR circuits 301A to 301D are input to bit4 to bit1 of the DAC 401.

  The counter 201 counts the counter value from “00000” to “11111”. At this time, the upper 4 bits of bit 4 to bit 1 of the input of the DAC 401 are up-counted from “0000” to “1111” and then down-counted from “1111” to “0000”. Also, bit 0, which is the least significant bit of the input of DAC 401, is “0” during the upper count of the upper 4 bits of the input of DAC 401, and bit 0 is “1” during the down count of the upper 4 bits. It is. That is, when the input of the DAC is represented by a decimal number, it increases by 2 from 0 to 30, and then decreases by 2 from 31 to 1.

  The DAC 401 D / A converts the digital input consisting of bits 0 to 4 and outputs a reference voltage RTREF, and the frequency of the clock signal CLK is proportional to the reference voltage RTREF. Accordingly, the temporal transition of the frequency of the clock signal CLK corresponding to the count by the counter 201 is as shown in FIG. As shown in FIG. 10, in one cycle T10 of frequency spreading, the frequency of the clock signal CLK gradually increases for each cycle of the clock signal CLK and then gradually decreases for each cycle.

  In one cycle T10, the frequency of the clock signal CLK is distributed to 32, so that the frequency can be sufficiently diffused to suppress noise peaks. However, there is a problem that one period T10 of frequency spreading becomes long and low frequency noise occurs in the audible band. Note that noise in the audible band is generated when the frequencies are distributed to 32, and such noise is not always generated.

  Therefore, for example, the counter 2, the logic circuit 3, and the DAC 4 in the oscillator 10 can be configured as shown in FIG. In FIG. 9, the counter 202 corresponds to the counter 2, the DAC 402 corresponds to the DAC 4, and the logic circuit 3 includes the XOR circuits 302A and 302B.

  The configuration shown in FIG. 9 is basically the same as that in FIG. 8, but both the output of the counter 202 and the input of the DAC 402 are 3 bits. The counter 202 counts from “000” to “111”. At this time, the upper 2 bits of the input of the DAC 402 are up-counted from “00” to “11” and then down-counted from “11” to “00”. The least significant bit of the input of the DAC 402 is “0” during the up-count and “1” during the down-count. Therefore, when the digital input of the DAC 402 is represented by a decimal number, it increases by 2 from 0 to 6, and then decreases by 2 from 7 to 1.

  The time transition of the frequency of the clock signal CLK in the oscillator 10 when the configuration shown in FIG. 9 is used is as shown in FIG. As shown in FIG. 11, in one cycle T11 of frequency spreading, the frequency is increased and decreased, and the frequency is dispersed into eight. Since one period T11 of frequency spreading becomes shorter, it is possible to suppress the occurrence of low frequency noise in the audible band as compared with the case shown in FIG. However, since the frequency is dispersed into 8 and not sufficiently dispersed, there is a problem that the noise peak becomes large. That is, the effect of frequency spreading is reduced.

  In view of the above situation, an object of the present invention is to provide an oscillator capable of improving the effect of frequency spreading while suppressing low frequency noise in the audible band.

  The oscillator according to the present invention is configured to output an oscillation signal having an oscillation frequency having an ascending / descending component that rises and falls in one cycle and an offset component for each cycle (first configuration).

In the first configuration, an oscillation circuit that outputs the oscillation signal;
A counter that counts the oscillation signal output from the oscillation circuit;
A DAC (D / A converter) having an input connected to the output of the counter,
Based on the output of the DAC, the oscillation circuit generates the oscillation signal,
The input of the DAC has a first bit indicating an ascending / descending component and a second bit indicating an offset component,
The first bit may be connected to the output of the counter via a logic circuit and / or directly (second configuration).

In the second configuration, the output of the counter and the input of the DAC are each configured with N bits,
The lower K bits of the counter output are connected to the upper K bits of the DAC input,
(NK) bits other than the lower K bits of the output of the counter are connected to (NK) bits other than the upper K bits of the input of the DAC,
The upper K bits of the input of the DAC are the first bits;
The (NK) bits of the input of the DAC may be the second bits (third configuration).

In the third configuration, the most significant bit in the lower K bits of the output of the counter is connected to the least significant bit in the upper K bits of the input of the DAC and to one input terminal of the XOR circuit And
Bits other than the most significant bit in the lower K bits of the output of the counter may be connected to the bits other than the least significant bit in the upper K bits of the input of the DAC via the XOR circuit. 4 configuration).

  In the third or fourth configuration, the (NK) bits of the counter output are connected with the (NK) bits of the input of the DAC being inverted in an upper / lower relationship. It is good also as a thing (5th structure).

In the second configuration,
A counter different from the counter,
The output of the counter is composed of K bits,
The input of the DAC is composed of N bits,
The output of the other counter is composed of (N−K) bits,
The counter performs up-counting and down-counting,
The output of the counter is connected to the upper K bits of the DAC,
The other counter counts the edge of the most significant bit of the output of the counter;
The output of the other counter is connected to a bit other than the upper K bits of the input of the DAC,
The upper K bits of the input of the DAC are the first bits;
Bits other than the upper K bits of the input of the DAC may be the second bit (sixth configuration).

  In the sixth configuration, the output of the counter may be directly connected to the upper K bits of the DAC (seventh configuration).

  Further, in the sixth or seventh configuration, the output of the other counter may be connected by inverting the upper / lower relationship to bits other than the upper K bits of the input of the DAC ( Eighth configuration).

  According to the oscillator of the present invention, the effect of frequency spreading can be improved while suppressing low frequency noise in the audible band.

It is a figure showing an example of 1 composition of an oscillator concerning an embodiment of the present invention. It is a figure which shows the structure using the counter and DAC which concern on 1st Embodiment of this invention. It is a figure which shows the structure using the counter and DAC which concern on 2nd Embodiment of this invention. It is a table | surface which shows transition of the output bit of the counter which concerns on 1st Embodiment of this invention, and the input bit of DAC. It is a table | surface which shows transition of the output bit of the counter which concerns on 2nd Embodiment of this invention, and the input bit of DAC. It is a figure which shows the time transition of the frequency of the clock signal which concerns on 1st Embodiment of this invention. It is a figure which shows the time transition of the frequency of the clock signal which concerns on 2nd Embodiment of this invention. It is a figure which shows the structure using the counter and DAC which concern on the 1st comparative example with this invention. It is a figure which shows the structure using the counter and DAC which concern on the 2nd comparative example with this invention. It is a figure which shows the time transition of the frequency of the clock signal which concerns on the 1st comparative example with this invention. It is a figure which shows the time transition of the frequency of the clock signal which concerns on the 2nd comparative example with this invention.

  An embodiment of the present invention will be described below with reference to the drawings. The configuration of the oscillator according to the embodiment of the present invention is basically the same as the configuration of the oscillator 10 shown in FIG. Since the configuration of the oscillator 10 itself has been described above, a detailed description thereof will be omitted here. Hereinafter, an embodiment relating to the configuration of the counter 2, the logic circuit 3, and the DAC 4 in the oscillator 10 will be described.

<First Embodiment>
A specific configuration of the counter 2, the logic circuit 3, and the DAC 4 according to the first embodiment of the present invention is shown in FIG. The counter 21 shown in FIG. 2 corresponds to the counter 2, the DAC 41 corresponds to the DAC 4, and the logic circuit 3 includes the XOR circuits 31A and 31B.

  The counter 21 outputs a count value consisting of 5 bits of bit0 to bit4. The DAC 41 receives a digital signal consisting of 5 bits of bit0 to bit4. The lower 3 bits (bit0 to bit2) of the output of the counter 21 are connected to the upper 3 bits (bit2 to bit4) of the input of the DAC 41. Bit 2 which is the most significant bit among the lower 3 bits of the output of the counter 21 is directly connected to bit 2 which is the least significant bit among the upper 3 bits of the input of the DAC 41. The output bit 2 of the counter 21 is also connected to one input terminal of each of the XOR circuits 31A and 31B.

  Of the lower 3 bits of the output of the counter 21, bit1 is connected to the other input terminal of the XOR circuit 31A. Of the lower 3 bits of the output of the counter 21, bit0 is connected to the other input terminal of the XOR circuit 31B. The output of the XOR circuit 31A is connected to the input bit 4 of the DAC 41. The output of the XOR circuit 31B is connected to the input bit 3 of the DAC 41. That is, the bits other than the most significant bit (bit1, bit0) in the lower 3 bits of the output of the counter 21 have XOR circuits 31A and 31B added to the bits (bit4, bit3) other than the least significant bit in the upper 3 bits of the input of the DAC 41. Connected through.

  That is, the most significant bit (bit 1) of the lower 3 bits of the output of the counter 21 other than the most significant bit is the most significant bit of the higher 3 bits of the input of the DAC 41 other than the least significant bit. (Bit 4) is connected via the XOR circuit 31A. Each time one bit is shifted from the most significant bit among the lower 3 bits of the output of the counter 21 from the most significant bit, the shifted bit (bit 0) is the least significant bit of the upper 3 bits of the input of the DAC 41. A bit (bit 3) shifted bit by bit from the most significant bit other than the bits is connected via the XOR circuit 31B.

  Of the upper 2 bits of the output of the counter 21, bit 4 is connected to bit 0 of the lower 2 bits of the input of the DAC 41, and bit 3 of the output of the counter 21 is connected to the bit 1 of the input of the DAC 41. That is, the upper 2 bits (bit4, bit3) of the output of the counter 21 and the lower 2 bits (bit1, bit0) of the input of the DAC 41 are connected by inverting the upper / lower relationship. That is, 2 (= 5-3) bits other than the lower 3 bits of the output of the counter 21 are connected to 2 (= 5-3) bits other than the upper 3 bits of the input of the DAC 41.

  FIG. 4 shows the transition of the output bits of the counter 21 and the input bits of the DAC 41 when the counter 21 counts in the configuration shown in FIG. In the table shown in FIG. 4, the rightmost column indicates numerical values representing the input of the DAC 41 in decimal numbers.

  The counter 21 counts from “00000” to “11111”. During the count from “00000” to “00111” (referred to as the first count), the upper 3 bits of the input bits of the DAC 41 rise from “000” to “111” and then fall to “001”. The same rise and fall of the input bits of the DAC 41 are caused by the counter 21 from “01000” to “01111” (referred to as the second count), from “10000” to “10111” (referred to as the third count), and “ It is also performed between each count from “11000” to “11111” (referred to as a fourth count). That is, the upper 3 bits of the input of the DAC 41 correspond to a bit (first bit) indicating an ascending / descending component.

  At this time, the lower 2 bits of the input of the DAC 41 are “00” in the first count, “10” in the second count, “01” in the third count, and “11” in the fourth count. That is, the lower 2 bits of the input of the DAC 41 correspond to a bit (second bit) indicating an offset component.

  Thereby, in the first count, the value represented by the decimal number of the input of the DAC 41 increases by 8 from 0 to 24 and then decreases by 8 from 28 to 4. In the second count, the decimal value increases by 8 from 2 to 26 and then decreases by 8 from 30 to 6. The lower 2 bits “10” of the input of the DAC 41 in the second count have an offset of “+2” in the decimal number with reference to the lower 2 bits “00” of the input of the DAC 41 in the first count. Accordingly, in the second count, the decimal value input to the DAC 41 has an offset of “+2” while maintaining the same rise and fall with the first count as a reference.

  Similarly, since the lower 2 bits of the input of the DAC 41 are “01” in the third count, the decimal value of the input of the DAC 41 has an offset of “+1” with reference to the first count. As a result, in the third count, the value representing the input of the DAC 41 in decimal number increases by 8 from 1 to 25 and then decreases by 8 from 29 to 5.

  Similarly, since the lower 2 bits of the input of the DAC 41 are “11” in the fourth count, the decimal value of the input of the DAC 41 has an offset of “+3” on the basis of the first count. As a result, in the fourth count, the value representing the input of the DAC 41 in decimal number increases by 8 from 3 to 27 and then decreases by 8 from 31 to 7.

  The DAC 41 D / A converts the digital input composed of bit 0 to bit 4 and outputs a reference voltage RTREF, and the frequency of the clock signal CLK is proportional to the reference voltage RTREF. Therefore, the temporal transition of the frequency of the clock signal CLK corresponding to the count by the counter 21 is as shown in FIG.

  In FIG. 6, one period T1 to T4 is a period corresponding to each of the first count to the fourth count. Thus, in each of the periods T2 to T4, the frequency of the clock signal CLK has a different offset while maintaining the same rise and fall with respect to the one period T1. That is, the frequency (oscillation frequency) of the clock signal CLK (oscillation signal) has an ascending / descending component that rises and falls in one cycle and an offset component for each cycle.

  In FIG. 6, noise of each frequency of 1/8, 1/16, and 1/32 of the frequency of one clock of the clock signal CLK occurs, but noise of 1/8 of the frequency becomes dominant. Generation of low frequency noise in the audible region can be suppressed.

  Moreover, the broken line shown in FIG. 6 shows the level of the frequency which arises in 1 period T1-T4. As described above, in the present embodiment, the frequency is distributed to 32 frequencies in a cycle including one cycle T1 to T4. Therefore, noise peaks can be suppressed by sufficient frequency spreading.

  Thus, in this embodiment, the effect of frequency spreading can be improved while suppressing low frequency noise in the audible band.

Second Embodiment
FIG. 3 shows specific configurations of the counter 2 and the DAC 4 according to the second embodiment of the present invention. The first counter 22 shown in FIG. 3 corresponds to the counter 2, and the DAC 42 corresponds to the DAC 4. In the present embodiment, the logic circuit 3 is not configured. Further, a second counter 50 different from the first counter 22 is provided between the first counter 22 and the DAC 42.

  The counter 22 outputs a count value composed of 3 bits of bit0 to bit2. The DAC 42 receives a digital signal composed of 5 bits of bit0 to bit4. The second counter 50 outputs a 2-bit count value obtained by subtracting the number of output bits of the first counter 22 from the number of input bits of the DAC 42.

  The 3 bits (bit0 to bit2) of the output of the first counter 22 are directly connected to the upper 3 bits (bit2 to bit4) of the input of the DAC 42. The second counter 50 counts the rising edge of the most significant bit (bit 2) of the output of the first counter 22. The second counter 50 outputs a count value composed of 2 bits (bit0, bit1). Each bit of the output of the second counter 50 is connected to the lower two bits (bit0, bit1) of the input of the DAC 42 by inverting the upper / lower relationship.

  FIG. 5 shows the transition of the output bits of the first counter 22 and the second counter 50 and the input bits of the DAC 42 when the first counter 22 counts in the configuration shown in FIG. In the table shown in FIG. 5, the rightmost column indicates numerical values representing the input of the DAC 42 in decimal numbers.

  The first counter 22 counts up from “100” to “111”, then counts down to “001”, and then counts up to “011” (hereinafter referred to as “first count”). After that, after counting up again from “100” to “111”, it counts down to “001” and then counts up to “011” (hereinafter referred to as a second count). After that, after counting up again from “100” to “111”, it counts down to “001” and then counts up to “011” (hereinafter referred to as a third count). After that, after counting up again from “100” to “111”, it counts down to “001” and then counts up to “011” (hereinafter referred to as the fourth count).

  The output of the second counter 50 starts from “00”, and the second counter 50 is changed when the output of the first counter 22 is switched from “011” to “100”, that is, from the first count to the second count. At the same time, the rising edge of bit 2 is counted and the output is set to “01”. Further, at the same time as the change from the second count to the third count, the rising edge of bit 2 is counted and the output is set to “10”. Further, at the same time when the third count is changed to the fourth count, the rising edge of bit 2 is counted and the output is set to “11”. Further, at the same time as the change from the fourth count to the zeroth count, the rising edge of bit 2 is counted and the output is set to “00”.

  During the first count, the upper 3 bits of the input of the DAC 42 rise and fall in the same manner as the output of the first counter 22. At this time, the lower 2 bits of the input of the DAC 42 sequentially take the value “00”. Further, during the second count, the upper 3 bits of the input of the DAC 42 rise and fall in the same manner as the output of the first counter 22. This rise and fall is the same as the rise and fall during the first count. At this time, the lower 2 bits of the input of the DAC 42 sequentially take a value of “10”. Further, during the third count, the upper 3 bits of the input of the DAC 42 rise and fall in the same manner as the output of the first counter 22. This rise and fall is the same as the rise and fall during the first count. At this time, the lower 2 bits of the input of the DAC 42 sequentially take a value of “01”. Further, during the fourth count, the upper 3 bits of the input of the DAC 42 rise and fall in the same manner as the output of the first counter 22. This rise and fall is the same as the rise and fall during the first count. At this time, the lower 2 bits of the input of the DAC 42 sequentially take a value of “11”. That is, the upper 3 bits of the input of the DAC 42 correspond to the bit (first bit) indicating the rising / falling component, and the bits other than the upper 3 bits of the input of the DAC 42 are the bits (second bit) indicating the offset component. Applicable.

  The lower 2 bits “10” of the input of the DAC 42 in the second count have an offset of “+2” in decimal notation with respect to the lower 2 bits “00” of the input of the DAC 42 in the first count. The lower two bits “01” of the input of the DAC 42 in the third count have an offset of “+1” in decimal notation with respect to the lower two bits “00” of the input of the DAC 42 in the first count. The lower 2 bits “11” of the input of the DAC 42 in the fourth count have an offset of “+3” in decimal notation with respect to the lower 2 bits “00” of the input of the DAC 42 in the first count.

  As a result, the decimal value of the input of the DAC 42 increases by “4” from “16” to “28” during the first count, decreases by “4” to “4”, and “12”. Corresponding to an increase of “4” until “4”, and an increase of “4” from “18” to “30” by an offset of “+2” with reference to the first count between the second count and “6” "4" to "14" and "4" to "14".

  Then, during the third count, with the offset of “+1” with respect to the first count, the value increases from “17” to “29” by “4”, decreases to “5” by “4”, and decreases to “13”. Corresponds to increasing by “4”.

  Further, during the fourth count, the offset increases by “4” from “19” to “31” by “+3” with respect to the first count, and decreases by “4” until “7”. Corresponds to increasing by “4”.

  The time transition of the frequency of the clock signal CLK corresponding to the count by the counter 22 is as shown in FIG.

  In FIG. 7, one cycle T5 to T8 is a period corresponding to each of the first count to the fourth count. In this way, in one cycle T6 to T8, the frequency of the clock signal CLK has an offset while maintaining the same rise and fall with reference to the one cycle T5. That is, the frequency (oscillation frequency) of the clock signal CLK (oscillation signal) has an ascending / descending component that rises and falls in one cycle and an offset component for each cycle.

  In FIG. 7, noise having a frequency that is 1/12 of the frequency of one clock of the clock signal CLK is dominant, so that it is possible to suppress the occurrence of low-frequency noise in the audible region.

  Moreover, the broken line shown in FIG. 7 shows the level of the frequency generated in one cycle T5 to T8. As described above, in the present embodiment, the frequency is distributed to 28 frequencies in a cycle including one cycle T5 to T8. Therefore, noise peaks can be suppressed by sufficient frequency spreading.

  Thus, even in the present embodiment, the effect of frequency spreading can be improved while suppressing low frequency noise in the audible band.

<Other variations>
As mentioned above, although embodiment of this invention was described, if it is in the range of the meaning of this invention, embodiment can be variously deformed.

  For example, in the configuration of FIG. 2 described in the first embodiment, the XOR circuits 31A and 31B are provided, but without the XOR circuit, the bit2, bit1, and bit0 of the counter 21 are respectively set to the input bit2 of the DAC 41, You may connect directly to bit4 and bit3. As a result, the upper 3 bits of the input of the DAC 41 indicating the ascending / descending component rise from “000” to “110”, descend to “001”, and then rise again to “111”. Even in this way, the object of the present invention can be achieved.

  In the first embodiment, the lower 2 bits of the input of the DAC 41 indicating the offset component may be connected without inverting the upper / lower relationship with the upper 2 bits of the output of the counter 21.

  In the second embodiment (FIG. 3), the upper 3 bits of the DAC 42 indicating the rising / falling component may be connected to each of the output bits of the first counter 22 via an inverter. As a result, the upper 3 bits of the DAC 42 become values that rise and then fall again after falling, but the object of the present invention is achieved. The inverter constitutes the logic circuit 3.

  The present invention can be used for an oscillator used for a DC-DC converter, for example.

1 One-shot circuit 2 Counter 3 Logic circuit 4 DAC (D / A converter)
5 Error Amplifier 10 Oscillator 101 Oscillator Circuit CM Current Mirror Circuit Tr1, Tr2 Transistor Q1 Transistor C1 Capacitor M1 Transistor CP1 Comparator R1 Resistor 21 Counter 41 DAC
31A, 31B XOR circuit 22 First counter 42 DAC
50 Second counter 201, 202 Counter 301A to 301D, 302A, 302B XOR circuit 401, 402 DAC

Claims (8)

  An oscillator characterized by outputting an oscillation signal having an oscillation frequency having an ascending / descending component that rises and falls in one cycle and an offset component for each cycle. An oscillation circuit for outputting the oscillation signal;
A counter that counts the oscillation signal output from the oscillation circuit;
A DAC (D / A converter) having an input connected to the output of the counter,
Based on the output of the DAC, the oscillation circuit generates the oscillation signal,
The input of the DAC has a first bit indicating an ascending / descending component and a second bit indicating an offset component,
The oscillator according to claim 1, wherein the first bit is connected to the output of the counter via a logic circuit and / or directly. The counter output and the DAC input are each composed of N bits,
The lower K bits of the counter output are connected to the upper K bits of the DAC input,
(NK) bits other than the lower K bits of the output of the counter are connected to (NK) bits other than the upper K bits of the input of the DAC,
The upper K bits of the input of the DAC are the first bits;
The oscillator according to claim 2, wherein the (N−K) bits of the input of the DAC are the second bits. The most significant bit in the lower K bits of the output of the counter is connected to the least significant bit in the upper K bits of the input of the DAC and to one input terminal of the XOR circuit,
The bit other than the most significant bit in the lower K bits of the output of the counter is connected to a bit other than the least significant bit in the upper K bits of the input of the DAC via the XOR circuit. Oscillator.   5. The (NK) bit of the counter output is connected to the (NK) bit of the DAC input by inverting the upper / lower relationship. Oscillator. A counter different from the counter,
The output of the counter is composed of K bits,
The input of the DAC is composed of N bits,
The output of the other counter is composed of (N−K) bits,
The counter performs up-counting and down-counting,
The output of the counter is connected to the upper K bits of the DAC,
The other counter counts the edge of the most significant bit of the output of the counter;
The output of the other counter is connected to a bit other than the upper K bits of the input of the DAC,
The upper K bits of the input of the DAC are the first bits;
The oscillator according to claim 2, wherein bits other than the upper K bits of the input of the DAC are the second bits.   The oscillator of claim 6, wherein the output of the counter is directly connected to the upper K bits of the DAC.   8. The oscillator according to claim 6, wherein an output of the another counter is connected to a bit other than the upper K bits of the input of the DAC by inverting an upper / lower relationship.

Images