JP2010206990A - Circuit and method for controlling power-supply voltage, and dc-dc converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit and a method for controlling a power-supply voltage, maintaining a switching frequency at a desired frequency, and to provide a DC-DC converter. <P>SOLUTION: A control circuit 1a includes a comparator 20 generating an output signal S1 at a level corresponding to the result of a comparison between an output voltage Vo and a first reference voltage Vr1, and a frequency-difference detector 40 detecting a period difference (Tr-Tsw) between the switching period Tsw of an output transistor T1 and a reference period Tr. The control circuit 1a further includes a pulse generator 30 generating on-pulses of a pulse width corresponding to the period difference (Tr-Tsw) in response to an H-level output signal S1 from the comparator 20. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a power supply voltage control circuit, a power supply voltage control method, and a DC-DC converter.

Conventionally, a comparator-type DC-DC converter is known as a control method capable of high-speed response to a sudden load change (see, for example, Patent Documents 1 and 2).
FIG. 16 shows an example of a conventional comparator type on-time fixed type DC-DC converter. The DC-DC converter 1e is a step-down DC-DC converter that generates an output voltage Vo obtained by stepping down an input voltage Vin, and includes a control circuit 10e and a converter unit. The converter unit includes an output transistor T1, a diode D1, a choke coil L1, and a smoothing capacitor C1.

  The comparator 20 in the control circuit 10e compares the output voltage Vo with the reference voltage Vr, and outputs an output signal S1 having a level corresponding to the comparison result to the one-shot flip-flop (FF) circuit 21.

  When the output voltage Vo is lower than the reference voltage Vr and the H level output signal S1 is input, the FF circuit 21 is set, outputs the H level drive signal SG1 for a certain period of time, and keeps the output transistor T1 constant. Turn on for hours. Then, when a certain time has elapsed, the FF circuit 21 returns to the reset state, outputs an L level drive signal SG1, and turns off the output transistor T1.

  In such a DC-DC converter 1e, the output voltage Vo rises based on the ON operation of the output transistor T1, and when the output transistor T1 is turned off after a predetermined time, the energy stored in the choke coil L1 is released. . When the energy stored in the choke coil L1 decreases and the output voltage Vo decreases, and the output voltage Vo becomes lower than the reference voltage Vr, the drive signal SG1 of the FF circuit 21 becomes H level for a certain time, and the output transistor T1 It is turned on again. By such an operation, the output voltage Vo output from the output terminal To is maintained at a constant voltage (target voltage) based on the reference voltage Vr.

  FIG. 17 shows an example of a conventional hysteresis comparator type DC-DC converter. The DC-DC converter 2c includes a control circuit 11c and a converter unit. The configuration of the converter section is the same as that of the fixed on-time DC-DC converter shown in FIG.

  In the hysteresis comparator 90 of the control circuit 11c, the output voltage Vo is input to the inverting input terminal, and the reference voltage Vr is input to the non-inverting input terminal. In the hysteresis comparator 90, a lower limit reference voltage and an upper limit reference voltage based on the reference voltage Vr are set. The hysteresis comparator 90 compares the output voltage Vo and the reference voltage Vr (lower limit reference voltage and upper limit reference voltage), and outputs a drive signal SG2 having a level corresponding to the comparison result to the output transistor T1.

  In such a DC-DC converter 2c, when the output voltage Vo becomes lower than the lower limit reference voltage of the hysteresis comparator 90, an H level drive signal SG2 is output from the hysteresis comparator 90 and the output transistor T1 is turned on. Then, the current flowing through the choke coil L1 increases and the output voltage Vo gradually increases. When the output voltage Vo becomes higher than the upper limit reference voltage of the hysteresis comparator 90, an L level drive signal SG2 is output from the hysteresis comparator 90 and the output transistor T1 is turned off. As a result, the energy stored in the choke coil L1 decreases and the output voltage Vo decreases, and when the output voltage Vo becomes lower than the lower limit reference voltage, the output transistor T1 is turned on again. With such an operation, the ripple width of the output voltage Vo is maintained constant, and the output voltage Vo output from the output terminal To is maintained at a target voltage based on the reference voltage Vr.

  In these comparator type DC-DC converters 1e and 2c, the output voltage Vo and the reference voltage Vr can be directly compared by the comparator 20 (or the hysteresis comparator 90), and the output transistor T1 can be immediately turned on / off. . For this reason, in these DC-DC converters 1e and 2c, a high-speed response is possible with respect to a sudden load change.

JP 2007-174772 A JP 2004-104942 A

  However, in the comparator DC-DC converters 1e and 2c, when the input voltage Vin, the output voltage Vo, or the output current Io varies, the switching duty of the output transistor T1 varies. As a result, the switching frequency (switching cycle) of the output transistor T1 varies. For this reason, when a plurality of DC-DC converters are operated, there is a problem that due to the difference in switching frequency between the DC-DC converters, the plurality of switching frequencies interfere with each other to generate EMI noise.

  A power supply voltage control circuit aims to maintain a switching frequency at a desired frequency.

  The disclosed power supply voltage control circuit includes: a pulse generator that generates an on pulse or an off pulse according to an output voltage or an output current; a switching frequency of a switching element that is on / off controlled by the on pulse or the off pulse; and a reference frequency A frequency difference detector for detecting a frequency difference, and the pulse generator adjusts a pulse width of the on-pulse or the off-pulse according to the frequency difference detected by the frequency difference detector.

  According to the disclosed power supply voltage control circuit, the switching frequency can be maintained at a desired frequency.

The circuit diagram which shows the DC-DC converter of 1st Embodiment. The circuit diagram which shows the internal structural example of a frequency detector. The circuit diagram which shows the internal structural example of a pulse generator. The timing chart which shows operation | movement of a DC-DC converter. Explanatory drawing which shows the simulation result at the time of load sudden increase. Explanatory drawing which shows the simulation result at the time of sudden load reduction. The circuit diagram which shows the DC-DC converter of 2nd Embodiment. The circuit diagram which shows the internal structural example of a pulse generator. The circuit diagram which shows the DC-DC converter of 3rd Embodiment. The circuit diagram which shows the DC-DC converter of 4th Embodiment. The circuit diagram which shows the internal structural example of a hysteresis comparator. The timing chart which shows operation | movement of a DC-DC converter. The circuit diagram which shows the DC-DC converter of 5th Embodiment. The circuit diagram which shows the internal structural example of a frequency detector. The circuit diagram which shows the DC-DC converter of a modification. The circuit diagram which shows the conventional DC-DC converter. The circuit diagram which shows the conventional DC-DC converter.

(First embodiment)
Hereinafter, a first embodiment will be described with reference to FIGS. In the present embodiment, the same components as those shown in FIG. 16 will be described with the same reference numerals.

  A DC-DC converter 1a shown in FIG. 1 is a comparator-type DC-DC converter. The DC-DC converter 1a is a step-down DC-DC converter that generates an output voltage Vo obtained by stepping down an input voltage Vin, and includes a DC-DC converter control circuit (control circuit) 10a and a converter unit. The converter unit includes an output transistor T1, a diode D1, a choke coil L1, and a smoothing capacitor C1. In the present embodiment, the output transistor T1 is an N-channel MOS transistor.

  The drive signal SG1 output from the control circuit 10a is supplied to the gate of the output transistor T1, and the input voltage Vin is supplied to the drain of the output transistor T1. The source of the output transistor T1 is connected to the cathode of the diode D1, and the anode of the diode D1 is connected to the ground. A connection point between the output transistor T1 and the diode D1 is connected to the output terminal To via the choke coil L1. The output terminal To is connected to the ground via a smoothing capacitor C1. The choke coil L1 and the smoothing capacitor C1 function as a smoothing circuit.

  The output transistor T1 is controlled to be turned on / off based on the drive signal SG1 from the control circuit 10a, whereby the input voltage Vin is stepped down and applied to a load (not shown) connected to the output terminal To as the output voltage Vo. Is output. Further, an output current Io is supplied to this load.

The output terminal To is connected to the control circuit 10a, and the output voltage Vo at that time is fed back to the control circuit 10a.
The control circuit 10 a includes a comparator 20, a pulse generator 30, a frequency difference detector 40, and an error amplifier 50.

  In the comparator 20, the output voltage Vo (feedback signal) is input to the inverting input terminal, and the first reference voltage Vr1 is input to the non-inverting input terminal. The first reference voltage Vr1 is a voltage generated by the first reference power supply e1, and is set according to the target voltage of the output voltage Vo.

  The comparator 20 compares the output voltage Vo and the first reference voltage Vr1, and generates an output signal S1 having a level corresponding to the comparison result. Specifically, the comparator 20 generates the L level output signal S1 when the output voltage Vo is higher than the first reference voltage Vr1, and outputs the H level when the output voltage Vo becomes lower than the first reference voltage Vr1. A signal S1 (detection signal) is generated.

  The output signal S1 of the comparator 20 is input to the set terminal of the pulse generator 30. When the H level output signal S1 is input to the set terminal, the pulse generator 30 enters the set state, outputs the H level drive signal SG1 for a predetermined time, and turns on the output transistor T1 for a predetermined time. When a predetermined time elapses, the pulse generator 30 returns to the reset state, outputs an L level drive signal SG1, and turns off the output transistor T1. That is, the pulse generator 30 outputs an ON pulse (H level drive signal SG1) having a predetermined pulse width to the output transistor T1 based on the H level output signal S1.

  In the first control loop including the comparator 20, the pulse generator 30, and the converter unit, the output voltage Vo is controlled to be maintained at a constant voltage (target voltage) based on the first reference voltage Vr1. That is, in the first control loop, when the output transistor T1 is turned off, the energy stored in the choke coil L1 is released when the output transistor T1 is turned on. When the energy stored in the choke coil L1 decreases and the output voltage Vo decreases, and the output voltage Vo becomes lower than the first reference voltage Vr1, the drive signal SG1 of the pulse generator 30 becomes H level for a predetermined time, and output The transistor T1 is turned on again. Thereafter, such an operation is repeated, and the output voltage Vo is maintained at the target voltage based on the first reference voltage Vr1.

  The drive signal SG1 of the pulse generator 30 is also input to the frequency difference detector 40. The frequency difference detector 40 detects a switching period Tsw (switching frequency) of the output transistor T1 based on the drive signal SG1, and detects a period difference (frequency difference) between the switching period Tsw and a desired reference period Tr. . The frequency difference detector 40 includes a frequency detector 41 and a calculator 42.

  The frequency detector 41 receives the drive signal SG1 from the pulse generator 30 at its input terminal and the reference clock signal CK from the oscillator 43 at its clock terminal. The reference clock signal CK is a clock signal having a sufficiently high frequency (for example, 32 times) with respect to the switching frequency. The frequency detector 41 detects the switching period Tsw of the output transistor T1 based on the drive signal SG1 and the reference clock signal CK. That is, the frequency detector 41 detects the switching period Tsw of the output transistor T1 by counting the number of reference clock signals CK (the number of rising edges) between the rising edges of the drive signal SG1. Here, the switching period Tsw is a count value obtained by counting the reference clock signal CK, and is an M-bit digital signal.

  The computing unit 42 receives the switching period Tsw from the frequency detector 41 and a desired reference period Tr, and detects a period difference (Tr−Tsw) between the switching period Tsw and the reference period Tr. The computing unit 42 outputs a period difference signal S2 indicating the detected period difference (Tr−Tsw) to the error amplifier 50. The reference period Tr is a count value obtained by counting the reference clock signal CK, and is an M-bit digital signal, like the switching period Tsw.

  The error amplifier 50 amplifies the period difference (Tr−Tsw) and outputs the amplified N-bit digital signal to the pulse generator 30 as the pulse width adjustment signal S3. The error amplifier 50 has the same configuration as a digital filter such as an IIR filter or an FIR filter, and functions as a digital error amplifier. The relationship between the M bit and the N bit is generally M bit ≦ N bit.

  The pulse generator 30 adjusts the pulse width of the on-pulse (H level drive signal SG1) in accordance with the pulse width adjustment signal S3 from the error amplifier 50. That is, the pulse generator 30 adjusts the on-pulse width according to the pulse width adjustment signal S3 so that the switching period Tsw approaches the reference period Tr. The pulse generator 30 outputs the ON pulse having the adjusted pulse width to the output transistor T1 and the frequency difference detector 40 in response to the H level output signal S1. The pulse generator 30 is a digital mono-multi circuit that varies the pulse width in accordance with the pulse width adjustment signal S3 that is a digital signal.

  In the second control loop including the frequency difference detector 40, the error amplifier 50, and the pulse generator 30, the switching period Tsw is controlled to be maintained at a desired reference period Tr by adjusting the on-pulse width. The That is, in the second control loop, when the switching cycle Tsw is shorter than the reference cycle Tr, the cycle difference signal S2 has a positive value, and thus the pulse width adjustment signal S3 for increasing the on-pulse width is generated. The In response to the pulse width adjustment signal S3, the pulse generator 30 adjusts the on-pulse width to increase. Here, if the input voltage Vin, the output voltage Vo, and the output current Io are constant as in the steady state, the switching cycle Tsw changes in proportion to the on-pulse width. For this reason, when the on-pulse width is increased, the switching cycle Tsw becomes longer (the switching frequency becomes lower). On the other hand, when the switching period Tsw is longer than the reference period Tr, the period difference signal S2 has a negative value, so that the pulse width adjustment signal S3 for reducing the on-pulse width is generated. In response to the pulse width adjustment signal S3, the pulse generator 30 adjusts so that the on-pulse width decreases. Thereby, the switching cycle Tsw is shortened (the switching frequency is increased).

  In the present embodiment, compared to the band of the first control loop including the comparator 20, the pulse generator 30, and the converter unit, the second including the frequency difference detector 40, the error amplifier 50, and the pulse generator 30. The bandwidth of the control loop is set to be sufficiently narrow.

Next, an example of the internal configuration of the frequency detector 41 will be described with reference to FIG.
The frequency detector 41 includes two D-flip flop (D-FF) circuits 41a and 41b, a NAND circuit 41c, a counter 41d, and an output D-FF circuit 41e. The reference clock signal CK from the oscillator 43 is input to the clock terminals of the D-FF circuits 41a and 41b. The drive signal SG1 is input from the pulse generator 30 to the input terminal D of the D-FF circuit 41a. The output terminal Q of the D-FF circuit 41a is connected to the input terminal D of the next-stage D-FF circuit 41b and the NAND circuit 41c. The inverting output terminal XQ of the D-FF circuit 41b is connected to the NAND circuit 41c. The output terminal of the NAND circuit 41c is connected to the clear terminal CL of the counter 41d.

  The D-FF circuit 41a outputs from the output terminal Q a signal having the level of the drive signal SG1 input to the input terminal D in synchronization with the rising edge of the reference clock signal CK. The D-FF circuit 41b outputs a signal having a level obtained by inverting the level of the input terminal D from the inverted output terminal XQ in synchronization with the rising edge of the reference clock signal CK. The NAND circuit 41c outputs an L level signal that is a clear signal when both the output signals of the D-FF circuits 41a and 41b are at the H level. That is, the D-FF circuits 41a and 41b and the NAND circuit 41c output a clear signal to the counter 41d when the rising edge of the drive signal SG1 is detected in synchronization with the rising of the reference clock signal CK. Thus, the D-FF circuits 41a and 41b and the NAND circuit 41c function as a clear signal generation circuit.

  The reference clock signal CK is input to the clock terminal of the counter 41d. The output terminal of the counter 41d is connected to the input terminal D of the next stage D-FF circuit 41e. The counter 41d counts rising edges of the reference clock signal CK and outputs the count value CNT to the input terminal D of the D-FF circuit 41e. The count value CNT of the counter 41d is reset to zero each time a clear signal is input to the clear terminal CL. Thus, the counter 41d counts the number of reference clock signals CK (the number of rising edges) input during the period from the clear signal to the next clear signal being input, and outputs the count value CNT. That is, the counter 41d counts the number of reference clock signals CK input in a period substantially corresponding to a period (one cycle) from the rising edge to the next rising edge of the drive signal SG1. For this reason, the count value CNT of the counter 41d corresponds to the switching cycle Tsw. The count value CNT is an M-bit digital signal.

  The drive signal SG1 from the pulse generator 30 is input to the clock terminal of the D-FF circuit 41e. The output terminal Q of the D-FF circuit 41e is connected to the computing unit 42 (see FIG. 1). Although not shown, the D-FF circuit 41e includes M D-FF circuits 41e corresponding to each bit of the input count value CNT (M bit signal). Each of these D-FF circuits 41e outputs from the output terminal Q a signal having the level of the count value CNT input to the input terminal D in synchronization with the rising edge of the drive signal SG1. That is, the D-FF circuit 41e outputs the count value CNT input from the counter 41d as the switching period Tsw in synchronization with the rising edge of the drive signal SG1.

Next, an example of the internal configuration of the pulse generator 30 will be described with reference to FIG.
The pulse generator 30 includes a buffer circuit 31, an RS-flip flop (RS-FF) circuit 32, a delay circuit 33, and a multiplexer 34.

  As shown in FIG. 3, the output signal S <b> 1 from the comparator 20 (see FIG. 1) is input to the set terminal S of the RS-FF circuit 32 via the buffer circuit 31. Specifically, when the output voltage Vo becomes lower than the first reference voltage Vr 1, the H-level output signal S 1 that is a set signal is input to the set terminal S of the RS-FF circuit 32 via the buffer circuit 31.

The output signal S1 is also input to the delay circuit 33. The delay circuit 33 includes a plurality of stages (here, n (= 2 ^N ) stages) of buffer circuits 33a connected in series. Each buffer circuit 33a has a predetermined delay time and functions as a delay element. The output signals of these buffer circuits 33a are input to the multiplexer 34, respectively.

  The multiplexer 34 receives the pulse width adjustment signal S3 (N-bit digital signal) output from the error amplifier 50 as a selection signal. The multiplexer 34 selects an output signal of any one of the plurality of buffer circuits 33a based on the pulse width adjustment signal S3, and uses the selected output signal as a delay signal S1L as an RS-FF circuit 32. Is output to the reset terminal R. The delay circuit 33 and the multiplexer 34 output an output signal S1 to the RS-FF circuit 32 through the buffer circuits 33a corresponding to the number of stages corresponding to the pulse width adjustment signal S3 among the plurality of buffer circuits 33a. As a result, the output signal S1 is delayed by a desired time and output to the reset terminal R of the RS-FF circuit 32. Specifically, after the delay time corresponding to the pulse width adjustment signal S3 has elapsed since the H level output signal S1 was input to the delay circuit 33, the H level delay signal S1L, which is a reset signal, is converted into the RS-FF circuit 32. To the reset terminal R.

  The RS-FF circuit 32 transitions to a set state in response to an H level output signal S1 (set signal) input to the set terminal S via the buffer circuit 31, and outputs an H level drive signal SG1. The RS-FF circuit 32 transitions to a reset state in response to an H level delay signal S1L (reset signal) input to the reset terminal R, and outputs an L level drive signal SG1. That is, the RS-FF circuit 32 starts driving the H level drive signal SG1, and then drives the H level until the H level delay signal S1L is input after the delay time selected by the delay circuit 33 and the multiplexer 34. Continue to output the signal SG1. In other words, the timing at which the drive signal SG1 falls to the L level is controlled by the delay time selected by the delay circuit 33 and the multiplexer 34, that is, the on-pulse width is adjusted.

  Next, the operation of the DC-DC converter 1a configured as described above will be described with reference to FIG. In FIG. 4, the horizontal axis and the vertical axis are enlarged or reduced as appropriate for the sake of simplicity of explanation.

  Now, the switching cycle Tsw1 from time t1 to t2 (see switching cycle Tsw at time t2) is shorter than the reference cycle Tr. At this time, the pulse width adjustment signal S3 generated based on the period difference signal S2 having a positive value is input to the multiplexer 34 of the pulse generator 30 at time t2. Then, in the multiplexer 34, the output signal of the buffer circuit 33a in the delay circuit 33 is selected so that the delay time becomes longer than the delay time Td1 in the previous switching cycle Tsw1. That is, in the switching period Tsw2 from time t2 to time t3, the output voltage Vo is lower than the first reference voltage Vr1 and the H level output signal S1 is output, and then delayed by the delay time Td2 (> Td1). An H level delay signal S1L (reset signal) is output. As a result, the reset timing of the RS-FF circuit 32 is delayed, and the on-pulse width is adjusted to be longer. Here, if the input voltage Vin, the output voltage Vo, and the output current Io are constant as in the steady state, the switching cycle Tsw changes in proportion to the on-pulse width. For this reason, when the on-pulse width is adjusted to be longer, the switching cycle Tsw2 from time t2 to time t3 becomes longer than the previous switching cycle Tsw1.

  Subsequently, in the frequency detector 41, the switching period Tsw2 is detected by counting the number of reference clock signals CK input from time t2 to time t3, and the switching period Tsw2 becomes longer than the reference period Tr. At this time, the pulse width adjustment signal S3 generated based on the period difference signal S2 having a negative value is input to the multiplexer 34 of the pulse generator 30 at time t3. Then, in the multiplexer 34, the output signal of the buffer circuit 33a in the delay circuit 33 is selected so that the delay time is shorter than the delay time Td2 in the previous switching cycle Tsw2. That is, in the switching cycle Tsw3 from time t3 to time t4, after the H level output signal S1 is output, the delay time Td3 (<Td2) is delayed and the H level delay signal S1L (reset signal) is output. . As a result, the reset timing of the RS-FF circuit 32 is advanced, so that the on-pulse width is adjusted to be shorter. Accordingly, the switching cycle Tsw3 from time t3 to t4 becomes shorter than the previous switching cycle Tsw2.

By repeating such an operation, the switching cycle Tsw (switching frequency) is maintained at a desired reference cycle Tr (desired frequency).
Next, the operation when the load changes suddenly will be described with reference to the simulation results of FIGS. In these simulations, an appropriate minimum off-time limit is set.

First, the operation when the load increases rapidly will be described with reference to FIG.
At time t5, when the load suddenly increases and the output current Io suddenly increases from 0.5A to 1A, the output voltage Vo decreases rapidly, and the output voltage Vo becomes a value extremely lower than the first reference voltage Vr1. Become. Then, the switching of the output transistor T1 is repeated by the on-time and the minimum off-time according to the switching cycle Tsw when the output current Io is 0.5 A in a steady state (period before time t10). For this reason, after the output current Io rapidly increases, the switching cycle Tsw is rapidly shortened (time t5 to t6). With the sudden change of the switching period Tsw, the pulse width adjustment signal S3 generated based on the period difference (Tr−Tsw) increases rapidly. Then, in accordance with the pulse width adjustment signal S3, the pulse generator 30 adjusts the on-pulse width so as to be significantly increased. As a result, the switching cycle Tsw is converged to a desired reference cycle Tr as after time t6.

  Note that the value of the pulse width adjustment signal S3 in the steady state between the output current Io of 0.5A and 1A is different because of the conduction loss of the output transistor T1 and the choke coil L1 with the change of the output current Io. This is because the switching duty changes.

Next, the operation when the load is suddenly reduced will be described with reference to FIG.
At time t7, when the load suddenly decreases and the output current Io rapidly decreases from 1A to 0.5A, the output voltage Vo increases rapidly, and the output voltage Vo becomes a value extremely higher than the first reference voltage Vr1. Become. Then, the off period of the output transistor T1 continues until time t8 when the output voltage Vo becomes lower than the first reference voltage Vr1. For this reason, the switching cycle Tsw at that time becomes abnormally long. With the sudden change of the switching period Tsw, the pulse width adjustment signal S3 generated based on the period difference (Tr−Tsw) rapidly decreases. Then, in accordance with the pulse width adjustment signal S3, the pulse generator 30 adjusts the on-pulse width to be significantly shortened. As a result, the switching cycle Tsw is converged to a desired reference cycle Tr.

  As described above, according to the DC-DC converter 1a, the switching cycle Tsw in the steady state can be maintained at the desired reference cycle Tr even if the output current Io varies due to a load variation or the like.

According to this embodiment described above, the following effects can be obtained.
(1) In the pulse generator 30, the on-pulse width is adjusted based on the period difference (Tr−Tsw) between the switching period Tsw and the reference period Tr. For example, when the switching cycle Tsw is shorter than the reference cycle Tr, the on-pulse width is adjusted to be longer. Here, in a steady state, the switching period Tsw changes in proportion to the on-pulse width. For this reason, when the on-pulse width is increased, the switching cycle Tsw is increased. Thereby, the switching cycle Tsw (switching frequency) in the steady state can be maintained at the reference cycle Tr (desired frequency).

  Further, as apparent from the simulation results of FIGS. 5 and 6, even when the output current Io fluctuates due to the fluctuation of the load, the switching period Tsw in the steady state before and after the fluctuation can be maintained at the reference period Tr. it can. Even when the input voltage Vin and the output voltage Vo change, similarly, the switching cycle Tsw in the steady state before and after the change can be maintained at the reference cycle Tr.

  (2) The on-pulse width is adjusted according to one parameter called the switching period Tsw. For this reason, for example, compared with the case where the on-pulse width is adjusted according to two parameters such as the switching cycle Tsw and the phase, it is possible to adjust the on-pulse width so as to maintain the switching cycle Tsw at the reference cycle Tr with a simple control configuration. And has excellent controllability.

  (3) A so-called comparator method is employed in which the output voltage Vo and the first reference voltage Vr1 are directly compared by the comparator 20, and the output transistor T1 is immediately turned on / off according to the comparison result. For this reason, a high-speed response to a sudden load change is possible.

  (4) Direction in which the switching cycle Tsw varies due to the detection timing of the comparator 20 due to load variation, and direction of variation in the switching cycle Tsw due to the error amplifier 50 changing the pulse width adjustment signal S3 due to the variation. Are in the same direction. On the other hand, in the present embodiment, the frequency difference detector 40, the error amplifier 50, and the pulse generator 30 are included as compared with the band of the first control loop including the comparator 20, the pulse generator 30, and the converter unit. Since the bandwidth of the second control loop is set to be sufficiently narrow, the influence of the fluctuation is reduced.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to FIGS. The DC-DC converter 1b of this embodiment is different from the first embodiment in that a D / A converter 55 is added and the internal configuration of the pulse generator. Hereinafter, the difference from the first embodiment will be mainly described.

  As shown in FIG. 7, the pulse width adjustment signal S3 is input from the error amplifier 50 to the D / A converter 55 in the control circuit 10b. The D / A converter 55 performs D / A conversion on the pulse width adjustment signal S3 (digital signal) and outputs a pulse width adjustment voltage S4 (analog amplification signal), which is an analog signal, to the pulse generator 60.

  The pulse generator 60 adjusts the pulse width of the on-pulse (H level drive signal SG1) according to the pulse width adjustment voltage S4 from the D / A converter 55. Then, in response to the H level output signal S1, the pulse generator 60 outputs an ON pulse having the adjusted pulse width to the output transistor T1 and the frequency difference detector 40. The pulse generator 60 is an analog mono-multi circuit that varies the on-pulse width according to an analog signal.

Next, an example of the internal configuration of the pulse generator 60 will be described with reference to FIG.
As shown in FIG. 8, the pulse generator 60 includes an RS-FF circuit 61, an N-channel MOS transistor T2, a constant current source 62 and a capacitor C2 connected in series between a high potential power supply and the ground, And a comparator 63. An output signal S1 output from the comparator 20 (see FIG. 7) is input to the set terminal S of the RS-FF circuit 61. Further, the output signal of the comparator 63 is input to the reset terminal R of the RS-FF circuit 61. A signal output from the output terminal Q of the RS-FF circuit 61 is supplied as a drive signal SG1 to the output transistor T1 and the frequency difference detector 40, and a signal output from the inverting output terminal XQ is supplied to the gate of the transistor T2. The

  The transistor T2 has a source connected to the ground and a drain connected to a node N1 between the constant current source 62 and the capacitor C2. The drain (node N1) of the transistor T2 is connected to the non-inverting input terminal of the comparator 63. The pulse width adjustment voltage S4 from the D / A converter 55 is input to the inverting input terminal of the comparator 63. The output signal of the comparator 63 is input to the reset terminal R of the RS-FF circuit 61.

  In the pulse generator 60 configured in this way, the output voltage Vo is lower than the first reference voltage Vr1, and the H-level output signal S1 (set signal) is output from the comparator 20 to the set terminal S of the RS-FF circuit 61. Is input to the RS-FF circuit 61, the state transits to the set state. Then, an H level drive signal SG1 is output from the output terminal Q, and an L level output signal is output from the inverted output terminal XQ. Since the transistor T2 is turned off according to the L level output signal, the capacitor C2 is charged by the ds current supplied from the constant current source 62. As a result, the potential of the node N1 gradually increases. At this time, when the potential of the node N1 becomes higher than the pulse width adjustment voltage S4, an H level output signal (reset signal) is output from the comparator 63 to the reset terminal R of the RS-FF circuit 61. The RS-FF circuit 61 transitions to a reset state in response to the reset signal, and outputs an L level drive signal SG1 and an H level output signal from the inverted output terminal XQ. The transistor T2 is turned on according to the H level output signal, whereby the charging voltage of the capacitor C2 is discharged. The transistor T2, the constant current source 62, the capacitor C2, and the comparator 63 function as a reset timing adjustment circuit.

  As described above, the pulse generator 60 can control the timing (reset timing) at which the reset signal is output from the comparator 63 by adjusting the voltage value of the pulse width adjustment voltage S4. Can be adjusted. Specifically, when the switching cycle Tsw is shorter than the reference cycle Tr, the voltage value of the pulse width adjustment voltage S4 is increased, so that the time until the potential of the node N1 reaches the pulse width adjustment voltage S4 is increased. Extends the reset timing. This increases the on-pulse width and the switching cycle Tsw. On the other hand, when the switching period Tsw is longer than the reference period Tr, the voltage value of the pulse width adjustment voltage S4 is decreased, and thus the time until the potential of the node N1 reaches the voltage value of the pulse width adjustment voltage S4. This shortens the reset timing. As a result, the on-pulse width is shortened and the switching cycle Tsw is shortened.

According to this embodiment described above, the same effects as those of the first embodiment can be obtained.
(Third embodiment)
Hereinafter, a third embodiment will be described with reference to FIG. The DC-DC converter 1c of this embodiment is different from the second embodiment in that a frequency detector 71, a D / A converter 72, and an integrator 73 are provided. Hereinafter, the difference from the second embodiment will be mainly described.

  As shown in FIG. 9, the frequency detector 71 in the control circuit 10c sets the switching cycle Tsw of the output transistor T1 based on the drive signal SG1 from the pulse generator 60 and the reference clock signal CK from the oscillator 43. To detect. The frequency detector 71 has the same configuration as the frequency detector 41 of the first and second embodiments.

  The switching period Tsw detected by the frequency detector 71 is input to the D / A converter 72. The D / A converter 72 D / A converts the switching period Tsw (digital signal), generates an analog voltage signal, and outputs the analog voltage signal to the integrator 73.

  Integrator 73 includes an error amplifier 74, a resistor R1, and a capacitor C3. The analog voltage signal generated by the D / A converter 72 is input to the inverting input terminal of the error amplifier 74 as the voltage Va via the resistor R1. The second reference voltage Vr2 is input to the non-inverting input terminal of the error amplifier 74. The second reference voltage Vr2 is an analog voltage generated by the second reference power source e2, and is generated according to the reference cycle Tr. For example, the second reference voltage Vr2 is generated by D / A converting the reference period Tr (M-bit digital signal).

  The error amplifier 74 compares the voltage Va and the second reference voltage Vr2, and outputs a signal obtained by amplifying the difference voltage between the two voltages to the pulse generator 60 as a pulse width adjustment voltage S5 (analog amplified signal). The pulse width adjustment voltage S5 generated by the error amplifier 74 is fed back to the inverting input terminal of the error amplifier 74 as a voltage Va through the capacitor C3.

  In response to the H level output signal S1, the pulse generator 60 generates an ON pulse (H level drive signal SG1) having a pulse width corresponding to the pulse width adjustment voltage S5 from the error amplifier 74. The pulse generator 60 has substantially the same configuration as that of the second embodiment (see FIG. 8). In the pulse generator 60 of the present embodiment, the pulse width adjustment voltage S5 from the error amplifier 74 is input to the inverting input terminal of the comparator 63 shown in FIG. 8 instead of the pulse width adjustment voltage S4.

According to this embodiment described above, the same effects as those of the first embodiment can be obtained.
(Fourth embodiment)
Hereinafter, a fourth embodiment will be described with reference to FIGS. The same members as those shown in FIGS. 1 to 9 are denoted by the same reference numerals, and detailed description of these elements is omitted.

  A DC-DC converter 2a shown in FIG. 10 is a hysteresis comparator type DC-DC converter. The DC-DC converter 2a includes a DC-DC converter control circuit (control circuit) 11a and a converter unit. The configuration of the converter unit is the same as that of the DC-DC converter 1a shown in FIG.

  A drive signal SG2 output from the control circuit 11a is supplied to the gate of the output transistor T1. The output transistor T1 is on / off controlled based on the drive signal SG2, whereby the input voltage Vin is stepped down and output as an output voltage Vo to a load (not shown) connected to the output terminal To.

  The control circuit 11a includes a hysteresis comparator 80, a frequency difference detector 40a, an error amplifier 50a, and a D / A converter 55a. The frequency difference detector 40a, the error amplifier 50a, and the D / A converter 55a have substantially the same configuration as the frequency difference detector 40, the error amplifier 50, and the D / A converter 55a of the second embodiment, respectively. .

  In the hysteresis comparator 80, the output voltage (feedback signal) is input to the inverting input terminal, and the first reference voltage Vr1 is input to the non-inverting input terminal. In the hysteresis comparator 80, a lower limit reference voltage VL and an upper limit reference voltage VU (see FIG. 11) based on the first reference voltage Vr1 are set. The lower limit reference voltage VL (first threshold value) is a voltage for setting the on timing of the output transistor T1, and the upper limit reference voltage VU (second threshold value) is a voltage for setting the off timing of the output transistor T1.

  The hysteresis comparator 80 compares the output voltage Vo with the lower limit reference voltage VL and the upper limit reference voltage VU, generates a drive signal SG2 having a level corresponding to the comparison result, and outputs the drive signal SG2 to the output transistor T1 and the frequency difference. Output to the detector 40. Specifically, when the output voltage Vo becomes lower than the lower limit reference voltage VL, the hysteresis comparator 80 generates an H-level drive signal SG2 and turns on the output transistor T1. Further, when the output voltage Vo becomes higher than the upper limit reference voltage, the hysteresis comparator 80 generates an L level drive signal SG2 and turns off the output transistor T1.

  In the first control loop including the hysteresis comparator 80 and the converter unit, the output voltage Vo is controlled to be maintained at the target voltage based on the first reference voltage Vr1. That is, in the first control loop, when the output voltage Vo becomes higher than the upper limit reference voltage VU and the output transistor T1 is turned off, the energy stored in the choke coil L1 is released when the output transistor T1 is turned on. . When the energy stored in the choke coil L1 decreases and the output voltage Vo decreases and the output voltage Vo becomes lower than the lower limit reference voltage VL, the drive signal SG1 becomes H level and the output transistor T1 is turned on again. Thereafter, such an operation is repeated, and the output voltage Vo is maintained at the target voltage based on the first reference voltage Vr1.

  The frequency difference detector 40a includes a frequency detector 41 and an arithmetic unit 42. Based on the drive signal SG2, the reference clock signal CK, and the reference period Tr, the frequency difference (Tr−) between the switching period Tsw and the reference period Tr. Tsw) is detected. The frequency difference detector 40a outputs a period difference signal S2 indicating the detected period difference (Tr−Tsw) to the error amplifier 50a.

  The error amplifier 50a amplifies the period difference (Tr−Tsw) and outputs the amplified signal S3a to the D / A converter 55. The D / A converter 55 performs D / A conversion on the amplified signal S3a (M-bit digital signal), and outputs a hysteresis width adjustment signal S4a, which is an analog signal, to the hysteresis comparator 80.

The hysteresis comparator 80 adjusts the voltage values of the lower limit reference voltage VL and the upper limit reference voltage VU, that is, the hysteresis width, according to the hysteresis width adjustment signal S4a.
In the second control loop including the hysteresis comparator 80, the frequency difference detector 40a, the error amplifier 50a, and the D / A converter 55a, the switching period Tsw is maintained at the reference period Tr by adjusting the hysteresis width. To be controlled. For example, when the switching period Tsw is shorter than the reference period Tr, the period difference signal S2 has a positive value, and thus a hysteresis width adjustment signal S4a for increasing the hysteresis width of the hysteresis comparator 80 is generated. Thereby, the hysteresis comparator 80 is adjusted so that the hysteresis width is widened. Here, if the input voltage Vin, the output voltage Vo, and the output current Io are constant as in the steady state, the switching cycle Tsw changes in proportion to the hysteresis width. For this reason, the switching period Tsw becomes long by adjusting the hysteresis width widely.

  In the present embodiment, the first comparator including the hysteresis comparator 80, the frequency difference detector 40a, the error amplifier 50a, and the D / A converter 55a is compared with the band of the first control loop including the hysteresis comparator 80 and the converter unit. 2 The bandwidth of the control loop is set to be sufficiently narrow.

Next, an example of the internal configuration of the hysteresis comparator 80 will be described with reference to FIG.
As shown in FIG. 11, the hysteresis comparator 80 includes a comparator 81, a hysteresis width adjustment circuit 82, a resistor R1, and an inverter circuit INV1. The output voltage Vo is input to the inverting input terminal of the comparator 81. The first reference voltage Vr1 is input to the non-inverting input terminal of the comparator 81 via the resistor R11, and the hysteresis width setting signal S6 is input from the hysteresis width adjustment circuit 82. The comparator 81 outputs a comparison result between the reference voltage (the lower limit reference voltage VL and the upper limit reference voltage VU) corresponding to the first reference voltage Vr1 and the hysteresis width setting signal S6 and the output voltage Vo as the drive signal SG2. The output terminal of the comparator 81 is connected to the hysteresis width adjustment circuit 82 via the inverter circuit INV1.

  Hysteresis width adjustment circuit 82 includes an N-channel MOS transistor TN1, a resistor R12, current mirror circuits 83 to 85, and a CMOS inverter circuit 86. The hysteresis width adjustment signal S4a from the D / A converter 55 is supplied to the gate of the N-channel MOS transistor TN1. The source of the transistor TN1 is connected to the ground via the resistor R12, and the drain of the transistor TN1 is connected to the drains of the P-channel MOS transistors TP1 of the current mirror circuits 83 and 84. The transistor TN1 is ON / OFF controlled by a hysteresis width adjustment signal S4a, and a current I1 proportional to the hysteresis width adjustment signal S4a flows through the transistor TN1.

  Transistor TP1 is current mirror connected to P-channel MOS transistor TP2. That is, the drain of the input side transistor TP1 is connected to the gates of both transistors TP1 and TP2. The sources of both transistors TP1 and TP2 are connected to the high potential side power supply, and the drain of the output side transistor TP2 is connected to the drain of the N-channel MOS transistor TN2 of the current mirror circuit 85. The output side transistor TP2 has the same electrical characteristics as the input side transistor TP1. Therefore, the current I1 flowing through the input side transistor TP1 flows through the output side transistor TP2.

  The transistor TN2 is current mirror connected to the N-channel MOS transistor TN3. The drain of the output side transistor TN3 is connected to the source of the N channel MOS transistor TN4 in the CMOS inverter circuit 86. The output side transistor TN3 has the same electrical characteristics as the input side transistor TN2. Accordingly, the current I1 flowing through the input side transistor TN2 flows through the output side transistor TN3. Specifically, the output side transistor TN3 sucks the current I1 from the transistor TN4.

  The transistor TP1 is current mirror connected to the P-channel MOS transistor TP3. The drain of the output side transistor TP3 is connected to the source of the P channel MOS transistor TP4 in the CMOS inverter circuit 86. The output side transistor TP3 has the same electrical characteristics as the electrical characteristics of the input side transistor TP1. Therefore, the current I1 flowing through the input side transistor TP1 flows through the output side transistor TP3. Specifically, the output side transistor TP3 discharges the current I1 to the transistor TP4.

  The drive signal SG2 output from the comparator 81 is supplied to the gates of the transistors TP4 and TN4 in the CMOS inverter circuit 86 via the inverter circuit INV1. A node N2 between the transistors TP4 and TN4 is connected to the non-inverting input terminal of the comparator 81.

  In the hysteresis comparator 80 configured as described above, the transistors TP4 and TN4 of the CMOS inverter circuit 86 are turned on / off according to the drive signal SG2 output from the comparator 81. For example, when an H level drive signal SG2 is output from the comparator 81, an L level signal is output from the inverter circuit INV1, so that the transistor TP4 is turned on and the transistor TN4 is turned off. Then, the current I1 proportional to the hysteresis width adjustment signal S4a is discharged to the node N2 through the transistor TP4 by the current mirror operation by the current mirror circuit 84. A voltage that is higher than the first reference voltage Vr1 by a voltage corresponding to the current amount of the discharged current I1 is input to the non-inverting input terminal of the comparator 81 as the upper limit reference voltage VU.

  On the other hand, when the L-level drive signal SG2 is output from the comparator 81, an H-level signal is output from the inverter circuit INV1, so that the transistor TN4 is turned on and the transistor TP4 is turned off. Then, the current I1 proportional to the hysteresis width adjustment signal S4a is sucked into the transistor TN3 from the node N2 through the transistor TN4 by the current mirror operation by the current mirror circuits 83 and 85. A voltage that is lower than the first reference voltage Vr1 by a voltage corresponding to the amount of current I1 that is sucked is input to the non-inverting input terminal of the comparator 81 as the lower limit reference voltage VL.

  Here, when the switching cycle Tsw is shorter than the reference cycle Tr as in the switching cycle Tsw1 from time t11 to t12 shown in FIG. 12, the hysteresis width output from the D / A converter 55a at time t12. The voltage value of the adjustment signal S4a increases. Along with this, the amount of current I1 increases. For this reason, in the switching cycle Tsw2 from time t12 to t13, the voltage value of the upper limit reference voltage VU is increased and the voltage value of the lower limit reference voltage VL is decreased compared to the previous switching cycle Tsw1. That is, the hysteresis width in the switching cycle Tsw2 is adjusted to be wider than that in the previous switching cycle Tsw1. As a result, the switching cycle Tsw2 becomes longer than the previous switching cycle Tsw1.

  On the other hand, when the switching cycle Tsw is longer than the reference cycle Tr as in the switching cycle Tsw2, the voltage value of the hysteresis width adjustment signal S4a output from the D / A converter 55a decreases at time t13. Along with this, the amount of current I1 decreases. For this reason, in the switching cycle Tsw3 from time t13 to t14, the voltage value of the upper limit reference voltage VU is lowered and the voltage value of the lower limit reference voltage VL is increased compared to the previous switching cycle Tsw2. That is, the hysteresis width in the switching cycle Tsw3 is adjusted to be narrower than that of the previous switching cycle Tsw2. Thereby, the switching cycle Tsw3 becomes shorter than the previous switching cycle Tsw2.

By repeating such an operation, the switching cycle Tsw in the steady state is maintained at a desired reference cycle Tr.
According to this embodiment described above, the same effects as those of the first embodiment can be obtained.

(Fifth embodiment)
Hereinafter, a fifth embodiment will be described with reference to FIG. The DC-DC converter 2b of this embodiment is different from the fourth embodiment in that it includes a frequency detector 71, a D / A converter 72, and an integrator 73a. Hereinafter, the difference from the fourth embodiment will be mainly described.

  As shown in FIG. 9, the frequency detector 71 in the control circuit 11b sets the switching cycle Tsw of the output transistor T1 based on the drive signal SG1 from the pulse generator 60 and the reference clock signal CK from the oscillator 43. To detect. The D / A converter 72 performs D / A conversion on the switching period Tsw (digital signal) detected by the frequency detector 71 to generate an analog voltage signal and output the analog voltage signal to the integrator 73a.

  Integrator 73a includes error amplifier 74a, resistor R1, and capacitor C3. The analog voltage signal generated by the D / A converter 72 is input to the inverting input terminal of the error amplifier 74a as the voltage Va via the resistor R1. The second reference voltage Vr2 is input to the non-inverting input terminal of the error amplifier 74. The error amplifier 74a compares the voltage Va with the second reference voltage Vr2, and outputs a hysteresis width adjustment signal S5a obtained by amplifying the difference voltage between the two voltages to the pulse generator 60.

  The hysteresis comparator 80 adjusts the hysteresis width according to the hysteresis width adjustment signal S5a from the error amplifier 74a. The hysteresis comparator 80 has the same configuration as that of the fourth embodiment (see FIG. 11). In the hysteresis comparator 80 of this embodiment, the hysteresis width adjustment signal S5a from the error amplifier 74a is input to the gate of the transistor TN1 shown in FIG. 11 instead of the hysteresis width adjustment signal S4a.

According to this embodiment described above, the same effects as those of the first embodiment can be obtained.
(Other embodiments)
In addition, each said embodiment can also be implemented in the following aspects which changed this suitably.

  -If the frequency detectors 41 and 71 in the said embodiment are the structures which detect the switching period Tsw of the output transistor T1, the internal structure will not be restrict | limited in particular. For example, the frequency detectors 41 and 71 may have the configuration shown in FIG. In FIG. 14, the frequency detector 71 in the third embodiment will be described as an example.

  That is, as shown in FIG. 14, the frequency detector 71 includes two D-FF circuits 71a and 71b, an AND circuit 71c, a shift register 71d, a register circuit 71e, and an encoder 71f. The D-FF circuits 71a and 71b and the AND circuit 71c output an H level signal to the shift register 71d and the register circuit 71e when the rising edge of the drive signal SG1 is detected in synchronization with the rising of the reference clock signal CK. .

  The shift register 71d includes a plurality of stages (here, k stages) of D-FF circuits A1 to Ak connected in series. The reference clock signal CK is input to the clock terminals of these D-FF circuits A1 to Ak. In the first-stage D-FF circuit A1, the output terminal of the AND circuit 71c is connected to the input terminal D, and the output terminal Q is connected to the input terminal D of the next-stage D-FF circuit A2. Similarly, the output terminals Q of the second and subsequent stages of D-FF circuits A2 to Ak-1 are respectively connected to the input terminals D of the D-FF circuits A3 to Ak of the next stage. Therefore, the shift register 71d latches the signal input from the AND circuit 71c and sequentially transfers it to the D-FF circuits A2 to Ak at the next stage every time the reference clock signal CK rises.

  The register circuit 71e includes a plurality of (here, k stages) D-FF circuits B1 to Bk connected in series. The output signal of the AND circuit 71c is input to the clock terminals of the D-FF circuits B1 to Bk as a clock signal. The output terminals Q of the D-FF circuits A1 to Ak are connected to the input terminals D of the D-FF circuits B1 to Bk, respectively. Moreover, the output terminal Q of each D-FF circuit B1-Bk is connected to the encoder 71f. Each of the D-FF circuits B1 to Bk outputs a signal having the level of the input terminal D from the output terminal Q in synchronization with the rise of the output signal of the AND circuit 71c. Specifically, among the k-stage D-FF circuits B1 to Bk, the time until the next H level signal is output from the AND circuit 71c (the number of reference clock signals CK). 1 D-FF circuit corresponding to the output terminal Q outputs an H level signal from the output terminal Q in synchronization with the rise of the output signal of the AND circuit 71c. The other D-FF circuits output an L level signal from the output terminal Q in synchronization with the rise of the output signal of the AND circuit 71c.

  The encoder 71f generates a switching period Tsw that is an M-bit digital signal based on the output signals of the D-FF circuits B1 to Bk in the register circuit 71e. Thus, even the frequency detector 71 shown in FIG. 14 can detect the switching cycle Tsw of the output transistor T1.

Note that each of the D-FF circuits A1 to Ak of the shift register 71d in FIG. 14 may be replaced with a resistance element as a delay line.
In the frequency detector 71 shown in FIGS. 4 and 14, the switching period Tsw is detected by detecting the time from the rising edge of the drive signal SG1 to the next rising edge. However, the switching period Tsw may be detected by detecting the time from the falling edge of the drive signal SG1 to the next falling edge.

  In the first to third embodiments, the switching period Tsw is controlled to be maintained at a desired reference period Tr by adjusting the pulse width of the on pulse. However, the present invention is not limited to this, and the switching cycle Tsw may be controlled to be maintained at a desired reference cycle Tr by adjusting the pulse width of the off pulse. For example, the DC-DC converter 1a of the first embodiment may be changed to a DC-DC converter 1d shown in FIG.

  In the comparator 20a of the control circuit 10d shown in FIG. 15, the output voltage Vo is input to the non-inverting input terminal, and the first reference voltage Vr1 is input to the non-inverting input terminal. The comparator 20a generates an L level output signal S1a when the output voltage Vo is lower than the first reference voltage Vr1, and when the output voltage Vo becomes higher than the first reference voltage Vr1, the comparator 20a outputs an H level output signal S1a ( Set signal).

  The output signal S1a of the comparator 20a is input to the set terminal of the pulse generator 30. When the H level output signal S1 is input to the set terminal, the pulse generator 30 enters a set state and outputs an H level signal from the output terminal Q to the inverter circuit 35 for a predetermined time. As a result, the L-level drive signal SG1 is output from the inverter circuit 35 for a predetermined time, and the output transistor T1 is turned off for the predetermined time. When a predetermined time corresponding to the pulse width adjustment signal S3 from the error amplifier 50 has elapsed, the pulse generator 30 returns to the reset state and outputs an L level signal from the output terminal Q. As a result, an H level drive signal SG1 is output from the inverter circuit, and the output transistor T1 is turned on. That is, the pulse generator 30 and the inverter circuit 35 output an off pulse having a predetermined pulse width to the output transistor T1 based on the H level output signal S1a. The off pulse width is adjusted according to the pulse width adjustment signal S3 from the error amplifier 50.

Even with such a configuration, the same effects as those of the first embodiment can be obtained.
In the first, second, and fourth embodiments, the computing unit 42 subtracts the switching period Tsw from the reference period Tr to generate the period difference signal S2, but the reference period Tr is calculated from the switching period Tsw. The period difference signal S2 may be generated by subtraction.

  The pulse generator 30 in the first embodiment is not particularly limited in its internal configuration as long as it generates an on-pulse having a pulse width corresponding to the pulse width adjustment signal S3 in response to the output signal S1.

  If the pulse generator 60 in the second and third embodiments is configured to generate an on-pulse having a pulse width corresponding to the pulse width adjustment voltages S4 and S5 in response to the output signal S1, its internal configuration is There is no particular limitation.

  The hysteresis comparator 80 in the fourth and fifth embodiments is not particularly limited in its internal configuration as long as the hysteresis width is variable according to the input hysteresis width adjustment signals S4a and S5a.

-You may make it include the output transistor T1 in each said embodiment in each control circuit 10a-10d, 11a, 11b.
In the above-described embodiments, the comparator 20 and the hysteresis comparator 80 compare the output voltage Vo and the first reference voltage Vr1 as a feedback signal. For example, the comparator 20 and the hysteresis comparator 80 may compare the divided voltage obtained by dividing the output voltage Vo as a feedback signal with the first reference voltage Vr1. In this case, the first reference voltage Vr1 is set to coincide with the divided voltage when the output voltage Vo reaches the standard value.

  In each of the above embodiments, the output transistor T1 is configured by an N-channel MOS transistor, but is not particularly limited as long as it is a switching element. For example, the output transistor T1 may be configured by a P-channel MOS transistor or a bipolar transistor.

  In each of the above embodiments, the step-down DC-DC converter that generates the output voltage Vo obtained by stepping down the input voltage Vin is embodied. However, the step-up DC-DC that generates the output voltage Vo obtained by stepping up the input voltage Vin. It may be embodied in a converter.

In each of the above embodiments, the asynchronous rectification type DC-DC converter is embodied, but the synchronous rectification type DC-DC converter may be embodied.
In each of the above embodiments, the voltage control mode DC-DC converter is embodied. However, the current control mode DC-DC converter may be embodied.

The various embodiments described above can be summarized as follows.
(Appendix 1)
A pulse generator that generates an on-pulse or an off-pulse according to the output voltage or output current;
A switching frequency of a switching element that is on / off controlled by the on-pulse or the off-pulse, and a frequency difference detector that detects a frequency difference from a reference frequency,
The power supply voltage control circuit, wherein the pulse generator adjusts a pulse width of the on-pulse or the off-pulse according to the frequency difference detected by the frequency difference detector.
(Appendix 2)
A digital error amplifier that amplifies the frequency difference detected by the frequency difference detector and generates a pulse width adjustment signal;
The power supply voltage control circuit according to appendix 1, wherein the pulse generator is a digital pulse generator that generates the on-pulse or the off-pulse having a pulse width corresponding to the pulse width adjustment signal.
(Appendix 3)
The pulse generator adjusts the pulse width of the on-pulse or the off-pulse so that the frequency of the switching frequency and the frequency of the reference frequency are close to each other according to the frequency difference. The power supply voltage control circuit described.
(Appendix 4)
A comparator that compares a feedback signal proportional to the output voltage with a reference voltage, detects a case where the feedback signal crosses the reference voltage, and generates a detection signal;
The pulse generator generates a delayed signal obtained by delaying the detection signal by a time corresponding to the pulse width adjustment signal, and transits to a set state according to the detection signal, The power supply voltage control circuit according to appendix 2, further comprising: a flip-flop circuit that transitions to a reset state in response.
(Appendix 5)
A digital error amplifier that amplifies the frequency difference detected by the frequency difference detector and generates a pulse width adjustment signal;
A digital / analog converter that converts the pulse width adjustment signal into an analog signal to generate an analog amplified signal;
The power supply voltage control circuit according to appendix 1, wherein the pulse generator is an analog pulse generator that generates the on-pulse or the off-pulse having a pulse width corresponding to the analog amplification signal.
(Appendix 6)
The frequency difference detector is
A frequency detector for detecting the switching frequency;
An arithmetic unit that calculates the frequency difference based on the switching frequency and the reference frequency;
The power supply voltage control circuit according to any one of appendices 2 to 5, further comprising:
(Appendix 7)
The frequency difference detector is
A frequency detector for detecting the switching frequency;
A digital / analog converter for converting the switching frequency into an analog signal;
An error amplifier that amplifies an error between the analog signal and the analog signal corresponding to the reference frequency to generate an analog amplified signal;
The power supply voltage control circuit according to appendix 1, wherein the pulse generator is an analog pulse generator that generates the on-pulse or the off-pulse having a pulse width corresponding to the analog amplification signal.
(Appendix 8)
A comparator that compares a feedback signal proportional to the output voltage with a reference voltage, detects a case where the feedback signal crosses the reference voltage, and generates a detection signal;
The pulse generator includes a reset timing adjustment circuit that generates a reset signal after a lapse of time according to the analog amplification signal from the generation of the detection signal, and transitions to a set state according to the detection signal, and And a flip-flop circuit that transitions to a reset state.
(Appendix 9)
The frequency detector counts the number of clocks between rising edges or falling edges of a signal output from the pulse generator, and detects a switching cycle of the switching element. The power supply voltage control circuit according to any one of the above.
(Appendix 10)
A hysteresis comparator having a first threshold value for setting the ON timing of the switching element and a second threshold value for setting the OFF timing of the switching element;
A frequency difference detector for detecting a frequency difference between a switching frequency of the switching element and a reference frequency,
The power supply voltage control circuit, wherein the hysteresis comparator varies the first threshold value and the second threshold value according to the frequency difference detected by the frequency difference detector.
(Appendix 11)
A digital error amplifier for generating an amplified signal obtained by amplifying the frequency difference detected by the frequency difference detector;
A digital / analog converter that converts the amplified signal into an analog signal to generate a hysteresis width adjustment signal;
11. The power supply voltage control circuit according to appendix 10, wherein the hysteresis comparator varies the first threshold and the second threshold according to the hysteresis width adjustment signal.
(Appendix 12)
The frequency difference detector is
A frequency detector for detecting the switching frequency;
A digital / analog converter for converting the switching frequency into an analog signal;
An error amplifier that amplifies an error between the analog signal and the analog signal according to the reference frequency to generate a hysteresis width adjustment signal, and
11. The power supply voltage control circuit according to appendix 10, wherein the hysteresis comparator varies the first threshold and the second threshold according to the hysteresis width adjustment signal.
(Appendix 13)
A frequency difference between a switching frequency of a switching element that is ON / OFF controlled by an ON pulse or an OFF pulse generated according to an output voltage or an output current and a reference frequency is detected, and the pulse width corresponding to the detected frequency difference is detected. A power supply voltage control method characterized by generating an on pulse or the off pulse.
(Appendix 14)
A pulse generator that generates an on-pulse or an off-pulse according to the output voltage or output current;
A control circuit including a switching frequency of a switching element that is on / off controlled by the on-pulse or the off-pulse and a frequency difference detector that detects a frequency difference from a reference frequency;
The DC-DC converter, wherein the pulse generator adjusts the pulse width of the on-pulse or the off-pulse according to the frequency difference detected by the frequency difference detector.

T1 output transistor (switching element)
1a-1d, 2a, 2b DC-DC converters 10a-10d, 11a, 11b Control circuit (power supply voltage control circuit)
20, 20a Comparator 30, 60 Pulse generator 32 RS-flip flop circuit 33 Delay circuit (pulse width adjustment circuit)
34 Multiplexer (Pulse width adjustment circuit)
40, 40a Frequency difference detector 41, 71 Frequency detector 42 Operation unit 50, 50a Error amplifier 55, 55a, 72 D / A converter (digital / analog converter)
61 RS-flip-flop circuit 62 Constant current source (reset timing adjustment circuit)
63 comparator (reset timing adjustment circuit)
74, 74a Error amplifier 80 Hysteresis comparator

Claims (8)

A pulse generator that generates an on-pulse or an off-pulse according to the output voltage or output current;
A switching frequency of a switching element that is on / off controlled by the on-pulse or the off-pulse, and a frequency difference detector that detects a frequency difference from a reference frequency,
The power supply voltage control circuit, wherein the pulse generator adjusts a pulse width of the on-pulse or the off-pulse according to the frequency difference detected by the frequency difference detector. A digital error amplifier that amplifies the frequency difference detected by the frequency difference detector and generates a pulse width adjustment signal;
The power supply voltage control circuit according to claim 1, wherein the pulse generator is a digital pulse generator that generates the on-pulse or the off-pulse having a pulse width corresponding to the pulse width adjustment signal.   The pulse generator adjusts the pulse width of the on-pulse or the off-pulse so that the frequency of the switching frequency approaches the frequency of the reference frequency according to the frequency difference. The power supply voltage control circuit described in 1. A comparator that compares a feedback signal proportional to the output voltage with a reference voltage, detects a case where the feedback signal crosses the reference voltage, and generates a detection signal;
The pulse generator generates a delayed signal obtained by delaying the detection signal by a time corresponding to the pulse width adjustment signal, and transits to a set state according to the detection signal, The power supply voltage control circuit according to claim 2, further comprising: a flip-flop circuit that transitions to a reset state in response. A digital error amplifier that amplifies the frequency difference detected by the frequency difference detector and generates a pulse width adjustment signal;
A digital / analog converter that converts the pulse width adjustment signal into an analog signal to generate an analog amplified signal;
The power supply voltage control circuit according to claim 1, wherein the pulse generator is an analog pulse generator that generates the on-pulse or the off-pulse having a pulse width corresponding to the analog amplification signal. A hysteresis comparator having a first threshold value for setting the ON timing of the switching element and a second threshold value for setting the OFF timing of the switching element;
A frequency difference detector for detecting a frequency difference between a switching frequency of the switching element and a reference frequency,
The power supply voltage control circuit, wherein the hysteresis comparator varies the first threshold value and the second threshold value according to the frequency difference detected by the frequency difference detector.   A frequency difference between a switching frequency of a switching element that is on / off controlled by an on pulse or an off pulse generated according to an output voltage or an output current and a reference frequency is detected, and the pulse width corresponding to the detected frequency difference is detected. A power supply voltage control method characterized by generating an on pulse or the off pulse. A pulse generator that generates an on-pulse or an off-pulse according to the output voltage or output current;
A control circuit including a switching frequency of a switching element that is on / off controlled by the on-pulse or the off-pulse and a frequency difference detector that detects a frequency difference from a reference frequency;
The DC-DC converter, wherein the pulse generator adjusts the pulse width of the on-pulse or the off-pulse according to the frequency difference detected by the frequency difference detector.

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