JP5855418B2 - Switching regulator - Google Patents

Description

  The present invention relates to a switching regulator for supplying a predetermined voltage to a load circuit. In particular, the present invention performs pulse frequency modulation (hereinafter referred to as PFM) control or pulse width modulation (hereinafter referred to as PWM) control in accordance with the load current flowing in the load circuit. The present invention relates to a non-insulated switching regulator that converts an input voltage into an output voltage and outputs the output voltage via an inductor.

  In recent years, there has been a demand for power savings in electronic devices. In such power savings, the power consumed by electronic devices is reduced and the efficiency of the power supply circuit itself that supplies voltage to the electronic devices is improved. The emphasis is on reducing wasteful power consumption. For this reason, as a power supply circuit for an electronic device, a switching regulator capable of supplying power by converting input power with high efficiency is widely used.

  As a control method of the switching regulator, PWM control and PFM control are widely known. Specifically, in the PFM control, when the output voltage decreases, the on time of the switch element is lengthened, and when the output voltage increases, control is performed to shorten the on time of the switch element. On the other hand, in the PWM control, the oscillation frequency of the drive pulse of the switch element is set to be constant, and the pulse width of the drive pulse (that is, the ON time of the switch element) is changed according to the load variation. There is also known a control method for performing PFM control in a pseudo manner by generating a control signal representing the on-timing of the switch element at a predetermined fixed frequency and skipping the on-timing according to the output voltage.

  For example, Patent Documents 1 to 5 describe circuit configurations for automatically switching between PWM control and PFM control. Specifically, Patent Documents 1 and 2 describe a PWM control operation based on an error amplification output voltage representing a difference between a divided voltage value of an output voltage of a switching regulator and a predetermined reference voltage from a reference voltage source. A circuit configuration that automatically switches the operation to the PFM control operation or from the PFM control operation to the PWM control operation is disclosed.

  Further, Patent Document 3 has a difference time generating means for forming a difference time signal representing a difference time corresponding to the difference between the pulse width of the PWM control signal and the pulse width of the PFM control signal, and based on the difference time signal. A circuit configuration is disclosed that performs control to switch the operation mode by comparison with a reference signal for forming a PWM control signal in accordance with the difference time.

  Further, Patent Document 4 is provided with a circuit that counts the number of pulses of the PWM control signal and the number of pulses of the PFM control signal, and from each PFM control to PWM control, and from PWM control to PFM control. A circuit configuration is disclosed in which a reference is set for the number of pulses for shifting the mode, and the operation mode is switched based on the pulse count result during PFM control or the pulse count result during PWM control.

  Further, Patent Document 5 detects the reverse current of the inductor current flowing from the output of the switching regulator to the output switch side, and controls from PFM control to PWM control or from PWM control to PFM control based on the detection signal. A circuit configuration for switching operation is disclosed.

  According to the circuit configurations described in Patent Documents 1 to 5, the circuit for setting the pulse width of the control signal for the switch element in PFM control and the circuit for setting the pulse width of the control signal for the switch element in PWM control are provided. There is a problem that current consumption cannot be reduced because it is always operated. Further, when the range of the input voltage and the output voltage becomes relatively wide, there is a problem that the load current at the timing of switching the control method between the PWM control and the PFM control is not easily changed to the target value and is unstable.

  Further, according to Patent Document 2, the load current for switching the operation mode is a critical current when shifting from the current discontinuous operation mode in which the inductor current is controlled not to flow backward from the inductor to the output switch side. Although the reference voltage of the level detection circuit of the error amplification output voltage is set so as to be a value, a specific configuration example is not disclosed.

  The object of the present invention is to solve the above problems, and even if the input voltage, the output voltage, and the load condition fluctuate greatly, the power conversion efficiency can be improved as compared with the prior art, and between PWM control and PFM control. It is an object of the present invention to provide a switching regulator that can be stabilized as compared with the prior art by setting a load current at a timing at which the control method is switched to a desired value and suppressing variations in the load current.

The switching regulator according to the present invention is a switching regulator that converts an input voltage input via an input terminal into a predetermined output voltage and outputs the voltage via an inductor.
An output switch element connected via a connection point between the input terminal and the inductor;
A rectifying element connected between the connection point and ground,
An error voltage generation circuit that generates an error voltage between a feedback voltage corresponding to the output voltage and a predetermined voltage corresponding to a predetermined set value of the output voltage;
A pulse skip reference voltage generation circuit for generating a predetermined pulse skip reference voltage based on the input voltage and the set value of the output voltage;
A first comparison circuit that compares the error voltage with the pulse skip reference voltage and outputs a pulse skip detection signal representing the comparison result;
One-pulse generation for generating a one-pulse signal having a predetermined pulse width based on the input voltage and the output voltage in response to the pulse skip detection signal indicating that the error voltage exceeds the pulse skip reference voltage Circuit,
An oscillation circuit that generates a sawtooth wave signal having a predetermined frequency, and a clock signal having the frequency and representing the detection timing of the pulse skip detection signal;
A second comparison circuit for comparing the error voltage with the sawtooth signal and outputting a pulse width modulation signal representing the comparison result;
Based on the pulse width modulation signal, the pulse skip detection signal, the one pulse signal, and the clock signal, the output switch element and the rectifier element are controlled to be turned on and off, respectively, and the second comparison circuit, A switching control circuit for controlling the one-pulse generation circuit and the oscillation circuit;
The pulse skip reference voltage is set to have a voltage between an upper limit value and a lower limit value of the sawtooth signal,
When the switching control circuit is controlling to operate the oscillation circuit and stop the operation of the one-pulse generation circuit,
(A) At the detection timing, when it is detected that the error voltage is higher than the pulse skip reference voltage based on the pulse skip detection signal, the second comparison circuit is controlled to operate, and the pulse width While performing a pulse width modulation control operation for on / off control of the output switch element and the rectifier element at the frequency according to a modulation signal,
(B) When it is detected at the detection timing that the error voltage is lower than the pulse skip reference voltage based on the pulse skip detection signal, the operations of the oscillation circuit and the second comparison circuit are stopped and The one pulse generation circuit is controlled to operate, and when it is detected that the error voltage exceeds the pulse skip reference voltage based on the pulse skip detection signal, the oscillation circuit is controlled to operate, and The output switch element is controlled to be turned on and the rectifier element is turned off in accordance with the one-pulse signal, and when the one-pulse signal generation by the one-pulse generation circuit is detected, the operation of the one-pulse generation circuit is stopped. It is characterized by performing a pulse frequency modulation control operation to control

According to the switching regulator according to the present invention, when the switching control circuit controls the oscillation circuit to operate and stops the operation of the one-pulse generation circuit,
(A) When it is detected that the error voltage is higher than the pulse skip reference voltage based on the pulse skip detection signal at the detection timing, the second comparison circuit is controlled to operate and is output at a frequency according to the pulse width modulation signal. While performing a pulse width modulation control operation to turn on and off the switch element and the rectifier element,
(B) When it is detected at the detection timing that the error voltage is lower than the pulse skip reference voltage based on the pulse skip detection signal, the operations of the oscillation circuit and the second comparison circuit are stopped and the one pulse generation circuit is operated. And controlling the oscillation circuit to operate when detecting that the error voltage exceeds the pulse skip reference voltage based on the pulse skip detection signal and turning on the output switch element according to the one pulse signal and the rectifier element When the generation of the one-pulse signal by the one-pulse generation circuit is detected, a pulse frequency modulation control operation is performed to control the operation of the one-pulse generation circuit.

  Therefore, even if the input voltage, the output voltage, and the load condition fluctuate greatly, the power conversion efficiency can be improved as compared with the prior art, and the load current at the timing of switching the control method between PWM control and PFM control is desired. It is possible to suppress the variation of the load current and to stabilize the value as compared with the prior art.

1 is a block diagram illustrating a configuration of a switching regulator 100 according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration of a level shift circuit 61 in FIG. 1. FIG. 2 is a circuit diagram showing a configuration of a pulse skip reference voltage generation circuit 4 in FIG. 1. 2 is a graph showing output voltage dependency of a relationship between an input voltage Vin and a duty ratio in a continuous current operation mode from the critical point of the switching regulator 100 of FIG. 1. It is a circuit diagram which shows the structure of the one pulse generation circuit 5 of FIG. FIG. 2 is a circuit diagram showing a configuration of a gate signal generation circuit 11 in FIG. 1. FIG. 2 is a state transition diagram illustrating an operation of the switching regulator 100 of FIG. 1. 2 is a timing chart showing the operation of the switching regulator 100 of FIG. It is a circuit diagram which shows the operation state in the 1st state of the switching regulator 100 of FIG. It is a circuit diagram which shows the operation state in the 2nd state of the switching regulator 100 of FIG. It is a circuit diagram which shows the operation state in the 3rd state of the switching regulator 100 of FIG. It is a circuit diagram which shows the operation state in the 4th state of the switching regulator 100 of FIG.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

  FIG. 1 is a block diagram showing a configuration of a switching regulator 100 according to an embodiment of the present invention. The switching regulator 100 according to the present embodiment is a non-insulating switching regulator mounted on an electronic device such as a personal computer. The switching regulator 100 steps down an input voltage Vin to an output voltage Vout, for example, a CPU (Central To a load circuit 90 such as a Processing Unit). In FIG. 1, a switching regulator 100 includes a switching control circuit 10, an output switch element PDRV composed of a P-channel MOS field effect transistor (hereinafter referred to as a pMOS transistor), and an N-channel MOS field effect transistor (hereinafter referred to as an nMOS). A rectifying switch element NDRV (which is a rectifying element), an error voltage generation circuit 20, a pulse skip reference voltage generation circuit 4, a one-pulse generation circuit 5, an oscillation circuit 6, and a skip comparator 7 A PWM comparator 8, an inverter 9, a level shift circuit 61, an inductor L, a smoothing capacitor Cout, an input terminal TI, and an output terminal OUT. The error voltage generation circuit 20 includes a feedback circuit 1, a D / A converter (DAC) 2 that operates as a reference voltage source, and an error amplification circuit 3.

As will be described in detail later, the switching regulator 100 according to the present embodiment is a switching regulator that converts an input voltage Vin input via an input terminal TI into a predetermined output voltage Vout and outputs the output voltage via an inductor L.
(A) an output switch element PDRV connected between the input terminal TI and the inductor L via a connection point LX;
(B) a rectifying switch element NDRV connected between the connection point LX and the ground;
(C) an error voltage generation circuit 20 that generates an error voltage errout between a feedback voltage Vfb corresponding to the output voltage Vout and a predetermined voltage Vref corresponding to a predetermined set value of the output voltage Vout;
(D) a pulse skip reference voltage generation circuit 4 that generates a predetermined pulse skip reference voltage Vrefm based on the input voltage Vin and the set value of the output voltage Vout;
(E) a skip comparator 7 that compares the error voltage errout with a pulse skip reference voltage Vrefm and outputs a pulse skip detection signal skpout representing the comparison result;
(F) In response to the pulse skip detection signal skpout indicating that the error voltage errout exceeds the pulse skip reference voltage Vrefm, a one-pulse signal mpgout having a predetermined pulse width is generated based on the input voltage Vin and the output voltage Vout. A one-pulse generation circuit 5 to generate,
(G) an oscillation circuit 6 for generating a sawtooth wave signal S6 having a predetermined frequency and a clock signal clkout having the above frequency and indicating the detection timing of the pulse skip detection signal skpout;
(H) a level shift circuit 61 for shifting the sawtooth wave signal S6 by a predetermined shift amount by a predetermined shift amount;
(I) a PWM comparator 8 that compares the error voltage errout with the level-shifted sawtooth signal Vslope and outputs a PWM signal pwmout representing the comparison result;
(J) Based on the PWM signal pwmout, the pulse skip detection signal skpout, the one-pulse signal mpgout, and the clock signal clkout, the output switch element PDRV and the rectifying switch element NDRV are controlled on and off, respectively, and the PWM comparator 8 and the one-pulse The generation circuit 5 and the switching control circuit 10 that controls the oscillation circuit 6 are provided.

As will be described in detail later, the pulse skip reference voltage Vrefm is set to have a voltage between the upper limit value and the lower limit value of the sawtooth wave signal Vslope after the level shift, and the switching control circuit 10 includes the oscillation circuit 6. And controlling the one-pulse generation circuit 5 to stop the operation,
(1) At the above detection timing, when it is detected that the error voltage errout is higher than the pulse skip reference voltage Vrefm based on the pulse skip detection signal skpout, the PWM comparator 8 is controlled to operate, and the frequency is determined according to the PWM signal pwmout. While performing a pulse width modulation control operation for on / off control of the output switch element PDRV and the rectifier switch element NDRV,
(2) At the detection timing, when it is detected that the error voltage errout is lower than the pulse skip reference voltage Vrefm based on the pulse skip detection signal skpout, the operations of the oscillation circuit 6 and the PWM comparator 8 are stopped and the one pulse generation circuit 5 When the error voltage errout exceeds the pulse skip reference voltage Vrefm is detected based on the pulse skip detection signal skpout, the oscillation circuit 6 is controlled to operate and output according to the one pulse signal mpgout. The switch element PDRV is turned on and the rectifier switch element NDRV is controlled to be turned off. When it is detected that the one-pulse signal mpgout has been generated by the one-pulse generator circuit 5, the operation of the one-pulse generator circuit 5 is stopped. It is characterized by performing pulse frequency modulation control operation for controlling the so that.

  In FIG. 1, the output switch element PDRV is connected between the input terminal TI and the connection point LX, and the rectification switch element NDRV is connected between the connection point LX and the ground. The voltage at the connection point LX is output as an output voltage Vout to the load circuit 90 via the high frequency rejection and smoothing low-pass filter including the inductor L and the smoothing capacitor Cout, and the output terminal OUT. Further, the output voltage Vout is output to the feedback circuit 1, the pulse skip reference voltage generation circuit 4, and the one pulse generation circuit 5.

  In FIG. 1, the feedback circuit 1 includes voltage dividing resistors R11 and R12 and a capacitor C11 that operates as a noise filter. The feedback circuit 1 divides the output voltage Vout by a predetermined voltage dividing ratio and is proportional to the output voltage Vout. Vfb is output to the inverting input terminal of the error amplifier circuit 3. The D / A converter 2 receives a digital output voltage setting signal Sout representing a voltage corresponding to the setting value of the output voltage Vout from an external circuit of the switching regulator 100, and a voltage value included in the output voltage setting signal Sout. Is D / A converted into a reference voltage Vref and output to the non-inverting input terminal of the error amplifier circuit 3. Further, the error amplifying circuit 3 amplifies the difference voltage between the feedback voltage Vfb and the reference voltage Vref, and uses a voltage proportional to the difference voltage as the error voltage errout and the non-inverting input terminal of the PWM comparator 8 and Output to the inverting input terminal of the skip comparator 7. Note that the gain of the error amplifying circuit 3 is set to a sufficiently large value larger than zero.

  Further, in FIG. 1, the oscillation circuit 6 is stopped in response to a high level reset control signal rstosc from the switching control circuit 10 and is brought into a reset state. The oscillation circuit 6 starts operating in response to the low-level reset control signal rstosc, generates a sawtooth wave signal S6 and a clock signal clkout having a predetermined frequency, and level-shifts the sawtooth wave signal S6. While outputting to the circuit 61, the clock signal clkout is output to the switching control circuit 10. Here, the oscillation circuit 6 generates the sawtooth wave signal S6 and the clock signal clkout so that the falling timing of the clock signal matches the falling timing of the sawtooth wave signal S6. The period of the clock signal clkout and the sawtooth signal S6 is set to be longer than the pulse width of the one-pulse signal mpgout described later.

FIG. 2 is a circuit diagram showing a configuration of the level shift circuit 61 of FIG. In FIG. 2, the level shift circuit 61 includes a depletion type transistor 611 and a constant current source 612 connected in series between an input terminal TI and the ground. Here, the sawtooth wave signal S6 is output to the gate of the transistor 611, and the voltage at the connection point between the transistor 611 and the constant current source 612 is output to the inverting input terminal of the PWM comparator 8 as the sawtooth wave signal Vslope after the level shift. Is done. That is, the level shift circuit 61 shifts the voltage level of the input sawtooth wave signal S6 by a predetermined shift amount to generate the sawtooth wave signal Vslope. Here, the shift amount in the level shift circuit 61 in FIG. 2 is set so that the error voltage errout is within the voltage change range of the sawtooth wave signal Vslope after the level shift. Preferably, the shift amount in level shift circuit 61 is set so that error voltage errout is not in the vicinity of the upper limit value and lower limit value of the voltage change range of sawtooth wave signal Vslope after the level shift, but in the middle thereof. .

  In FIG. 1, the PWM comparator 8 is stopped in response to a high level reset control signal rstpwm from the switching control circuit 10 and is brought into a reset state. The PWM comparator 8 starts operating in response to the low level reset control signal rstpwm, compares the error voltage errout with the voltage level of the sawtooth signal Vslope, and generates the PWM signal pwmout indicating the comparison result. Output to the switching control circuit 10. Specifically, the PWM comparator 8 generates a high-level PWM signal pwmout when the error voltage errout is higher than the voltage level of the sawtooth wave signal Vslope, while the error voltage errout is equal to or lower than the voltage level of the sawtooth wave signal Vslope. In some cases, a low level PWM signal pwmout is generated.

  FIG. 3 is a circuit diagram showing a configuration of the pulse skip reference voltage generation circuit 4 of FIG. In FIG. 3, a pulse skip reference voltage generation circuit 4 includes variable resistors 41, 42, and 45, a constant current source 43 that outputs a predetermined constant current Is, a constant current source 44 that outputs a predetermined constant current Iref, Current mirror circuit CM1 having pMOS transistors p11 and p12, current mirror circuit CM2 having nMOS transistors n21 and n22, current mirror circuit CM3 having nMOS transistors n11 and n12, and nMOS transistors n13 and n14 A current mirror circuit CM4 and pMOS transistors p1 and p2 are provided. Here, the resistance values R41, R42, and Rref of the variable resistors 41, 42, and 45 are set according to the output voltage setting signal Sout.

  In FIG. 3, the variable resistor 41 has one end connected to the input terminal TI and the other end connected to the pMOS transistor p1. A predetermined bias voltage Vbias1 for turning on the pMOS transistor p1 is applied from the external circuit of the switching regulator 100 to the gate of the pMOS transistor p1. Further, the current I3 flowing through the variable resistor 41 is output to the current mirror circuit CM3, and the current mirror circuit CM3 returns the current I3 with a predetermined mirror ratio and outputs it. In FIG. 3, the current output from the current mirror circuit CM3 is subtracted from the current Is, and the current after the subtraction is folded back at a predetermined mirror ratio by the current mirror circuits CM4 and CM1 and output as the current I1.

  In FIG. 3, the variable resistor 42 has one end connected to the input terminal TI and the other end connected to the pMOS transistor p2. A predetermined bias voltage Vbias2 for turning on the pMOS transistor p2 is applied from the external circuit of the switching regulator 100 to the gate of the pMOS transistor p2. The current flowing through the variable resistor 42 is output to the current mirror circuit CM2, and the current mirror circuit CM2 outputs the current I2 by folding the current flowing through the variable resistor 42 at a predetermined mirror ratio.

  Further, the current I2 is subtracted from the current I1, and the current (I1-I2) after the subtraction is added to the current Iref and flows to the ground via the variable resistor 45. The voltage across the variable resistor 45 is output to the non-inverting input terminal of the skip comparator 7 as a pulse skip reference voltage Vrefm (see FIG. 1).

  In FIG. 3, the source voltage of the pMOS transistor p1 becomes a voltage (Vbias1 + Vthp1) obtained by level shifting the bias voltage Vbias1 by the threshold voltage Vthp1 of the pMOS transistor p1. Therefore, the current value of the current I3 flowing through the variable resistor 41 is expressed by the following equation.

I3 = (Vin−Vbias1−Vthp1) / R41 (1)

  Therefore, when each mirror ratio of the current mirror circuits CM3 and CM4 is 1, the current value of the current I1 is expressed by the following equation.

I1 = Is- (Vin-Vbias1-Vthp1) / R41 (2)

On the other hand, the source voltage of the pMOS transistor p2 becomes a voltage (Vbias2 + Vthp2) obtained by level shifting the bias voltage Vbias2 by the threshold voltage Vthp2 of the pMOS transistor p2. Therefore, when the mirror ratio of the current mirror circuit CM2 is 1, the current value of the current I2 is expressed by the following equation.
I2 = (Vin−Vbias2−Vthp2) / R42 (3)

  Therefore, the following equation is obtained from the equations (2) and (3).

Vrefm
= Rref × (Iref + I1-I2)
= Rref * [Iref + {Is- (Vin-Vbias1-Vthp1) / R41}
-(Vin-Vbias2-Vthp2) / R42] (4)

  As apparent from the equation (1), the pulse skip reference voltage Vrefm is set to the resistance values Rref, R41, R42 set according to the output voltage setting signal Sout, the current values of the constant currents Iref, Is, and the bias voltage Vbias1. , Vbias2 can be set to an arbitrary value depending on the input voltage Vin and the output voltage set value. In the present embodiment, the pulse skip reference voltage Vrefm is set to a voltage between the upper limit value and the lower limit value of the voltage level of the sawtooth wave signal Vslope. Further, the pulse skip reference voltage Vrefm is such that the current value of the output current Iout output from the switching regulator 100 when the operation of the switching regulator 100 shifts from the PFM control operation to the PWM control operation, and the operation mode of the switching regulator 100 is the current. Discontinuous operation mode (an operation mode in which the inductor current IL is zero, and control is performed so that the inductor current IL does not flow backward from the output terminal OUT to the rectifying switch element NDRV through the inductor L as will be described in detail later. The current value of the output current Iout at the critical point (also referred to as a critical current value) at the transition point from the current continuous operation mode (the operation mode in which there is no period when the inductor current IL is zero) to the current continuous operation mode. Is set.

  FIG. 4 is a graph showing the output voltage dependency of the relationship between the input voltage Vin and the duty ratio in the continuous current operation mode from the critical point of the switching regulator 100 of FIG. Here, the duty ratio is a ratio of the output voltage Vout to the input voltage Vin. As shown in FIG. 4, the duty ratio decreases as the input voltage Vin increases, and the duty ratio increases as the output voltage Vout increases. Further, the relationship between the duty ratio at the predetermined output voltage Vout1 and the input voltage Vin can be approximated by a broken line in which a straight line having an inclination A11 and a straight line having an inclination A21 (0> A21> A11) are connected at an intersection. Further, the relationship between the duty ratio and the input voltage Vin at a predetermined output voltage Vout2 (Vout2> Vout1) can be approximated by a broken line connecting a straight line having an inclination A12 and a straight line having an inclination A22 (A22> A21) at an intersection. .

  Further, the slope A11 in FIG. 4 indicates the current value of the constant current Is in FIG. 3, the resistance value R41, the bias voltage Vbias1, the size ratio of the nMOS transistors n11 and n12 constituting the current mirror circuit CM3, and the current mirror circuit. The current I1 can be adjusted and set by adjusting the size ratio of the nMOS transistors n13 and n14 constituting the CM4 and the size ratio of the pMOS transistors p11 and p12 constituting the current mirror circuit CM1. Further, the slope A21 can be set by adjusting the current I2 by adjusting the resistance value R42 of FIG. 3, the bias voltage Vbias2, and the size ratio of the nMOS transistors n21 and n22 constituting the current mirror circuit CM2. Further, the output voltage dependency of the relationship between the input voltage Vin and the duty ratio (for example, the change in the relationship between the input voltage Vin and the duty ratio when the output voltage Vout changes from Vout1 to Vout2 in FIG. 3). It is obtained by changing the resistance values Rref, R41, R42 according to the output voltage setting signal Sout.

  Therefore, with respect to the duty ratio duty at the critical point at which the switching from the current discontinuous operation mode to the current continuous operation mode is performed under any input / output conditions of the switching regulator 100, the pulse skip voltage Vrefm is set to the output current Iout at the critical point. After setting the current value to be a critical current value, by adjusting the respective current values of the current I1 added to and subtracted from the constant current Iref in the equation (4), the slope of FIG. A desired pulse skip voltage Vrefm can be generated by setting A11, A12, A21 and slope A22.

  Referring back to FIG. 1, the skip comparator 7 compares the error voltage errout with the voltage level of the pulse skip reference voltage Vrefm, generates a pulse skip detection signal skpout indicating the comparison result, and outputs it to the switching control circuit 10. The pulse skip detection inverted signal skpoutb is output to the one pulse generation circuit 5 through the inverter 9. Specifically, the skip comparator 7 generates a high-level pulse skip detection signal skpout when the error voltage errout is lower than the pulse skip reference voltage Vrefm, while when the error voltage errout is equal to or higher than the pulse skip reference voltage Vrefm. A low level pulse skip detection signal skpout is generated.

  FIG. 5 is a circuit diagram showing a configuration of the one-pulse generation circuit 5 of FIG. In FIG. 5, a one-pulse generation circuit 5 includes a slope generation circuit 54, a reference voltage generation circuit 55, a comparator 52, an OR gate 60, a Schmitt buffer 53, inverters 57 and 59, a NOR gate 58, and a reset signal generation circuit. 56 and a flip-flop 51. Here, the reference voltage generation circuit 55 includes resistors 552 and 553 having resistance values R552 and R553, respectively, and a capacitor 551 that operates as a noise filter, and divides the output voltage Vout at a predetermined voltage dividing ratio. The reference voltage Vrefmpg is output to the non-inverting input terminal of the comparator 52.

  In FIG. 5, the slope generation circuit 54 includes a pMOS transistor p54, an nMOS transistor n54, a resistor 541 having a resistance value R541, and a capacitor 542 having a capacitance value C452. Here, the nMOS transistor n54 has one end grounded and the other end connected to one end of the resistor 541. The pMOS transistor p54 has one end connected to the input terminal TI and the other end connected to the other end of the resistor 541. Further, the connection point between the resistor 541 and the nMOS transistor n54 is connected to the other end of the capacitor 542 having one end grounded, and the voltage at the connection point is output to the inverting input terminal of the comparator 52 as the slope voltage vs. The Further, the reset control signal rst from the reset signal generation circuit 56 is output to the gates of the pMOS transistor p54 and the nMOS transistor n54.

  In the slope generation circuit 54 of FIG. 5, when the reset control signal rst from the reset signal generation circuit 56 is at a high level, the pMOS transistor p54 is turned off and the nMOS transistor n54 is turned on, so that the slope generation circuit 54 is in a reset state. The operation is stopped and a low-level slope voltage vs is output. On the other hand, when the reset control signal rst from the reset signal generation circuit 56 is at a low level, the pMOS transistor p54 is turned on and the nMOS transistor n54 is turned off, so that the reset state of the slope generation circuit 54 is released, and the slope generation circuit 54 Starts operation. Then, the slope generation circuit 54 charges the capacitor 542 with the input voltage Vin via the resistor R541, and generates a slope voltage vs that is a voltage across the capacitor 542.

In FIG. 5, a reset control signal rstmpg (described in detail later) from the switching control circuit 10 and a sleep signal slp from an external circuit of the switching regulator 100 are output to the OR gate 60. Here, the sleep signal slp represents whether or not the operation state of the switching regulator 100 is set to the sleep state. Further, the output signal from the OR gate 60 is output to the first reset terminal of the comparator 52 and the first input terminal of the NOR gate 58. In addition, the reset control signal rst from the reset signal generation circuit 56 is output to the second reset terminal of the comparator 52. The comparator 52 stops operating when at least one of the output signal from the OR gate 60 and the reset control signal rst is at a high level, and is brought into a reset state. On the other hand, when the output signal from the OR gate 60 and the reset control signal rst are at the low level, the slope voltage vs is compared with the reference voltage Vrefmpg, and a signal indicating the comparison result is sent to the NOR gate 58 via the Schmitt buffer 53 and the inverter 57. Output to the second input terminal. Further, the output signal from the NOR gate 58 is output to the inverting reset terminal RB of the flip-flop 51 .

  In FIG. 5, the pulse skip detection inverted signal skpoutb is output to the clock terminal CK of the flip-flop 51 via the inverter 59, and the input voltage Vin is output to the data terminal D of the flip-flop 51 via the input terminal TI. . The output signal from the flip-flop 51 is output to the reset signal generation circuit 56 and the switching control circuit 10 as a one-pal signal mpgout. The reset signal generation circuit 56 includes a delay element 561 and a NOR gate 562. The one-pal signal mpgout is directly output to the first input terminal of the NOR gate 562 and is output to the second input terminal of the NOR gate 562 via the delay element 561. An output signal from the NOR gate 562 is output as a reset control signal rst to the second reset terminal of the comparator 52, the gate of the pMOS transistor p54, and the gate of the nMOS transistor n54. The reset signal generation circuit 56 generates a high-level reset control signal rst, thereby stopping the operations of the comparator 52 and the slope generation circuit 54 and setting the reset state.

  In FIG. 5, when at least one of the sleep signal slp and the reset control signal rstmpg is at a high level, the one-pulse generation circuit 5 stops operating, enters a sleep state, and a low-level one-pulse signal mpgout is generated. On the other hand, when the sleep signal slp and the reset control signal rstmpg are at a low level, the one-pulse generation circuit 5 starts operating, the sleep state is released, the reset state of the flip-flop 51 is released, and the flip-flop 51 is pulse skipped. A high-level one-pulse signal mpgout is output in response to a rising edge of the voltage level of the detection signal skpout from a low level to a high level. Further, when the high-level one-pulse signal mpgout is output, the reset signal generation circuit 56 outputs the low-level reset control signal rst, and in response thereto, the reset state of the comparator 52 and the slope generation circuit 54 is released. The When the reset state is released, the comparator 52 compares the slope voltage vs with the reference voltage Vrefmpg, and switches the voltage level of the output signal from the high level to the low level when the slope voltage vs exceeds the reference voltage Vrefmpg. In response to this, the voltage level of the one-pulse signal mpgout changes from the high level to the low level.

  When the voltage level of the one pulse signal mpgout changes to a low level, the reset signal generation circuit 56 outputs a high level reset control signal rst. In response to this, the comparator 52 and the slope generation circuit 54 are reset again. Stop operation. The comparator 52 and the slope generation circuit 54 are configured such that the voltage levels of the sleep signal slp and the reset control signal rst are low level, and the voltage level of the pulse skip detection signal skpout is switched from low level to high level. The operation is stopped after being reset.

  In FIG. 5, the pulse width of the one-pulse signal mpgout (as will be described in detail later, the pulse width Ton of the one-pulse signal mpgout is equal to the ON time of the output switch element PDRV when the switching regulator 100 is performing the PFM control operation). Is expressed by the following equation.

Ton
= C542 × {R553 / (R552 + R553)} × Vout × (R541 / Vin)
(5)

  As is apparent from this equation (5), the pulse width of the one-pulse signal mpgout depends on the duty ratio duty (≈Vout / Vin), and the capacitance value C542 of the capacitor 542 and the resistance 541 in the slope generation circuit 54 By adjusting the resistance value R541 and the resistance values R552 and R553 of the resistors 552 and 553 in the reference voltage generation circuit 55, the pulse width of the one-pulse signal mpgout can be adjusted to a desired value, and output at the time of PFM control operation The on-time of the switch element PDRV can be adjusted. In the present embodiment, the pulse width of the one-pulse signal mpgout is set to be substantially equal to the duty ratio immediately after the operation of the switching regulator 100 shifts from the PFM control operation to the PWM control operation, that is, the ON time of the output switch element PDRV. Is done.

  Referring back to FIG. 1, the switching control circuit 10 is described in detail later based on the PWM signal pwmout, the one-pulse signal mpgout, the pulse skip detection signal skpout, the clock signal clkout, and the voltage at the connection point LX. Reset control signals rstpwm, rstmpg, rstosc and gate signals pgate, ngate are generated. Then, the gate signal pgate is output to the gate of the output switch element PDRV, while the gate signal ngate is output to the gate of the rectifying switch element NDRV, and switching between the PFM control operation and the PWM control operation of the switching regulator 100 is performed. On / off control of the switch element PDRV and the rectifying switch element NDRV is performed. Further, the switching control circuit 10 monitors the voltage at the connection point LX among the output switch element PDRV, the rectifying switch element NDRV, and the inductor L, and rectifies from the output terminal OUT via the inductor L based on the voltage. When a reverse current flowing to the switch element NDRV side or a sign of the reverse current is detected, the rectifier switch element NDRV is shut off, and control is performed to prohibit current from flowing from the connection point LX to the rectifier switch element NDRV. Has a backflow prevention function. When the switching control circuit 10 does not detect the reverse current and the sign of the reverse current, the voltage value of the output voltage Vout becomes the set value of the output voltage Vout and the output switch element PDRV and the rectifier switch element NDRV Gate signals pgate and ngate are generated so as to complementarily turn on and off.

  In FIG. 1, the switching control circuit 10 includes a gate signal generation circuit 11. FIG. 6 is a circuit diagram showing a configuration of the gate signal generation circuit 11 of FIG. In FIG. 6, the gate signal generation circuit 11 includes inverters 12, 14, 16, a NAND gate 13, a NOR gate 15, and a buffer 17. The pulse skip detection signal skpout is output to the first input terminal of the NAND gate 13 through the inverter 12, and the PWM signal pwmout is directly output to the second input terminal of the NAND gate 13. Further, the output signal from the NAND gate 13 is output to the first input terminal of the NOR gate 15 via the inverter 14, and the one-pulse signal mpgout is output to the second input terminal of the NOR gate 15. The output signal from the NOR gate 15 is output to the gate of the output switch element PDRV as the gate signal pgate through the inverter 16 and the buffer 17.

  Next, the operation of the switching regulator 100 will be described with reference to FIGS. FIG. 7 is a state transition diagram showing the operation of the switching regulator 100 of FIG. 1, and FIG. 8 is a timing chart showing the operation of the switching regulator 100 of FIG. When the voltage level of the sleep signal slp is low, as shown in FIG. 7, the state of the switching regulator 100 transitions between the first to fourth states. 9 to 12 are circuit diagrams showing operation states in the first to fourth states of the switching regulator 100 of FIG. 9 to 12, the hatched circuit has stopped operating and is in a reset state. Hereinafter, the operation of the switching regulator 100 in each state will be described.

(1) First state.
The first state will be described with reference to FIG. 7, FIG. 8, and FIG. In FIG. 7, the switching control circuit 10 changes the state of the switching regulator 100 to the first state when the voltage level of the pulse skip detection signal skpout is high at the rising timing of the clock signal clkout. The first state is a pulse skip state in which the on-pulse of the output switch element PDRV is skipped at a light load when the output current Iout that is a load current output from the output terminal OUT is relatively small. In the first state, the switching control circuit 10 turns off the output switch element PDRV. Furthermore, the switching control circuit 10 prevents the current from flowing back from the connection point LX to the rectifying switch element NDRV by turning off the rectifying switch element NDRV by the above-described backflow prevention function.

  In the first state, the switching control circuit 10 generates a high level reset control signal rstosc in response to the high level pulse skip detection signal skpout (see FIG. 7). In response to this, the oscillation circuit 6 is reset and stops generating the sawtooth wave signal S6 and the clock signal clkout (see FIG. 8). The switching control circuit 10 generates a high level reset control signal rstpwm, and in response to this, the PWM comparator 8 is reset.

  Further, the switching control circuit 10 generates a low level reset control signal rstmpg. In response to this, the one-pulse generation circuit 5 is in an operating state, but in response to the high-level reset control signal rst generated by the reset signal generation circuit 56 (see FIG. 5) after the one-pulse signal rstmpg is generated. The comparator 52 and the slope generation circuit 54 are reset. For this reason, in the first state, the one-pulse generation circuit 5 is substantially in a reset state, and the current consumption is greatly reduced as compared to when the comparator 52 and the slope generation circuit 54 are operating.

  As described above, as shown in FIG. 9, in the first state, the one-pulse generation circuit 5, the oscillation circuit 6, and the PWM comparator 8 are in a reset state. Therefore, in the first state, useless current consumption of the switching regulator 100 can be reduced.

(2) Second state.
The second state will be described with reference to FIG. 7, FIG. 8, and FIG. In the first state, when the output voltage Vout decreases as the output current Iout increases, the error voltage errout increases and becomes higher than the pulse skip reference voltage Vrefm. In response to this, the voltage level of the pulse skip detection signal skpout changes from the high level to the low level, and the switching control circuit 10 changes the state of the switching regulator 100 to the second state.

  Further, in FIG. 7, the switching control circuit 10 changes the voltage level of the reset control signal rstosc from the high level to the low level at the falling edge timing of the pulse skip detection signal skpout. In response to this, the oscillation circuit 6 starts to operate and starts generating the clock signal clkout and the sawtooth wave signal S6 (see the sawtooth wave signal Vslope in FIG. 8). Further, since the voltage level of the pulse skip detection inversion signal skpoutb rises from the low level to the high level, in response to this, the one-pulse generation circuit 5 outputs a high-level one-pulse signal mpgout (see FIG. 8). In response to the high-level one-pulse signal mpgout, the gate signal generation circuit 11 of the switching control circuit 10 generates a low-level gate signal pgate having the same pulse width as the one-pulse signal mpgout, and supplies it to the output switch element PDRV. At the same time, a low level gate signal ngate is generated and output to the rectifying switch element NDRV. In response to this, the output switch element PDRV is turned on and the rectifying switch element NDRV is turned off.

(3) Third state.
The third state will be described with reference to FIG. 7, FIG. 8, and FIG. When the voltage level of the one-pulse signal mpgout changes from the high level to the low level and the on period of the output switch element PDRV ends, the switching control circuit 10 changes the state of the switching regulator 100 to the third state (see FIG. 8). .) The third state is a pulse skip determination state in which transition is made to the first or fourth state based on the pulse skip detection signal skpout and the clock signal clkout. In the third state, the switching control circuit 10 changes the voltage level of the reset control signal rstmpg from the low level to the high level (see FIG. 7). In response to this, the one-pulse generation circuit 5 stops its operation ( See FIG.

  In the third state, when the voltage level of the pulse skip detection signal skpout is high at the rising timing of the clock signal clkout, the switching control circuit 10 changes the state of the switching regulator 100 to the first state. Then, the switching control circuit 10 generates a high level reset control signal rsocs, and in response to this, the oscillation circuit 6 is reset. Further, the switching control circuit 10 changes the voltage level of the reset control signal rstmpg from the high level to the low level, and controls the one-pulse generation circuit 5 to wait for the generation of the next one-pulse signal mpgout.

  On the other hand, when the voltage level of the pulse skip detection signal skpout is low at the rising timing of the clock signal clkout, the switching control circuit 10 changes the state of the switching regulator 100 to the fourth state.

(4) Fourth state.
The fourth state will be described with reference to FIG. 7, FIG. 8, and FIG. The switching control circuit 10 performs a PWM control operation in the fourth state. Specifically, as shown in FIG. 7, in the fourth state, the switching control circuit 10 changes the voltage level of the reset control signal rstppwm from high level to low level, and in response to this, the PWM comparator 8 The reset state is released. Therefore, the gate signal generation circuit 11 of the switching control circuit 10 generates the gate signal pgate synchronized with the PWM signal pwmout. For this reason, a PWM control operation is performed in which the output switch element and the rectifying switch element NDRV are on / off controlled in accordance with the PWM signal pwmout.

  In FIG. 7, in the third state, the switching control circuit 10 changes the state of the switching regulator 100 to the first state when the voltage level of the pulse skip detection signal skpout is high during the rising timing of the clock signal clkout. Transition to the state.

  In FIG. 7, when the state of the switching regulator 100 transitions to the first state, the second state, the third state, the first state,..., The ON time of the output switch element PDRV is a one-pulse signal. The pulse width is fixed to mpgout. That is, in a light load state where the output current Iout is relatively small, the switching control circuit 10 fixes the ON time of the output switch element PDRV and changes the switching cycle based on the error voltage errout and the pulse skip reference voltage Vrefm. Then, the switching regulator 100 is PFM-controlled.

  As shown in FIGS. 9, 10 and 11, only the minimum circuit in the switching regulator 100 is operated in the first to third states during the PFM control operation. Current consumption can be reduced and power conversion efficiency can be increased. In particular, as shown in FIG. 9, in the first state, the oscillation circuit 6 and the PWM comparator 8 are controlled so as to be stopped by a high-level reset control signal rstosc and rstpwm. Since the comparator 52 and the slope generation circuit 54 are controlled to stop the operation by the reset control signal rst, the power conversion efficiency at light load can be improved as compared with the conventional technique.

  In a heavy load state where the output current Iout is relatively large, the switching control circuit 10 changes the state of the switching regulator 100 to the fourth state, fixes the switching cycle of the output switch element PDRV to the cycle of the clock signal clkout, and Based on the error voltage errout and the sawtooth wave signal Vslope, a PWM control operation for determining the on-time of the output switch element PDRV is performed. At this time, as shown in FIG. 12, the switching control circuit 10 stops the operation of the one-pulse generation circuit 5 and performs the PWM control operation according to the PWM signal pwmout from the PWM comparator 8 while the skip comparator 7 is operated. Yes. According to the present embodiment, the switching control circuit 10 performs the PWM control operation while the skip comparator 7 is operated. Therefore, even if the switching regulator 100 changes from the heavy load state to the light load state, the rising edge of the clock signal clkout Based on the voltage level of the pulse skip detection signal skpout at the timing, the state of the switching regulator 100 is changed to the first state (see FIG. 7), and can be automatically switched to the PFM control operation. Therefore, the optimum switching frequency can be selected with respect to the fluctuation of the load of the switching regulator 100, and even if the input voltage, the output voltage, and the load condition fluctuate greatly, the power conversion efficiency is increased as compared with the conventional technique. be able to.

  As described above, according to the present embodiment, it is possible to select an optimum switching frequency for a wide range of input voltage, output voltage, and load condition variation as compared with the prior art, and to achieve the conventional over the entire load current range. Compared with technology, power conversion efficiency can be increased. Further, the pulse skip reference voltage generation circuit 4 causes the current value of the output current Iout when the switching regulator 100 shifts from the PFM control operation to the PWM control operation to be substantially equal to the current value of the output current Iout at the critical point. Therefore, the variation in the load current at the time of transition can be suppressed and stabilized as compared with the prior art, and the target value can be set. For this reason, the fluctuation | variation of the output voltage Vout when shifting from PFM control operation to PWM control operation can be suppressed compared with a prior art.

  Further, according to the present embodiment, the shift amount in the level shift circuit 61 of FIG. 2 is set so that the error voltage errout is within the voltage change range of the sawtooth wave signal Vslope after the level shift. Then, the PWM signal pwmout is generated using the sawtooth wave signal Vslope after the level shift and the error voltage errout, and the PWM control operation using the PWM signal pwmout is performed. Therefore, the voltage level of the PWM signal pwmout can be inverted at the timing at which the magnitude relationship between the error voltage errout and the voltage level of the sawtooth wave signal Vslope is reversed, and the switching regulator 100 that can respond faster than the conventional technique can be provided.

  Note that another level shift circuit similar to the level shift circuit 61 of FIG. 2 is provided between the pulse skip reference voltage generation circuit 4 and the skip comparator 7, and the pulse skip reference voltage Vrefm after the level shift is provided to the skip comparator 7. It may be output. As a result, the variation of the sawtooth wave signal Vslope due to the variation in the level shift amount of the level shift circuit 61 and the variation due to the temperature can be superimposed on the pulse skip reference voltage Vrefm. The variation of the load current at the switching timing between the PFM control operation and the PWM control can be further suppressed and stabilized.

  In the above description, the example in which the present invention is applied to the voltage feedback step-down switching regulator has been described. However, the present invention is not limited to this. The present invention detects the inductor current IL based on the voltage at the connection point LX between the output switch element PDRV and the inductor L, and generates a ramp voltage proportional to the detected inductor current IL to perform switching control. The present invention can also be applied to a feedback step-down switching regulator, an asynchronous rectification step-down switching regulator using a diode as a rectifying element instead of a rectifying switching element NDRV that is a transistor, and a step-up switching regulator.

1 ... feedback circuit,
2 ... D / A converter (reference voltage source),
3 ... error amplification circuit,
4. Pulse skip reference voltage generation circuit,
5 ... One pulse generation circuit,
6: Oscillator circuit,
7 ... Skip comparator,
8 ... PWM comparator,
9 ... Inverter,
10: Switching control circuit 10,
20: Error voltage generation circuit,
11: Gate signal generation circuit,
61 ... Level shift circuit,
100: switching regulator,
Cout: smoothing capacitor,
L ... Inductor,
NDRV: Rectifier switch element,
OUT: Output terminal,
PDRV: Output switch element,
TI: Input terminal.

Japanese Patent No. 3647811 JP 2010-063276 A JP 2008-92712 A JP 2009-213228 A JP 2009-225642 A

Claims (7)

In a switching regulator that converts an input voltage input via an input terminal into a predetermined output voltage and outputs the voltage via an inductor.
An output switch element connected via a connection point between the input terminal and the inductor;
A rectifying element connected between the connection point and ground,
An error voltage generation circuit that generates an error voltage between a feedback voltage corresponding to the output voltage and a predetermined voltage corresponding to a predetermined set value of the output voltage;
A pulse skip reference voltage generation circuit for generating a predetermined pulse skip reference voltage based on the input voltage and the set value of the output voltage;
A first comparison circuit that compares the error voltage with the pulse skip reference voltage and outputs a pulse skip detection signal representing the comparison result;
One-pulse generation for generating a one-pulse signal having a predetermined pulse width based on the input voltage and the output voltage in response to the pulse skip detection signal indicating that the error voltage exceeds the pulse skip reference voltage Circuit,
An oscillation circuit that generates a sawtooth wave signal having a predetermined frequency, and a clock signal having the frequency and representing the detection timing of the pulse skip detection signal;
A second comparison circuit for comparing the error voltage with the sawtooth signal and outputting a pulse width modulation signal representing the comparison result;
Based on the pulse width modulation signal, the pulse skip detection signal, the one pulse signal, and the clock signal, the output switch element and the rectifier element are controlled to be turned on and off, respectively, and the second comparison circuit, A switching control circuit for controlling the one-pulse generation circuit and the oscillation circuit;
The pulse skip reference voltage is set to have a voltage between an upper limit value and a lower limit value of the sawtooth signal,
When the switching control circuit is controlling to operate the oscillation circuit and stop the operation of the one-pulse generation circuit,
(A) At the detection timing, when it is detected that the error voltage is higher than the pulse skip reference voltage based on the pulse skip detection signal, the second comparison circuit is controlled to operate, and the pulse width While performing a pulse width modulation control operation for on / off control of the output switch element and the rectifier element at the frequency according to a modulation signal,
(B) When it is detected at the detection timing that the error voltage is lower than the pulse skip reference voltage based on the pulse skip detection signal, the operations of the oscillation circuit and the second comparison circuit are stopped and The one pulse generation circuit is controlled to operate, and when it is detected that the error voltage exceeds the pulse skip reference voltage based on the pulse skip detection signal, the oscillation circuit is controlled to operate, and The output switch element is controlled to be turned on and the rectifier element is turned off in accordance with the one-pulse signal, and when the one-pulse signal generation by the one-pulse generation circuit is detected, the operation of the one-pulse generation circuit is stopped. It is characterized by performing a pulse frequency modulation control operation to control Switch ring regulator.   The one-pulse generation circuit is substantially operated until being input by the pulse skip detection signal indicating that the error voltage exceeds the pulse skip reference voltage after being controlled to operate by the switching control circuit. The switching regulator according to claim 1, wherein the switching regulator is stopped.   The pulse width is set to be substantially equal to an ON time of the output switch element immediately after the operation of the switching control circuit shifts from the pulse frequency modulation control operation to the pulse width modulation control operation. The switching regulator according to claim 1 or 2. The pulse skip reference voltage generation circuit is configured such that when the operation of the switching control circuit shifts from the pulse frequency modulation control operation to the pulse width modulation control operation, the current value of the output current output from the switching regulator is the switching operation mode such that the current value substantially equal to the output current that put the critical point of transition from the current discontinuous mode in the current continuous mode of the regulator, and generates the pulse skip reference voltage The switching regulator according to any one of claims 1 to 3. The switching regulator further includes a level shift circuit that shifts the voltage level of the sawtooth wave signal by a predetermined shift amount and outputs the sawtooth wave signal after the shift to the second comparison circuit,
5. The switching according to claim 1, wherein the shift amount is set so that the error voltage falls within a voltage change range of the sawtooth wave signal after the level shift. 6. regulator. The switching control circuit shuts off the rectifying element when detecting a reverse current flowing from the output terminal of the switching regulator to the rectifying element through the inductor or an indication of the reverse current based on the voltage at the connection point. The switching regulator according to any one of claims 1 to 5, wherein: The rectifying element is a rectifying switch element composed of a switch element,
The switching control circuit sets the output switch element and the rectifying switch element so that the voltage value of the output voltage becomes a set value of the output voltage and the output switch element and the rectifying switch element are complementarily turned on. The switching regulator according to claim 1, wherein on / off control is performed.

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