KR100729845B1 - Digital pulse width modulation generator with clock divider and clock synthesizer - Google Patents

Abstract

A digital PWM(Pulse Width Modulation) generator using a clock divider and a clock synthesizer is provided to reduce a size of a circuit and increase compatibility with an external digital system by changing an analog PWM process of a saw tooth wave or latch structure into a digital PWM circuit which divides and synthesizes a reference clock. A digital PWM generator using a clock divider and a clock synthesizer includes a clock generator(1), a clock divider(2), a clock selection unit(3), a clock control unit(5), a clock synthesizer(4), and a pulse width adjusting unit(6). The clock generator(1) generates an internal reference clock of a system. The clock divider(2) divides the generated reference clock into N clocks. The clock selection unit(3) selectively transmits some clocks to the clock synthesizer(4) according to a control signal which is transmitted from the clock control unit(5) of a plurality of clocks divided by the clock divider(2). The clock control unit(5) analyzes a control signal or a command selected by an external system using an SMPS(Switching Mode Power Supply). The clock control unit(5) controls the clock selection unit(3) in a normal mode by transmitting the control signal to the clock selection unit(3) or checking a load change of the SMPS. The clock synthesizer(4) synthesizes and converts signals selected from the clock selection unit(3) into PWM signals. The pulse width adjusting unit(6) analyzes and transmits a load change signal of the SMPS to the clock control unit(5).

Description

Digital Pulse Width Modulation generator with clock divider and clock synthesizer}

1 is a block diagram of a digital PWM generator in accordance with the present invention.

2 is a synthesized output signal using a divided clock signal.

3 is an input of a load change signal using a linking operation and a comparator with an external MCU.

4 is a circuit diagram of a flyback SMPS to which digital PWM is applied.

* Description of symbols on the main parts of the drawings *

1: clock generator 2: clock divider

3: clock selector 4: clock synthesizer

5: clock control unit 6: pulse width control unit

7: Communication support department 10: Digital PWM generator

The present invention relates to a digital pulse width modulation (PWM) generator, and more particularly, to implement a switching mode power supply (hereinafter referred to as SMPS). An analog PWM generator is a digital PWM generator for generating a PWM signal using a clock division and clock synthesis method with respect to a reference clock.

The analog PWM generator used in the conventional SMPS, where information is commonly used in electrical equipment, compares the selected signal at the sawtooth wave and the load stage to determine the width of the PWM signal or to skip the reference clock using the latch method. Digital PWM-related circuits, which are patented or published, are circuits using a method of counting using a reference frequency to determine a pulse width and a method of designing a voltage comparing with a sawtooth wave by a counter. .

However, the conventional SMPS, which adjusts the pulse width of the PWM signal by comparing the load fluctuation signal with the sawtooth wave generator, has a problem in that it is inconvenient to decorate the sawtooth wave generation circuit and the compatibility becomes poor when the external system is a digital system.

Accordingly, the present invention facilitates the control by digitizing the analog PWM generator used in the SMPS device, which is commonly used for information electronic appliances, by using clock division and clock synthesis, and microcontrol unit (MCU) in a digital home appliance or a general home appliance. The present invention provides a digital PWM generator using clock division and clock synthesis to enable interoperation with digital communication.

The present invention for achieving the above object, the clock generation unit for generating a system internal reference clock; A clock divider for dividing the clock into N clocks using the reference clock generated by the clock generator; A clock selector for selectively sending a plurality of clocks to a clock synthesizer according to a control signal transmitted from a clock controller among a plurality of clock signals divided through the clock divider; A clock controller which analyzes a control signal or a command selected by an external system of the SMPS and sends a control signal to the clock selector or checks a load variation inside the SMPS to control the clock selector when the normal mode is selected; A clock synthesizer for synthesizing the signals selected by the clock selector into a PWM signal; It is characterized by consisting of a pulse width adjusting unit for analyzing the load change signal of the SMPS and sending it to the clock control unit.

According to the present invention, it is preferable to increase the size of the reference clock by a multiple of two or more by using a rising edge or a falling edge by using a flip-flop and generating a PWM signal through a combination of these signals.

In addition, although the present invention preferably increases the size of the reference clock by a multiple of two or more using a combination circuit of latches or gates, and generates a PWM signal through the combination of these signals, It is also possible to increase the size by more than a few times and generate a PWM signal through a combination of these signals.

In addition, the PWM signal generation method may be synthesized using a basic gate such as 'AND' or 'OR' gate.

According to another feature of the invention, the input of the load change signal to the pulse width control unit in the digital PWM generation circuit may be applied using M comparators or analog to digital converter (ADC).

In addition, the present invention may be embedded in the digital PWM generation circuit communication support circuit to control the clock control unit from the outside, or may monitor this, may control the block other than the clock control unit from the outside, or monitor this.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 1, the digital PWM generator 10 of the present invention uses a clock generator 1 for generating an internal clock of the system and a clock of several cycles using the clock generated by the clock generator 1. A plurality of clocks are selectively sent to the clock synthesizing unit according to a clock divider 2 for dividing the signal and a control signal transmitted from the clock control unit 5 among the signals of several clocks divided through the clock divider 2. The note includes a clock selector 3.

In addition, the present invention analyzes a control signal or a command selected from a system outside the SMPS to send a control signal to the clock selector 3 or check the load variation inside the SMPS to control the clock selector 3 in the normal mode. The clock controller 5, a clock synthesizer 4 for synthesizing the signals selected by the clock selector 3 to form a PWM signal, and a pulse width for interpreting the load variation signal of the SMPS and sending it to the clock controller 5. Control unit 6 and a communication support unit 7 for communication support with an external MCU.

As shown in FIG. 1, the reference clock generated by the clock generator 1 divides N different clocks using a flip-flop in the clock divider 2. N different clocks are generated by dividing the reference clock in two cycles using the rising edge clock or the falling edge clock, and then dividing the reference clock in two cycles.

Meanwhile, the signal of the analog load stage is converted into a digital signal by sending the magnitude of the signal selected at the load stage to the encoder block of the pulse width control unit 6 through M comparators composed of reference voltages having different magnitudes.

Alternatively, the signal selected at the load stage may be converted into a digital signal using an analog to digital converter (ADC) instead of M different comparators and applied to the pulse width controller.

The pulse width of the PWM signal according to the encoded signal of the pulse width adjusting unit 6 is determined by the decoder block and sent to the clock controller 5.

The clock control unit 5 outputs a clock selection control signal in consideration of the determined pulse width and the current state. At this time, the current state refers to a state divided into a normal normal operation mode (no skip signal) and a low power mode (usually a skip mode or a burst mode).

2 is a view illustrating synthesis of a PWM signal corresponding to a general skip mode or a burst mode. The selected clock signals are synthesized by the clock synthesizer to generate a PWM signal. At this time, it is also generated through the driver stage to increase the output current.

4 is a circuit applying digital PWM to a typical flyback SMPS structure. The two signals selected at the load stage are converted into digital signals using a comparator or an ADC to be applied to the digital PWM. The signals are analyzed and the pulse width controller 6 controls the pulse width, and the clock controller 5 ) Controls to synthesize the clock for the adjusted pulse width. In order to drive the power MOSFET (M1), the current amount needs to be increased, so the PWM signal output from the digital PWM is passed through the driver stage to the MOSFET (M1).

Accordingly, the present invention simplifies the PWM generation circuit by digitizing the PWM generation circuit which acts as a control inside the SMPS in order to increase the compatibility with the digital system, and improves the compatibility with the external digital system by implementing the digital PWM.

As described above, by changing from a conventional sawtooth wave or latch structure analog PWM method of SMPS to a digital PWM circuit that divides and synthesizes a reference clock, compatibility with an external digital system is increased, and the size of the circuit can be reduced. It is a very useful invention.

Claims (10)

A clock generator generating a system internal reference clock; A clock divider for dividing the clock into N clocks using the reference clock generated by the clock generator; A clock selector for selectively sending a plurality of clocks to a clock synthesizer according to a control signal transmitted from a clock controller among a plurality of clock signals divided through the clock divider; A clock controller which analyzes a control signal or a command selected by an external system of the SMPS and sends a control signal to the clock selector or checks a load variation inside the SMPS to control the clock selector when the normal mode is selected; A clock synthesizer for synthesizing the signals selected by the clock selector into a PWM signal; And Digital PWM generator using clock division and clock synthesis, characterized in that consisting of a pulse width control unit for analyzing the load fluctuation signal of the SMPS to send to the clock control unit. [Claim 2] The clock division method of claim 1, wherein the reference clock is enlarged in multiples of two or more by using a rising edge or a falling edge using a flip-flop, and a PWM signal is generated through a combination of these signals. Digital PWM generator using clock synthesis. The clock division and clock synthesis method of claim 2, wherein the reference clock is increased by a multiple of two or more by using a combination circuit of latches or gates, and a PWM signal is generated through the combination of these signals. Digital PWM generator. 3. The digital PWM generator using a clock division and clock synthesis according to claim 2, wherein the reference clock is enlarged by a multiple of two or more by using a counter, and a PWM signal is generated through a combination of these signals. The digital PWM generator using a clock division and clock synthesis according to claim 1, wherein the PWM signal is generated by synthesizing several different clock signals using a basic gate such as an 'AND' or an 'OR' gate. . The digital PWM generation circuit of claim 1, wherein the digital PWM generation circuit further includes a communication support circuit configured to externally control or monitor the clock controller. The digital PWM generation circuit of claim 1, wherein the digital PWM generation circuit further includes a communication support circuit configured to externally control or monitor a block other than a clock control unit. The digital PWM generation circuit according to claim 1, wherein an input of a load variation signal to the pulse width control unit in the digital PWM generation circuit is applied using M comparators. The digital PWM generation circuit according to claim 1, wherein an input of a load change signal to the pulse width control unit in the digital PWM generation circuit is applied by using an analog-to-digital converter (ADC). A clock generator generating a system internal reference clock; A clock divider for dividing the clock into N clocks using the reference clock generated by the clock generator; A clock selector for selectively sending a plurality of clocks to a clock synthesizer according to a control signal transmitted from a clock controller among a plurality of clock signals divided through the clock divider; A clock controller which analyzes a control signal or a command selected by an external system of the SMPS and sends a control signal to the clock selector or checks a load variation inside the SMPS to control the clock selector when the normal mode is selected; A clock synthesizing unit synthesizing the signals selected by the clock selecting unit into a PWM signal; A pulse width adjusting unit which analyzes the load variation signal of the SMPS and sends it to the clock control unit; And Digital PWM generator using clock division and clock synthesis, characterized in that consisting of a communication support unit for controlling or monitoring the clock control unit from the outside.

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