JP2534487B2 - Pulse generation circuit - Google Patents

Description

The present invention relates to a pulse generation circuit.

[Conventional technology]

In the pulse width modulation, as a circuit for generating a pulse having a pulse width corresponding to an n-bit data signal, the pulse is conventionally generated by the configuration shown in FIG. FIG. 2 is a timing chart of each part in FIG. In the set signal generation circuit 1, a set signal pulse 201 shown in FIG. 2 is generated at a position corresponding to the data signal, and the latch 2 is set by the set pulse, and the level changes from low level to high level. The latch 2 maintains a high level until the reset signal generating circuit 3 detects the reset signal 202 shown in FIG. 2 and is reset and outputs a low level when it detects the reset signal 202 shown in FIG.
As shown in 3, it outputs a pulse having a pulse width corresponding to the data signal.

[Problems to be solved by the invention]

However, in the above-mentioned conventional technique, when noise as shown in FIG. 301 is mixed in the set signal, the noise is detected and the latch 2 is set. Therefore, as shown in FIG. There is a possibility that a pulse different from a pulse having a pulse width according to the above may be generated, and it has been difficult to take measures to remove this mixed noise.

However, this problem cannot be avoided as long as a circuit that generates a pulse by using a latch is adopted.

Therefore, the present invention is intended to solve such a problem, and an object of the present invention is to provide a circuit for generating a pulse having a pulse width corresponding to a data signal regardless of whether noise is mixed. To do.

〔Example〕

Hereinafter, the present invention will be described in detail based on examples.

The data signal, which is the control signal, has three bits of information D1, D2,
A circuit for generating pulses P0, P1, P2, P3, P4, P5, P6, P7 having pulse widths corresponding to the data signals as shown in FIG. 4 will be described.

In order to realize each pulse of FIG. 4, A shown in FIG.
When each pulse of FIG. 4 is expressed by a logical expression using the waveforms of 0, A1, A2 and A3, it becomes as shown in FIG.

According to FIG. 6, each pulse P0 to P7 is a logical sum of A0 to A3,
It can be completely expressed by using a logical product, and if the data signals of D1 to D3 are at high level, the logical sum output is selected, and if the data signal is at low level, the logical product output is selected, whereby the pulses P0 to P7 shown in FIG.
Can be fully expressed.

FIG. 7 shows a pulse generating circuit that realizes this logical expression by using a logical circuit.

To the AND gate 4 and the OR gate 5, the low level signal A0 in FIG. 5 and the reference clock signal A1 are input. 6 is the data signal D1
If is a low level, the AND gate output is selected as an output, and if it is a high level, the OR gate output is selected as an output. The output of this select gate corresponds to the parentheses of the logical expression in FIG.
Waveform obtained by dividing A1 by half is shown in FIG. 5, A2 is the input signal to the AND gate 7 and OR gate 8 in the next stage. A selection gate 9 selects an AND gate output as an output when the data signal D2 is at a low level, and selects an OR gate output as an output when the data signal D2 is at a high level. The output of this selection gate corresponds to the bracket in the logic formula in Fig. 6. The output of this selection gate and the waveform obtained by dividing A2 by 1/2 are shown in Fig. 5 A3 is the AND gate 10 and OR gate of the next stage. 11 input signals. 12 is AN if the data signal D3 is low level
Select the D gate output as the output, and if it is high level, OR
It is a selection gate that selects the gate output as an output. The output waveform of the select gate 12 is exactly 3 bit data.
Outputs P0 to P8 corresponding to D1, D2, D3.

In this embodiment, the data signal is 3 bits, but in the case of n bits, the combination of the AND gate, the OR gate, and the selection gate is changed to n stages to generate a pulse having 2 ⁿ kinds of pulse widths. It is possible to realize a pulse generation circuit that generates a pulse.

〔The invention's effect〕

As described above, according to the present invention, since the circuit that generates the pulse having the pulse width corresponding to the combination of the control signals is realized by the logic gate, the pulse width corresponding to the combination of the control signals can be set even when the noise is mixed. It is extremely effective because it can generate the pulse that it has.

[Brief description of drawings]

FIG. 1 is a block diagram of a conventional pulse generating circuit. FIG. 2 is a timing diagram at various points in FIG. 1, and FIG.
The drawings are timing charts at various points in FIG. 1 when noise is mixed in the set signal. FIG. 4 is a diagram showing pulses P0 to P7 having pulse widths corresponding to the data signals D1, D2, D3. FIG. 5 shows reference waveforms A0, A1, A2, A3, and 6th waveforms used for logical operation.
The figure is a diagram showing a logical expression in which P0 to P7 are expressed by A0, A1, A2, and A3. FIG. 7 is a circuit diagram when the logical expression of FIG. 6 is realized by a digital circuit. 1 ... Set signal generation circuit 2 ... Latch 3 ... Reset signal generation circuit 4 ... AND gate 5 ... OR gate 6 ... Selection gate 7 ... AND gate 8 ... OR gate 9 ... Selection gate 10 ... … AND gate 11 …… OR gate 12 …… Selection gate

Claims (1)

(57) [Claims] 1. A circuit block having a plurality of stages, wherein a control signal is input to each of the circuit blocks, the first stage circuit block inputs a clock signal, and the first stage circuit block receives the clock signal. Based on a control signal, the clock signal or a signal of a predetermined level is selectively output, and each of the subsequent circuit blocks outputs the output of the previous circuit block and the clock signal input to the previous circuit block to 1 A logical product gate and a logical sum gate for inputting a clock signal divided by 2 and an output gate for selectively outputting one of the logical product gate and the logical sum gate based on the control signal input to each. And a pulse based on a combination of the control signals input to each of the plurality of circuit blocks from the last circuit block. There pulse generating circuit, characterized in that generated as outputs the control pulses.