JPH0630438B2 - Pulse generator - Google Patents

Description

The present invention relates to an improvement of a pulse generation circuit that outputs a serial pulse signal having a predetermined number of pulses.

[Prior Art] As a conventional pulse generator, there is a pulse generator which outputs a set number of serial pulse signals at a constant frequency when the number of output pulses is set by a microprocessor.

[Problems to be Solved by the Invention] However, in such a pulse generator, since the frequency of the output pulse signal is constant, the output signal becomes a burst pulse signal as shown in FIG. Therefore, if the receiving side of the output pulse is, for example, a drive circuit of the pulse motor, there arises a problem that the rotation of the pulse motor is not smooth.

Also, the time when the pulse generation ends is determined by the number of generated pulses. Therefore, the time when the pulse generation ends cannot be changed. As a result, there is a problem in that it cannot cope with changes in the pulse generation period.

The present invention has been made to solve such a problem, and it is possible to output a smooth serial pulse signal in which pulses are evenly arranged over the entire period, and moreover, the pulse generation end time can be easily changed. The purpose is to realize a generator circuit.

[Means for Solving Problems] According to the present invention, the number of pulses generated in one cycle is set, counting is performed every time an input pulse signal is given, and a count-up signal is output when a set value is counted. The counter, the number of pulses generated in one cycle, and the pulse cycle corresponding to the number of pulses are stored in association with each other, and the number of pulses is stored in the ROM.
When the set value is given to the counter, the address determined by the given set value is given, and the data of the pulse cycle stored at this address is read out, and this ROM A first flip-flop for latching and outputting the data read from, a full adder for introducing the output of the first flip-flop, and an addition value of the full adder are latched by a predetermined block signal. A second flip-flop is provided, the output of the second flip-flop is fed back to the full adder, and the full adder adds the outputs of the first flip-flop and the second flip-flop. , The added value is latched by the second flip-flop, and when the latched added value exceeds a predetermined value, the second flip-flop outputs a carry signal. And a DDA circuit for generating a count-up signal. The carry signal is passed before the counter generates a count-up signal, the serial pulse signal is output by the carry signal passed, and the input pulse signal is applied to the counter. When a count-up signal is generated, the pulse generation circuit includes: a pulse prohibition circuit that prohibits passage of a carry signal and terminates the output of the serial pulse signal.

[Examples] The present invention will be described below with reference to the drawings.

FIG. 1 is a configuration block diagram of an embodiment of a pulse generating circuit according to the present invention.

In FIG. 1, 1 is a counter, for example, a down counter,
The number of pulses generated in one cycle is set, and it counts down every time an input pulse signal is given, and the count is 0.
Then, the count-up signal CU is generated.
This counter is, for example, an 11-bit counter. The set value is given by the output pulse number setting data buses D0 to D7. This bus carries 8-bit data.

PLOADL and PLOADH are lower byte load signal and the upper byte load signal, since the counter 1 transmission data is 8-bit data of the data bus D0～D ₇ is 11-bit counter, the lower byte and upper byte of the set value data Is a signal used for causing the down counter 1 to read in a time division manner. The set value and the PLODL and PLOADH signals are provided from a microprocessor (not shown).

Reference numeral 2 is a selector using a flip-flop in which 1-bit data is set, and the most significant bit of the PLOADH signal is set by the bus D7. The selector 2 generates an up pulse or a down pulse depending on the content of the set bit. When the pulse receiving side is the pulse motor drive circuit, the rotation direction of the pulse motor is determined according to the up pulse and the down pulse.

A memory 3 stores data corresponding to the set value at an address determined by the set value of the down counter. An external ROM or the like is used as the memory 3.

A sequencer 4 operates at the timing given by the clock input CLOCK1, and the set value is set in the down counter 1 based on the level of the PLOADH signal.
Is made accessible and the address determined by the set value is sent to the memory 3 using the address buses RA0 to RA12.

5 is the first flip-flop, 6 is the full adder 7 is the second
Flip-flop of DDA (Dig
It constitutes an iterative differential adder circuit.

The first flip-flop 5 latches and outputs the data read from the memory 3. This flip-flop latches 12-bit data.

The data buses RD0 to RD7 are used to transmit the data read from the memory 3. This bus carries 8-bit data.

RA1 to R of the address buses connected to the memory 3
The set value of the down counter 1 is transmitted by the transmission signal of A11. The data to be read is the transmission signal of the bus RA0
It is designated whether the data to be latched in the first flip-flop 5 is the upper byte or the lower byte. The transmission signal of the bus RA12 specifies whether the read data corresponds to an up pulse or a down pulse.

DLATCH and ULATCH are an adder initial value lower byte load signal and an adder initial value upper byte load signal, the first flip-flop 5 latches 12-bit data, and the data buses RD0 to RD7 are 8-bit data. Is used to latch the lower byte and the upper byte of the initial value in the first flip-flop 5 in a time division manner. ULATC
The sequencer 4 generates the H signal and the DLATCH signal.

The full adder 6 receives the output of the first flip-flop 5 and outputs the added value to the second flip-flop 7
Give to.

In the second flip-flop 7, the added value of the full adder 6 and the clock signal CL that has passed through a pulse inhibition circuit described later
OCK1 is input. The second flip-flop 7 latches the added value of the full adder 6 at the timing of CLOCK1 and feeds back the added value to the input section of the full adder 6. The second flip-flop latches 12-bit data.

The full adder 6 adds the outputs of the first flip-flop 5 and the second flip-flop 7, and gives the added value to the second flip-flop 7. The second flip-flop 7 generates a carry signal (pulse signal) F every time the most significant bit of the latched data changes. This carry signal F becomes the output signal of the DDA circuit.

The pulse frequency of CLOCK1 is set higher than the frequency at which data is latched in the first flip-flop 5.

Reference numeral 8 denotes a pulse prohibiting circuit, which passes the carry signal F to the down counter 1 and the selector 2 before the down counter 1 generates the counter up signal, and passes the carry signal F when the count up signal is generated. Disable and end the output of the serial pulse signal.

An error detection circuit 9 is provided with a signal PLOADL and a signal S depending on the presence / absence of a state response from the pulse inhibition circuit 8, and based on these signals, a new pulse number is added to the down counter 1 during the generation of the serial pulse. When is set, an error signal ERROR is generated.

Next, the operation of such a pulse generating circuit will be described.

FIG. 2 is a time chart of each signal of the circuit of FIG.

In the figure, PLOADH, PLODL, ROMOE, UL
The signals ATCH and DLATCH are low active signals.

That is, PLOADH, PLOADL, ULATC
The H and DLATCH signals are read at the timing of rising from the low level to the high level, and the ROMO
When the E signal becomes low level, the memory 3 is enabled.

The number of pulses generated in one cycle is set in the down counter 1 by the PLOADH signal and the PLOADL signal from the microprocessor, and is the most significant bit of the set value of the pulse direction determination bit (up pulse and down pulse determination bit). The contents are selector 2 by data bus D7.
Is set to. As a result, the selector 2 outputs a signal corresponding to the up pulse or the down pulse to the address bus RD.
12 to the memory 3.

After setting the PLOADH signal, sequence 4
Starts to read, the initial value of the full adder 6 is read from the memory 3 using the set value of the down counter 1 as an address,
Set it in flip-flop 5 of. When the setting is completed, the pulse prohibiting circuit 8 allows CLOCK1 to pass and the second
To flip flop 7. As a result, the full adder 6 starts to move.

The second flip-flop 7 latches the output of the full adder 6, that is, the added value of the first flip-flop 5 and the second flip-flop 7 in the cycle of CLOCK1.
The second flip-flop 7 generates a carry signal F each time the most significant bit of the latched output changes. The carry signal F becomes an up pulse signal or a down pulse signal and becomes a signal counted by the down counter 1.

When the down counter 1 generates a count up signal,
The pulse prohibiting circuit 8 prohibits the passage of CLOCK1 and outputs the second pulse.
No more to give to flip flop 7. As a result, the second flip-flop 7 does not generate the carry signal, and the generation of the serial pulse signal ends.

When the error detection circuit 9 sets a new pulse number in the down counter 1 during generation of a serial pulse, an error signal ERROR is generated.

In the embodiment, when the number of output pulses is set in the down counter 1, the set value of the first flip-flop 5 is constant until the next setting, but the present invention is not limited to this.
The set value of the flip-flop 5 may be changed according to the count of the down counter 1.

That is, in the embodiment, when the number of output pulses is set in the down counter 1, the set value of the first flip-flop 5 is constant until the next setting, so the increase rate of the added value of the full adder 6 Is constant. Therefore, the frequency of generation of the carry signal is also constant, and as shown in FIG. 3, the pulse rate of the serial pulse output is constant between the set times. In FIG. 3, t ₀ , t ₁ , t ₂ , t
₃ is the timing for setting the number of output pulses.

Therefore, the setting of the data in the first flip-flop 5 is not limited to the setting of the number of pulses in the down counter 1, but the count of the down counter 1 may be appropriately performed as a parameter. As a result, as shown in FIG. 4, the pulse rate of the serial pulse output changes in a curve. This makes it possible to distribute the pulses more finely and evenly.

Further, as shown in FIG. 5, a circuit including the full adder 6 and the second flip-flop 7 may be connected in series in plural stages. When connected in series with n stages, the added value of the adder changes with an nth-order function.

Further, as the counter 1, an up counter may be used instead of the down counter.

Further, the number of bits of signals handled by the down counter 1, the first flip-flop 5, the full adder 6, the second flip-flop 7, and each bus may be other than the numbers shown in the embodiments.

An example of using the pulse generating circuit according to the present invention is shown in FIG.

In FIG. 6, D is a direct drive motor that directly drives a drive target without passing through a speed reducer, C is a drive / control circuit that drives and controls the direct drive motor C, and P is a drive circuit.
Is a positioner that gives a command value signal of the rotation speed and the rotation position of the motor to the drive / control circuit C.

The pulse generation circuit C _{1 according} to the present invention provided in the drive / control circuit C slips the pulse signal of the existing value of the rotational position or the rotational speed of the direct drive motor D provided from the microprocessor C _2. It is given to the counter P _{1 of the} positioner P.

The pulse generating circuit P _{2 according} to the present invention provided in the positioner P slips the command pulse signal calculated by the microprocessor P ₃ and supplies it to the counter C ₃ of the controller C.

With such a configuration, both the current value pulse signal and the command pulse signal can maintain continuity, so that it is not necessary to perform the synchronization processing between the microprocessors C ₂ and P ₃ .

[Effect] According to the present invention, the optimum initial setting value of the DDA circuit is read from the memory with the number of pulses generated in one cycle as a parameter, and the DDA circuit serial pulse is output based on this initial setting value. Therefore, it is possible to output a smooth serial pulse in which the pulses are evenly arranged over the entire period.

Further, when the number of output pulses and the set period of the output pulse are in one-to-one correspondence, the pulse generation end time can be set by software by properly using a plurality of types of memories that store different correspondences.

Further, the ROM stores the number of pulses generated in one cycle and the pulse cycle corresponding to the number of pulses in association with each other. The number of pulses is the ROM address.

When the set value is given to the counter, the address determined by the given set value is given to the ROM, and the pulse cycle data stored at this address is read.
Therefore, when the number of output pulses is set in the counter, the cycle of output pulses is also determined.

As described above, the data stored in the ROM determines the number of output pulses and the period in association with each other. Since the ROM is external to the pulse generation circuit, it can be replaced.

Therefore, the pulse generation end time can be changed by software by properly using a plurality of types of memories having different correspondences between the output pulse number and the output pulse period. As a result, when the pulse generation cycle is changed,
Accordingly, the pulse generation end time can be easily changed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a pulse generation circuit according to the present invention, FIG. 2 is a time chart for explaining the operation of the circuit of FIG. 1, and FIGS. 3 and 4 are pulse generation according to the present invention. FIG. 5 is a diagram showing a change over time in the output pulse rate of the circuit, FIG. 5 is a diagram showing another configuration example of the circuit according to the present invention, and FIG. 6 is a use example of the pulse generation circuit according to the present invention. Figure,
FIG. 7 is a time chart of the output signal of the conventional pulse generation circuit. 1 ... Counter, 3 ... Memory, 5 ... First flip-flop, 6 ... Full adder, 7 ... Second flip-flop
The flop.

Claims (1)

[Claims] 1. The number of pulses generated in one cycle is set, and counting is performed every time an input pulse signal is given,
The counter that outputs a count-up signal when counting only the set value, the number of pulses generated in one cycle, and the pulse cycle corresponding to the number of pulses are stored in association with each other.
When the set value is given to the counter, the address determined by the given set value is given, and the data of the pulse cycle stored at this address is read out, and this ROM A first flip-flop for latching and outputting the data read from, a full adder for introducing the output of the first flip-flop, and an addition value of the full adder is latched by a predetermined clock signal. A second flip-flop is provided, the output of the second flip-flop is fed back to the full adder, and the full adder adds the outputs of the first flip-flop and the second flip-flop. , The added value is latched by the second flip-flop, and when the latched added value exceeds a predetermined value, the second flip-flop outputs a carry signal. And a DDA circuit for generating a count-up signal. The carry signal is passed before the counter generates a count-up signal, the serial pulse signal is output by the carry signal passed, and the input pulse signal is applied to the counter. A pulse generation circuit comprising: a pulse prohibition circuit that, when a count-up signal is generated, prohibits passage of a carry signal and terminates output of a serial pulse signal.