KR890006187Y1 - Data recording circuits of video ram - Google Patents

Abstract

No content.

Description

Video RAM Data Writing Circuit

1 is a block diagram of the present invention.

2 is a detailed circuit diagram of the present invention.

3 is a waveform diagram of the main part of FIG.

* Explanation of symbols for main parts of the drawings

1: latch portion 2: address generator

3: control unit 4: driving unit

5: Memory 11-13: Latch

21-26: counter 31,32: flip-flop

41,42: Line Driver 51: Video RAM

52: Andgate

The present invention relates to a circuit for writing data displayed on a motor to a video RAM.

In the related art, since a system is configured to control information displayed on a monitor by software, that is, the position of the monitor to be displayed, information about the data to be deleted and the quantity of the deleted data by software, the displayed processing speed is not fast.

Especially when displaying and deleting a large amount of processing data from a computer on a monitor, it was very late.

Therefore, an object of the present invention is to provide a circuit that consists of hardware, rather than software, that writes data displayed on a monitor to video RAM in order to increase the processing speed of the system.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of the present invention, and the latch unit 1 is synchronized with the address signals AL and AH and the counter synchronizing signal CTK output from the central processing unit (hereinafter referred to as CPU) of the main system. A circuit for temporarily storing -D7) and the address generator 2 loads the output signal of the latch unit 1 in synchronization with the character generation synchronization signal CCK output from the CRT controller of the main system. The control unit 3 generates a control signal for counting down the data input to the latch unit 1 and sending an interrupt request signal IRQ to the CPU and stopping the address transfer at the time of becoming 0. It is a circuit.

The driver 4 is a circuit driven by an output signal of the controller 3 to transmit an address output from the address generator 2, and the memory 5 is monitored by an address applied through the driver 4. The circuit writes the data FD0-FD7 displayed on the screen.

The detailed circuit of the present invention configured as described above is shown in FIG.

In Fig. 2, the latches 11-13 for applying data D0-D7 transmitted from the main system are the counter synchronization signal CTK, the lower address signal AL, and the upper address signal output from the CPU of the main system. When the counter 22 is synchronized to (AH), and counts down at the counters 21 and 22 that apply 4 bits each to the 8-bit signal output from the latch 11, the counter 22 The signal output from the output terminal TC is applied to the input terminal D of the flip-flop 31, and is applied to the interrupter terminal of the CPU (not shown in the figure) output from the flip-flop Q and at the same time the data write synchronization is performed. It is applied to the reset terminal R of the flip-flop 32 which is synchronized by the signal FCK.

The counters 23 and 24 that apply four bits of the eight-bit output signals of the latch 12 each counter up to apply the 8-bit lower address signal outputted to the line driver 41. The counters 25 and 26 applying four bits of the 8-bit output signal of (13) each counter up, so that the 4-bit signal of the counter 25 and the 2-bit signal of the counter 26 are 6-bit upper address signals. It applies to the line driver 42, the line driver 41, 42 is enabled as a signal of the output terminal (Q) of the flip-flop 32, the 14-bit address signal inputted to the address of the video RAM 51 It is applied to terminals A0-A13 and the video RAM 51 is enabled by the logical AND product of the character generation synchronization signal CCK and the data write and read signal R / W at the AND gate 52 for monitoring. Stores the data (FD0-FD7) displayed on the screen.

In the video writing circuit of the video RAM of the present invention having the above-described configuration, a circuit operation for processing hardware by writing data displayed on the monitor to the video RAM will be described based on the waveform diagram shown in FIG.

When information on the number of data to be stored in the video RAM 51 is applied through the data bus of the main system, the latch is generated when the counter sync signal CTK output from the CPU of the main system is a logic "0" (low level) signal. (11) is synchronized to latch the applied data, and then, when the lower 8 bit signal of the start address to be assigned to the video RAM 51 is applied through the data bus, the latch when the lower address signal AL is a logic "0" signal. In addition, when the upper address signal AH is logic " 0 ", the upper 8-bit address signal applied through the data bus is applied to the latch 13.

The data FD0-FD7 to be displayed on the monitor is a character generation synchronization signal CCK output from the CRT controller (not shown) while being applied to the video RAM 51 through the port of the main system. Whenever is reduced to the logic " 0 " signal, the counter counts down by one from the counts 21 and 22 which have loaded the output data of the latch 11.

At the same time, the 14-bit address signals A0-A13 generated by counter-up one by one from the counters 23-26 which have loaded the output data of the latches 12, 13 are inputted through the liner 41, 42. When applied to 51, the data FD0-FD7 to be displayed corresponding to the designated address is written in the video RAM 51.

As shown in the above operation, each time the character generation synchronization signal CCK falls to a logic " 0 " signal, the control counters 21 and 22 count down, and the address generation counters 23-26 are countered up to video. The address applied to the RAM 51 is incremented by one so that eight bits of data FD0-FD7 are sequentially written to the video RAM 51.

This operation is continued until the data loaded into the control counters 21 and 22 is counted down to "0". When the value is "0", the logic "0" signal ( 3a) is outputted to the flip-flop 31 and a logic "0" signal appears at (Q) of the flip-flop 31 to reset the flip-flop 32.

At this time, a logic " 1 " (high level) signal (FIG. 3b) is output to the output terminal Q of the flip-flop 32 to control the line drivers 41 and 42 to output the address signals from the counters 23-26. To not be applied to the video RAM 51.

At the same time, since the interrupt signal IRQ of the CPU of the main system is applied, the video RAM 51 is notified of the completion of data writing.

As described above, in the present invention, writing data to be displayed on the monitor to the video has an advantage of improving the processing speed of the system because the hardware is configured.

Claims (1)

A latch unit 1 which is synchronized with the address decoding signals AL and AH provided from the CPU of the main system and the counter synchronizing signal CTK and temporarily stores the data D0-D7 applied through the data bus of the main system. ) And the latch generator 1 and the address generator 2 for generating an address by loading the output signal of the latch unit 1 in synchronization with the character generation synchronization signal CCK provided from the main system CRT controller. Drive by the output signal of the control unit 3 and the control unit 3 which counts down the data input from the control unit and generates an interrupt request signal IRQ and a control signal that emphasizes address transmission when the data becomes " 0 " The driver 4 for controlling the transmission of the address output from the address generator 2 to the video RAM 51 and the address applied through the driver 4 are designated and displayed on the monitor. Data (FD0-FD7) a data write circuit of the video RAM, characterized in that consisting of the storage unit (5) for writing.