SU873396A1 - Regulated delay device - Google Patents

Description

   . The invention relates to a pulse technique and can be used for the formation of time intervals in devices of pulsed radio communication, radionavigation, telemetry, in various timing schemes, in studies in nuclear physics, etc. A quantized delay device is known that contains two counters, a bitwise comparison unit, a coincidence element and a prohibition element 1. A disadvantage of the device is the limited discretization value of time interval control and the instability of the value of the generated time delay when exposed to an asynchronous start signal, which are determined by the clock frequency period. The closest L to the proposed device is a device containing an ELECTRICALLY element or, an installation counter and a control trigger 2. The drawbacks of the device are the large discreteness of the regulation of the time interval determined by the clock pulse (t;) period coming from the external generator and the amount of instability of the formed time delay when exposed to an asynchronous start signal, the maximum magnitude of which is also determined by the period of the clock pulses ( B) The purpose of the invention - reduction of the discreteness of the control slot and to increase its stability. To achieve this goal, a descrambler, N delay elements, N logic elements OR n (N + 1) logic elements AND are entered into the adjustable delay device, which contains the control trigger, the setting counter, and the input of the device is connected to the installation input of the control trigger unit and with the first inputs of N-logic elements AND, whose inputs are connected with the outputs of the depotfrarator, and the outputs with the first inputs of the corresponding OR elements, the output of the control trigger is connected to the recording input of the installation counter a and to the first input (N + D-oro of an AND logical gate, the output of which is connected to the second input of the first OR logical element, the output of the latter is connected

with the input of the first delay element, the output of which is connected to the second input of the second logical element OR, the output of the latter is connected to the input of the second delay element, etc., the output of the N-oro delay element is connected to the counting input of the installation counter and to the second input (N + l) -oro of the logic element I, and the inputs of the decoder and information inputs of the installation counter are connected via the register PsNo 4 to the write buses, the output of the installation counter is connected to the input of the installation zero of the control trigger and the output of the device.

The drawing shows a structural diagram of the proposed device adjustable delay.

The device consists of a control trigger 1, the output of which is connected to the first input (N + l) -oro of the logic element AND 2, the output of which is connected to the second input of the first of the N-logical elements OR 3, and the outputs of the latter are connected to the inputs of the corresponding delay elements 4 of the installation counter 5, the counting input of which is connected to the output of the N-oro delay element and to the second input {N + l) -oro of the logical element I, and the recording input to the output of control trigger 1, the decoder 6, whose outputs are connected to the second inputs of N logical elements And, and output dy with memory register 7 connected 1 also to the write counter of the installation counter, input 8 of the device connected to the installation input of the control trigger unit and the first inputs N of logic gates AND, the outputs of which are connected to the first inputs of the corresponding logic elements OR, output 9 the device associated with the installation input of the control trigger zero and the output of the installation counter, write buses 10, connected to the inputs of the memory register.,

The adjustable delay device operates as follows.

In the initial state (until the trigger signal arrives at the device 8 input), control trigger 1 is in the zero state, blocking the first input element (Y + 1) -th logic element I 2 and setting counter 5 at the recording input. The decoder 6 blocks in the second inputs, all N logical elements AND 2 except for one, whose number is determined by the code present on the inputs of the decoder 6. In addition to the information inputs of installation counter 5, there is a code I identifying number to be written to the counter. In the register. Memory 7 is written on the write bus 10 number corresponding to the specified delay value. At the moment when the trigger pulse arrives at the input 8, the control trigger 1 switches to one state, unlocks the (L + 1) -th logical element AND 2 and the setting counter 5, into which from the memory register 7 a number is written. At the same time In this case, the triggering pulse passes through one of the N logical elements AND 2, the second input of which does not contain the prohibition signal from the decoder b, and arrives at the first input of the corresponding logical element OR 3. Then this pulse passes through subsequent successively connected alternating logical elements OR 3 and delay elements 4, as well as through the unlocked (YI) -th logical element I. Next, the pulse circulates around the ring formed by the logical elements OR 3, the delay elements 4 and (Y + 1) -s logical e ementom and 2. At the output of N-oro delay element is generated by a sequence of clock pulses, the repetition period of which is determined by the total value of the delay elements of the ring. The moment of occurrence of the first clock pulse at the counting input of the installation counter 5 is determined by the delay time of the pulse from the logical element OR 3 associated with the corresponding unblocked decoder 6 logic element 2 to the output of the N-oro delay element. The counter begins to count clock pulses, and when their number coincides with the number written into the installation counter, it is set to the zero state. At the output of the counter, a signal is delayed relative to the triggering pulse, which is fed to the output 9 of the adjustable delay device and to the setup input of control trigger 1, which switches to the initial state, blocking the installation counter 5 and (Y + 1) logic element AND The device returns to its original state. condition.

The total value of the formed delay time interval is defined as.

.. To5y T, + TSts .. (1

de T

the initial value is delayed. ki, determined by the time of the trigger pulse passing through the delay circuit from the logical element OR, connected with the unlocked decoder logical AND element, to the output; c1 N-oro delay element;

Claims (2)

the value of time inter s. the shaft formed by the adjusting counter. In this Tns1h. K / TI + Ta + Tj where T is the value of the time delay determined by the delay element; T - the value of the time delay introduced by the logical e; | emen volume OR; T is the value of the time delay introduced by (N + 1) -th logical element AND, Kr1,1, ..., M is the number of delay elements and logical elements OR, which pass the start pulse before it arrives at the counting input of the installation counter. With a good degree of approximation, it can be considered that the magnitude of the initial delay is 404. K t ,. - (3) The value of the time interval formed by the installation counter Tc-c. m. TO, (4) where, l, ..., M is the number recorded in the installation counter; Tr is the repetition period of the generated clock pulses, which is equal to TO N / T + T, H– T ;, (5) + T. Thus, the value of the formed delay time interval of the proposed device is equal to Toby K. T + m. T, In the known device, the time interval interval time is defined as t T - + U T I L T, where TO is the clock period; L T is the instability of the time interval formed, determined by the asynchronous occurrence of the trigger pulse relative to the clock pulses. From the formula (6) and (7) it can be seen that with the equality m TO m. TO. (8) in the proposed device, an additional adjustment of the formed time interval (see formula 5) with discreteness T, | L. (9) Consequently, in the proposed adjustable delay device, the control resolution is reduced by N compared to the known device. ; From the principle of operation of a known device, it follows that the maximum Be is the degree of instability of the formed, time interval DT (in formula 7) under asynchronous influence for-; the trigger pulse is LT tA. 2) (7) (10) In the proposed device, such an error is excluded, since the moment of the beginning of the formation of the time interval is always rigidly connected with an arbitrary moment of the appearance of the trigger pulse, which passes through the decoder unlocking the logical element AND, arriving at a certain point of the ring. Therefore, the proposed device forms time intervals that have a much greater stability than the known device. The greatest effect from the application of the proposed device is achieved when forming time intervals of the nanosecond range. In this case, it is advisable to use integrated circuits as delay elements. Claims of the invention A variable delay device comprising a control trigger, a setting counter, a memory register, characterized in that, with the aim of reducing the discreteness of adjusting the time interval and increasing its stability, a decoder, N lock elements, N Logical elements OR and ( N + 1) logic gates And, with the device input connected to the installation input of the control trigger unit and the first input N logic gates And, the second of which are connected to the outputs of the control panel, and the outputs to the first In the odes of the corresponding OR elements, the output of the control trigger is connected to the recording input of the installation counter and to the first input (N + l) -oro of the AND logic gate, the output of which is connected to the second input of the first OR logic element, the output of the last one is connected to the input of the first element delay, the output of which is connected to the second input of the second logical element OR, the output of the latter is connected to the input of the second delay element, etc., the output of the N-oro delay element is connected to the counting input of the installation counter and to the second go (N + l) -oro AND gate, and inputs and data inputs of the decoder adjusting counter coupled through the register memory with a recording tires mounting counter output coupled to the input for setting zero trigger control and output device. Information sources, . taken into account during the examination 1. USSR author's certificate 639132, cl. H 03 K 5/13, 28.12.73. 2. Japanese Patent 52-36669, per owner. 08.12.72, No. 47-123245, cl. 98/5 / C22, H 03 K 5/153, published. 17.09.77 (prototype).