SU792570A1 - Single pulse shaper - Google Patents

Description

The invention relates to a pulse technique and can be used to normalize time intervals of a given duration. Known driver single pulse containing the elements AND, OR OR NOT, two trigger and adjustable delay device l. The disadvantage of this device lies in the fact that the duration of the pulse at the output is determined by the parameters of the delay line and cannot be controlled by software. The closest technical solution to the invention is a single pulse shaper, which contains a clock pulse generator whose output is connected to the inputs of the first and second elements AND, the second inputs of which are connected to the trigger outputs, to the inputs of which control signals are fed directly and through an inverter, the trigger of the permission and the trigger of the prohibition of the passage of pulses, the inputs of which are connected through the inverter to the output of the first element I, and the outputs to the inputs of the third and fourth elements I, the second inputs of which s connected to the output of the second AND gate 2. A disadvantage of this device is the large delay time of the output pulse relative to the control; its signal during the formation of duration pulses and the small range of control of the pulse duration at the output of the fop 1 and the transducer. The purpose of the invention is to reduce the delay time and expand the range of control of the duration of the output pulses. To do this, the shaper containing the clock, the inhibit trigger, the enable trigger, the first and second AND elements, an additional decoder, a frequency divider, additional AND elements, the first and second OR elements, and the output of the first OR element are simultaneously connected to a single trigger input prohibition and rep. the input of the first and second elements And whose outputs are connected respectively to the zero and counting inputs of the frequency divider and the second inputs to the output of the clock generator and to the output of the inhibit trigger connected by the counting input to the output of the clock generator and zero input with the trigger output

the permissions, the outputs of the frequency divider are connected to the second inputs of the additional AND elements, the outputs of which are connected to the counting input of the resolution trigger via the second OR element, and the first inputs are connected to the decoder outputs and the inputs of the first YAN element. ,

The device contains a decry frequency generator 1, a frequency divider 2, additional elements AND 3, the first and second elements OR 4 and 5, the resolution trigger b, the prohibition trigger 7, the first and second elements 8 and 9, and reiiepaTop 10 clock pulses.

The drawing shows a block diagram of the device.

In the initial state, when the zero code arrives at the input of the decoder 1, the single potential input of the enable trigger 6 and the control input of the inhibit trigger 7 receive the zero potential, which sets the trigger 6 to single, and the trigger 7 goes to the zero state. In this case, the elements 8 and 9 are locked, the divider 2 is set to the zero state and the output of pulses from the generator output of 10 clock pulses to the input of the divider 2 is stopped.

When issuing to the input of the decoder 1 any other code, a single potential input of flip-flop 6 to the control input of flip-flop 7 and the second input of elements AND 8 and 9 through the first element OR 4 receives a high potential. At the same time, elements 8 and 9 are opened, trigger 7 is set by a clock pulse in one state, divider 2 becomes operational, and at the output of element 8 is formed the leading edge of the output single pulse, the duration of which is specified by the input command using divider 2. The formation of the leading edge takes place immediately after the command is received by the first clock pulse. A trigger of 7 seconds maintains its state until high levels coincide with the output of the decoder 1 and divider 2 at the input of the corresponding IZ element.

With the introduction at the output of the second element or 5 high potential, the trigger b is set to the zero state, which leads to the establishment of the trigger 7 to the zero state, the AND 8 elements are blocked, the front edge of the output pulse is formed, the divider 2 is set to zero and the device in the initial state.

When the input code is changed, similarly, at the output of the device, single pulses of another required

duration, and the device provides for the formation of a single pulse of a different duration only when there is a short pause between the commands, which is necessary for setting trigger b to one state. In addition, the formation of the output pulse occurs immediately after the arrival of an input command from the leading edge of the clock pulse. This makes it possible to reduce the delay time of the output pulse relative to the input pulse up to the value of the period of the master oscillator, which can be shortened, since the duration of the output pulse mainly depends on the division ratio of the divider.

The use of the device makes it possible to shorten the delay time of the output pulse relative to the control signal and provides a wide range of programmed control of the duration of the output single pulse.

Claims (2)

1. Author's certificate of the USSR W 463230, cl. H 03 K 5/153, 1972. 2. USSR author's certificate number 515262, cl. H 03 K 5/18, 1975.