SU764111A1 - Pulse delay device - Google Patents

Description

I

The invention relates to a pulse technique and can be Hcnoj # 3pBaHo in communication systems, in radio-insulating, measuring and computing equipment.

A device for delaying pulses is known, which contains working and control counters, census gates, a census generator, a starting generator, and triggers Ts. The specified device has insufficient accuracy of the delay.

The aim of the invention is to improve the accuracy of the delay.

To achieve this goal, a pulse delay device containing work and control counters, census gates connected between the serial outputs of the control and work counter inputs, a census generator whose output is connected to the second inputs of the census gates, the starting generator, direct output which through the valve connected by the input to the output of the first trigger, is connected to the input of the working counter, the output of which is connected to the input of zero installation of the first trigger, input

the census generator and the second trigger input, an exact delay block is inserted, containing a frequency divider, the bit outputs of which are indirect output of the trigger generator connected to the inputs of the matching elements, outputs connected to the RS trigger inputs, the output of which, as well as the inverse output of the trigger generator and trigger the second trigger is connected to the inputs of the coincidence element, the output of which is connected to the second input of the second trigger.

FIG. 1 shows a functional diagram of the device; in fig. Figure 2 shows the time diagrams for how the device works.

The device consists of blocks of coarse I and

15 exact n delay. The coarse delay unit has a work counter that controls the reversible counting machine 2, census gates 3, valve 4j trigger 5, census generator 6. The outputs of counter 2 are connected to census gates,

20 unlocked pulses of the census generator. The output of the starting crystal oscillator 7 is connected to the valve 4, unlocked by the trigger 5, the signal of which is combined in time with

376

one of the counting pulses of the generator 7. The output of the work counter 1 is connected to the input of the zero setting of the trigger 5, the input of the census generator 6 and the input of the trigger 8, in which information about the coarse delay is written. The switch 9 is connected to the addition or subtraction inputs of counter 2. The exact delay unit consists of frequency divider 10, coincidence element 11, gates 12, RS flip-flop 13. At the lower bits of the frequency divider, RS 12 triggered control signals are generated single and zero inputs. The trigger output is connected to the input of the matching element. The inputs of the element 11 are also connected to the output of the generator 7 and the trigger 8. The element 11 selects a pulse of a precise delay.

The number Np with the help of gates 3 unlocked by the census pulse f (Fig. 2) is rewritten into work counter 1. A pulse b, synchronized in time with one of the counting pulses a, overturns the starting trigger 5, the pulse from which unlocks the gate 4. Counting impulses a begin to flow into the work counter, increasing its readings from Mp. The counting comes from the overflow of the working counter, coming with the arrival of the nth counting pulse: (Nn) + n N. In this case, all bits of the working counter, including the most significant one, overturn to the zero state. . He is detained for starting at the time

B bn + & tma№.O)

The impulse e is applied simultaneously on the trigger of trigger 5, the delivery of counting pulses is stopped to start the generator 6 of the rewriting impulse, the impulse f of which provides a new entry in the working counter of the ike (or changed) number N-n; and to the input of the trigger 8, as a result of which the latter remembers the value of the coarse delay.

.In the process of forming coarse. Software delays; signal: | m from the generator 7 and from the lower bits of the Divider frequency 10 on the valves 12, the pulses h and i are formed, controlling the trigger 13 on the inputs of the installation 1 and О, respectively. As a result, the signal from the output of the trigger 13 is synchronized with the counting pulses in such a way that the leading edge of these pulses coincides with the midpoint of the pulses k.

The first pulse after pulse e, gated by pulse k, is released as pulse 6 on element 11. At the same time, pulse t arrives at the input of setting O of trigger 8 and the device returns to its initial state. Since the repetition period of strobe pulses k is equal to 2 tons, a switch 14 is introduced to obtain a smooth step delay, varying with quantum r, which alternately switches the zero point of the delay. The total delay is determined by the formula

t.j pg -I- kr, (2)

where K 2, 4, 8, ... is a coefficient depending on the speed and the number of bits of the working counter involved in the formation of the delay.

The term kr A can be called the lead interval. It is subject to the condition

A b

(3)

T mate.

It is not difficult to see in FIG. 2 that the pulse t delayed by time 1 has an error De equal to only the on time of element 11, and the parasitic delay is. is quenched in the interval between the last coarse delay pulse e and the first fine delay pulse. However, a very small and significant delay of DCs can be compensated for by the introduction of an inverter into the zero channel L, which results in the accuracy of forming the total delay to the potential, i.e. determined only by the stability of the quartz oscillator.

Claims (1)

Claims A pulse delay device containing work and control counters, census gates, connected between the serial outputs of the control and the inputs of the work counters, a census generator whose output is connected to the second inputs of the census gates, which triggers the generator, whose direct output through the valve, connected by the input to the output of the first trigger, is connected to the input of the working counter, the output of which is connected to the input of the zero setting of the first trigger, the input of the census generator and the input of the second An igger, characterized in that, in order to increase the delay accuracy, an exact delay block is inserted into it consisting of a divider, frequencies whose bit outputs and the direct output of the trigger generator are connected to the inputs of the coincidence elements, the output 1 of which is connected to the RS inputs a trigger, the output of which, as well as an inverse output, starts up a generator; to the output of the second trigger is connected to the inputs of the element, a match whose output is connected to the second input of the second trigger. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 295194, p. H 03 K 5/153, 09/26/69.