SU860052A1 - L-bit word encoder - Google Patents

Description

The invention relates to automation and computing and can be used to convert a spatial unitary code into a binary code. A coder is known that contains multiple input OR elements whose inputs are connected to the inputs of encoder 1. The disadvantage of such a converter is the large amount of hardware and the irregularity of the connections. The closest to the proposed technical essence and circuit design is an encoder containing sequentially connected encryption stages consisting of OR elements, the input of the first encryption stage being the encoder input, and the output of the last encryption stage and the group of outputs of each encryption stage are outputs Encoder And A disadvantage of this encoder is the relatively large amount of hardware and low speed. The purpose of the invention is to reduce hardware and improve the speed of the encoder. The goal is achieved by the fact that in the encoder 6-bit words containing sequentially connected ciphering stages consisting of OR elements, the input of the first ciphering stage being the input of the cipher, and the output of the last ciphering stage and output group of the ciphering level of coding are outputs the encoder i is the encryption stage Cl - C) / where And -2, and 6 is the number of bits of the output word, K-2, contains the first group of - K-input elements OR, the second group of, K-input elements. OR and K-input additional encoder, the inputs of which are connected to the outputs of the OR elements of the second group, and the outputs are the outputs of the i -th encryption stage H ((- ii) (4 (-f - i) bits of the encoder outputs, and the last the encryption stage also contains an I-2 input additional encoder (where w is the number of stages encryption), whose inputs are connected to the outputs of the OR elements of the first group, and the outputs are outputs (wp 4 Cogg M) of the encoder bits, -jth input H -th element OR the second group of the t-th step of the stem ((q, -14K), (hm) is connected to the q, -th input of the j-th element IL The first group at the encryption stage and with the input of the (j -vj) element OR of the first group (d-1) -th encryption stage, -) -th input q, -th element OR of the second group of the first encryption stage is connected to cj , -th input of the j-or element of the OR of the first group of the first encryption stage and with R ((1} n-1 /. + J) -th input of the encoder. In Fig. 1, a functional diagram of the / 1st encryption stage is shown; FIG. 2 - the same, 1st encryption stage, in FIG. 3 - the same, the last stage. The proposed encoder contains m encryption steps. Each i-stage (Fig. 1) includes p / K-input circuits divided into K groups 1.1 (index i For numbers, blocks means that the described block belongs to the i-th stage), К. The n / K input elements OR 2.1, the elements OR 3 K are input encoder 4. The input circuits of the first encryption stage (Fig. 2) are the encoder inputs, which are numbered in such a way that the binary code of the input circuit number corresponds to the output This code is generated by the encoder when a single signal appears on this input circuit. The input circuits of the first stage are divided into K groups, the counting being taken from the input specifying the zero code at the output of the cipher. The first group of input circuits contains O-fn / K-l circuits, the second - (n / Kt2p / K-1), etc. Thus, each circuit includes all the circuits whose number codes contain the same sets in the higher bits. The input circuits of each group 1.1 are connected to the corresponding p / K - input element OR 2, 1. The outputs of the elements OR 2 are connected to the inputs of K - input encoder 4, the outputs of which are with outputs 1,2, .... Each higher OR bit of the encoder (out. tl) Each element OR 3.1 is connected to the input circuits of each group whose binary codes of numbers differ only in the higher most bits. At the same time, the output of this element OR 3.1 is injected for the second stage by the input circuit, the number of which corresponds. the numbers of the input circuits of the first station to which this element is connected 3.1, but not taking into account the first hundred bits. Consequently, the second stage contains S / C input circuits, which, in turn, are divided into K groups in a similar way to & and in the first stage. Other steps are built angshogichno. So, 1- with the stump (Fig. 1) contains p / K-input circuits divided into K groups l, i. the first group l, -i of the receiver; the input circuits with the numbers Otp / kch- lie, to the second group 1, - (- the input circuits with the numbers n / K Kl-l, etc., i.e. in the composition of the group 1, i includes input circuits of the 1st stage, the binary codes of the numbers of which contain the same sets in the most significant bits.The input circuits of each group 1.1 are connected to the corresponding p / K input element OR 2, i, the outputs of which are connected To the K-input encoder 4.1. The outputs of the encoder 4.1 are (-f -Dp -and, (1 -Dp -and, ..., (-I-Dp + pm bits of the encoder (output.PZ) Each K-input element OR 3, i is connected to those input circuits of each group whose binary codes of numbers differ only in higher-order bits. Note that the code number of the input circuit - (-th stage contains the control code - p - -1 bits. The outputs of the elements OR 3, l are the inputs + 1-OUT steps. The numbering of the input circuits of the i + 1-st stage is performed in the same way as for the second stage. The last stage is (Fig. 3 contains II. #/K-input elements or 3, t, the outputs of which nx) dklyu-. to the inputs n 2 of the input additional encoder 5. The outputs of the last (output,) are tr + 1, mp + 2, ... log the n-th outputs of the encoder. Note that elaments OR 3.1 of each stage, the outputs of which are input circuits of the subsequent stage, with the numbers O, the 1st p / K, the input element of each stage are practically not used. When building real encoders, they can be omitted. The proposed encoder works as follows. At the inputs of each element OR 2.1, input circuits are introduced, the binary codes of which numbers are equal on the highest bits. Thus, at the outputs of the elements OR 2, the spatial unitary K-bit code corresponding to the positional p-bit code corresponds to the output code (1-1) p + 1, ..., ((- -) p + The pth bit of the encoder. At the outputs of the elements OR 3, i, a unitary spatial code is formed that corresponds to a positional .1 -disable positional code. This unitary code is the input code for the 1 + 1 st level of encryption. Each step of encryption yields p bits of the position output code of the encoder. stage produces 2 ° & i P -razr spatial unitary projectile loader code, which is supplied to the inputs of the encoder 5, which outputs are ck + 1 ,,, ..

 bits of the output position code of the encoder.

Example. Let the bit width of the output position code be 5, p: r2 and, therefore, n "32. The encoder will contain two steps of encryption. Let the wils be a single signal on the input circuit with the number lOlOl-Sl o. Input circuits with number 10101 Input-circuits will be divided into four groups, each with 8 circuits, the first group will be input circuits with numbers 00000 ..... 00111, the second

01000 ..... 01111, in the third - 10,000

.10111 and in the fourth - 1100011111.

The excited input circuit belongs to the third group. At the output of the third eight-input element OR 2.1, a single signal is applied. Thus,

at the outputs of the elements OR 2.1, a unitary spatial code 00100000 is produced, which corresponds to the position code 10, obtained at the outputs of the additional encoder 4.1. At the output of the fifth element OR 3.1, too, a single signal is shown on a Vits. Thus, at the outputs of the elements OR 3.1, a unitary eight-bit spatial code is also generated, corresponding to position code 101. The second stage input slots are divided into four groups similarly to the first stage. The first contains the input circuits with numbers 000.001, the second 010, 011, the third - 100,101 and the fourth - 110,111. The position code of the number of the first stage belongs to the third group. Therefore, at the outputs of the OR 2.2 elements, a unitary code 0010 is generated, which corresponds to the position code 10 obtained at the outputs of the encoder 4.2. At the outputs of the OR 2.3 elements, a unitary code 10 is generated, which corresponds to the position code 1 obtained at the output of the encoder 5. So, in general, position code 10101 is obtained at the outputs of the encoder.

Compare the amount of equipment to build the known and proposed encoders. As a measure of the amount of equipment we take Quine's price. To build a well-known encoder, many-input elements OR with a total price, are required. In the proposed encoder, the price of the first stage is + Sz1 + C4 f where n is the price of K p n / K of the input elements OR, C 1 Kooa. To the price of the additional encoder We will save the encoder specified in the known devices. The price of the first two members of each stage is K times less than the previous one.

The total price of all the stages is according to the law of a decreasing geometric progression. For example, for

and 688

n 256,

 -f. Having a record of 762. given p and choosing defined by method p, it is possible to achieve the optimal variant (Quina’s price is minimal. The encoder’s communications regularity is ensured by the similarity of its step construction and the possibility of its expansion.

Claims (2)

1. Mayor S.A. and Novikov G.I. Principles of organization of digital machines. L., Mechanical Engineering, 1974, p. 118, 2. USSR author's certificate yo application code 2629656/24, cl. G 06 F 5/02, 1978. Bbixli W / t Bb / xlm-nJ