SU1638790A1 - Programmable delay line - Google Patents

Abstract

The invention relates to radio engineering and can be used in measurement technology and other areas where the need arises for precision adjustable delay of analog signals. The purpose of the invention — improving the delay accuracy by stabilizing the load of each delay stage — is achieved by introducing a 5 converter and new connections into each delay stage. In addition, the composition of

Description

about co oo i

before

Signal input 1, code 1-bit input 2, I identical delay stages, and each delay stage Contains 3 delay elements and key element 4. The introduced differences provide the device operation mode when any delay stage is loaded only by one the entrance of the subsequent cascade. Thanks to the parallel-sequential method

connecting delay cascades provided by inserting a code converter, supplying key elements with additional inputs, combining the same outputs of all cascades, and the last 1st output directly with the device output last has a higher accuracy than the prototype device, no less than . 2 hp f-ly, 4 ill.

The invention relates to radio engineering and can be used in measurement technology and other areas of science and technology, if necessary, with a precision signal delay controlled by a code.

The purpose of the invention is to improve the accuracy of the delay by stabilizing the load of each delay stage.

Figure 1 shows a five-decade programmable delay line (LZ); in fig. 2 and 3 are diagrams of connecting with each other a code converter and a key element included in a single LZ cascade, examples of execution; FIG. 4 is a graph of the advantages of the proposed technical solution and the known one.

LZ, shown in Fig. 1, contains a signal input 1, a code 1-bit input 2 and, for example, five (I 5) identical stages, which are assigned indices 0,1,11,111 and IV.

Each cascade, in turn, contains an element of 3 delays (38), a key element (CE) 4 and a converter of 5 code (PC). The first input of the cascade is the connection point of the input of the delay element and the first input (:) of the key element. The output of the delay element is connected to the second input (: 2) of the key element, which is the second input of the cascade. In this five-stage LZ, the cascade with index II is taken for the i-th stage. Code input 2 has zero, first, second, third, and fourth bits, each having weights of 2 °, 2 2 (2), 23, and 2 4 (231). Each delay element has an input and output.

Each key element in the general case has I outputs, the first and the second

i swarm entrances. In LZ, given on

figure 1, each key element has five outputs. Their serial numbers are -1, -2, ..., -i, ..., ..., - (1-1), -I. According to the number of working outputs (i.e. those connected to other nodes L), the key elements are different from each other. The working outputs of a key element, for example, the i-th stage, are those whose sequence numbers are equal or greater. The number of operating outputs is i - i. Thus, in the five-stage LZ, key elements of the 0-, I-, II-, III- and

IV-ro cascades respectively

5,4,3,2 and 1 working output. The working outputs of the key element are the same outputs of the cascade, which includes this key element.

The last 1st outputs of all cascades are combined and connected to the output LZ. The same-name, for example, the 1st, outputs of the stages (i) CI) are combined and connected to the first input of the same-named 1st stage. Thus, the fourth outputs of the cascades 0,1,11 and III are connected to the first input of the IV-ro cascade, the third outputs of the cascades O, I and II to the input

The 3rd stage, the second outputs of the stage 0 and I - to the input of the 11th stage, the first output of the 0th stage - to the input of the 1st stage. The first input of the 0th stage is connected to the input of 1-LZ.

Converter 5 code, incoming

in each cascade, connected to the fourth input of the key element 4 has (1-1) inputs, i.e. : 1,: 2,: 3,: 4, inputs that

are the corresponding bits of the third cascade input. Bits 10

weight: first -2., second - 2, third - 2, fourth - 2. Generally

In this case, the weight of the 1st bit is 2. The bits of the third input of the cascade, the sequence numbers of which are greater than the number of this cascade, are working. Cascades differ in the number of working bits of the third input, for example, the i-th stage has (I-i-1) working bits. The same work bits of the third inputs of all cascades are combined and connected to the code section of the same name of the 2 LZ code input: the first bit of the third input of the 0th stage is connected to the first input bit, the second bit to the second, and so on. The second input of each cascade is connected to the bit of the input of 2 LZ, the sequence number of which coincides with the sequence number of the cascade: the zero bit of input 2 is connected to the second input of the 0th cascade, the 1st bit d to the second input of the 1st cascade, etc. Each of the non-working bits of the third input of each stage is connected to the source log. O (not shown in FIG. 1).

The key element 4, shown in figure 2, contains switches 6 and 7, while the output of the first is connected

with the signal input of the second, the signal 30 is not coming to the fourth input

key element 4, one of the operating outputs of the latter is activated. The number of the activated output is equal to the number of that from the input bits of the converter 5 of the code, which has the value 1. In this case, the lower bit has a priority. Under the action of the code signal arriving at the third input of the key element 4, its activated output is connected to either the first or the second input of the key element. As a result, the input (if the code signal at the third input of the key element has the value O) or the output (otherwise) signal of the delay element 3 is transmitted to the activated output. As an example, let us consider the state of LZ cascades when 2 binary numbers 01001 (N 9) arrive at its input. In cascade 0, the input from the delay element receives a signal from the input 1 of the LZ, and the inputs of the converter 5 of the code and the third input of the key element are received respectively (codes 0100 and 1. Under the action of the first code (after its transformations in the converter), third (-3) output is key

The first and the control inputs of the first one are the first, second and third inputs of the key element, the control inputs AO, A, A of the switch 7 are the bits of the fourth (code) input of the key element. Key element 4 shown in FIG. contains switch 6 and keys 3, with each key 8 connected between the output of switch b and the corresponding output of the key element, and its control input (Y) is the corresponding bit of the fourth input of the key element Converter Code 5 shown in Fig. 2, designed as a prior The power encoder 9. Code converter 5, shown in FIG. 3, is made on circuits I 10-14, having direct and inverse outputs. Here, the inputs and direct outputs of the AND 10 - 13 circuits are respectively i the first, second, third and fourth inputs and outputs of the converter 5 of the code. The output of circuit AND 14 is the fifth output of converter 5 of the code Inverse. The output of each circuit AND with a lower sequence number is connected to one of the inputs of each

five

0

AND circuits with a large sequence number, for example, the inverted output of the AND 10 circuit is connected to the first inputs of the remaining AND circuits, the inverted output of the AND 1 circuit is connected to the second inputs of the AND 12-14 circuits, etc. Scheme 14 also has an input that is connected to the source log. 1 (not shown).

The delay element 3 is realized either on commercially available MLS lines, either as a discrete-analog LZ, or as an analog shift register on a CCD.

Programmable LZ works as follows.

In the initial state, the signal to be delayed is fed to the 1 LZ input, and a number is sent to the 2 input, indicating how long the signal should be delayed. The 3 delay elements in the cascades 0,1,11,111 and IV have times

Ltl

About T - Ј. B

2

five

delays V0 2 t :, tj, tlr 2 С-, с | 1; 23Ј, tfi, respectively. In each stage, using a code converter 5, the binary code of the number arriving at its inputs is converted into a key element control code. Under the action of the control code or coming to the fourth input

five

0

five

0

five

key element 4, one of the operating outputs of the latter is activated. The number of the activated output is equal to the number of that from the input bits of the converter 5 of the code, which has the value 1. In this case, the lower bit has a priority. Under the action of the code signal arriving at the third input of the key element 4, its activated output is connected to either the first or the second input of the key element. As a result, the input (if the code signal at the third input of the key element has the value O) or the output (otherwise) signal of the delay element 3 is transmitted to the activated output. As an example, let us consider the state of LZ cascades when 2 binary numbers 01001 (N 9) arrive at its input. In cascade 0, the input from the delay element receives a signal from input 1 of the LZ, and inputs to the converter 5 of the code and the third input of the key element arrive respectively (0100 and 1). Under the action of the first code (after its transformations in the converter), the third ( -3) output is key

element, and, under the action of the second code, the signal from the output of the delay element 3 (delayed by time C) is switched to the third output of the key element. In the cascade I, the signal does not arrive at the first input (since the output.-1 of the cascade 0 to which it is connected is not activated - open), the third input receives the code 0100 (code 010 from input 2 LZ and code O from the source log. O), and the second input - code 0 from the first bit of the input 2 LZ. As a result of the similar effect of codes in stage I, the third output is also activated, to which the first input of stage I is switched (since the code at the second input is equal to O). In cascade II, the first input does not receive a signal, the third input receives code 0100 (code 01 from input 2 LZ and code 00 from the source log. O), and the second input receives code O. The state of cascade II is similar to the state of stage I In cascade III, the first input receives a signal from the third output of cascade 0, the code 0000 enters the third input (code 0 from the fourth bit of input 2 and the code 000 from the source log. O), and the second input receives 1 from the third bit input 2 LZ. With the help of the delay element of the cascade III, the input signal is delayed by time Ј (1 (2 Ј. Under the action of the first code (0000) the fifth output of the key element 4 of this cascade is activated, and under the action of the second code (1) the signal from the output of the delay element commutes to the fifth output (-5) of this cascade and then to the programmable LZ output. In cascade IV, the first input does not receive a signal (the fourth outputs of the cascades are not activated), the third input receives the code 0000 from the source O. to the second input comes in. About from the fourth bit of the input 2 LZ. This stage IV is similar to the state of stage III, except that there is no signal at the active output (-5) because there is no signal at the first input of this stage. Thus, when inputting 2 LZ code 01001, the signal from the input 1, the LSD is delayed in the delay element of the cascade 0 for a time Ј0 Ј, the delayed signal from the third output of the helmet

yes 0 enters the first entrance of the cascade III, where it is additionally delayed

In its delay element, the time is C, 2 Ј, and then comes from its fifth output to the output of the programmable LZ.

When entering the input 2 of the other

numbers change cascade states accordingly. However, in this case, the output of the lower-order cascade will be connected directly to the input of the older stage, and the output of the last (most senior) stage will be directly connected to the output of the code-controlled delay line.

From the above it follows that any delay stage is loaded only on one input of the next stage, i.e. And 1

Thus, the efficiency of the proposed code-controlled, for example, 11-cascade LZ is A, / A 20. The delay error due to the mismatch of LC LC links of the LC type is estimated to be approximately one order of magnitude above 50-80 kHz.

Programmable LZ also has a 1 time smaller parasitic error compared with the similar error t

Max

known device.

This follows from the fact that all delay stages are directly connected to the output of the code-controlled LZ. At the same time, regardless of the control code H, the parasitic error of the code-controlled LZ is equal to the parasitic delay of one stage. The efficiency of the proposed code-controlled LZ in comparison with the known one is illustrated in Fig. 4, where the graphs of parasitic errors depending on the code N for the known (curve a) and the proposed (curve b) devices for a 5-stage LZ are given. From figure 4 it follows that for a 5-cascade LZ, the additive error for the proposed device is 5 times less.

So thanks to the paral-. sequential method of connecting delay stages, for which code converters are introduced into the cascades, supplying key elements with additional outputs, combining the same outputs of all stages, and the last 1 output directly with the output of the co-controlled

LZ last has an increased accuracy of at least an order of magnitude (at $ 1. U).

Claims (3)

Invention Formula 1, A programmable delay line having a coded I-bit input and made in the form of I series-connected stages, each 1st stage, where IS 0, 1-1, contains a key element and a delay element, with in each stage the first input of each stage is connected to the input of the delay element and the first one. the input of the key element, the output of the delay element is connected to the second input of the key element, and the third input of the key element, which is the second input of this 1st cascade, is connected to the i-th bit of the code input of the delay line, So that, in order to improve the accuracy by stabilizing the load of each delay stage, a code converter, inputs), 2, 3, ..., i and inputs (iH), (i + 2), ..., (1-1) which is connected to the source log. О and to the bits (i + 1), (i + 2), ..., ..., (1-1) of the code 1-bit input, respectively, and the output are connected to the fourth executive input, ten 3879010 do key element, with additional (I-i), (l-i + 1), ..., (1-1) -th outputs of the key element; of this 1st stage are combined with the same-named additional outputs of the key elements of the remaining stages and connected to the inputs of the same-named stages, and the additional 1st outputs of the key elements of all the stages are combined and connected to the output of the coding-controlled delay line. 2. Line according to claim 1, which is different from routing so that the code converter is made in the form of a chain of AND schemes, the first inputs and direct outputs of which are the inputs and outputs of the code converter, and the inverse output of each AND circuit connected to one from the inputs of each of the subsequent schemes I. 15 20 3. Lines pop.1, which means that the key element is made up of two code-controlled analog switches connected in series, the analog inputs of the first switch being the first and second inputs of the key element, the code inputs the first and second switches are the third and fourth inputs of the key element, and the outputs of the second switch are the outputs of the key element. t / vff / irf5ff Tff and N