RU2313125C1 - Generator of pseudo-random series - Google Patents

Abstract

FIELD: computer engineering, possible use for producing a random series of a given set of data with required characteristics.

SUBSTANCE: device contains selector-multiplexer (1), random-access memory device (2), supply of random numbers (3), K P-bit registers (4), where K≥2 and P≥2, K comparison blocks (5), priority encoder (6) and N, where N≥1, inverters (7).

EFFECT: increased trustworthiness of generated series of values due to ensured dependence of value selection only on probability of occurrence of that value set by distribution law.

2 dwg, 2 cl

Description

The invention relates to computer technology and is intended to obtain a random sequence of elements of a given data set with the required characteristics.

A device for obtaining random numbers with a given distribution law (see Aut. St. USSR No. 478298, class G06F 1/02, 1973), containing a generator of uniformly distributed random numbers, a multi-stage decoder, a set-up field, an OR block, and an output device , which includes a block of AND-NOT elements, a counter and a decoder.

The disadvantage of the generator is that it has a limited area of use, since it does not allow generating symbolic and string constants with a given distribution law.

A known random number sequence generator (see Aut. St. USSR No. 447706, class G06F 1/02, 1974), containing a uniformly distributed number sensor, switch, first and second clock generators, counter, registers, valves, delay element, transducer, acquisition pulse generator and key.

The disadvantage of the generator is the limited scope, since this device does not allow to obtain a sequence of set values of the data set.

A known random number generator (see Aut. St. USSR No. 771654, class G06F 1/02, G07C 15/00, 1978) containing a source of uniformly distributed random signals, two memory blocks, adder, switch and multiplier.

The known generator allows to obtain random numbers with a given approximation accuracy both with continuous distributions and with distributions having discontinuities of the first kind. The disadvantage of the generator is the limited area of its use due to the impossibility of generating a random finite sequence of given values of a data set with a given distribution law.

Of the known closest analogue (prototype) in terms of its technical essence, the claimed device is a random number generator of given values of a data set (see Aut. St. RF №2138074, class G06F 1/02, 1999), consisting of a source of random numbers, the first and the second random access memory (made in the form of a set of 16 random-access memory devices each), a TV-bit selector-multiplexer (made in the form of a set of 3 selector-multiplexers), a comparison unit and a block of elements I. M-bit block e output ementov And where M≥2 - bit generated numbers is N-bit output "Result" generator. The bits of the N-bit output of a random number source, where N≥2 is the number of bits sufficient to address the elements of a given data set, are connected to the corresponding inputs of the second group of information inputs of the N-bit selector-multiplexer, the N-bit output of which is connected to N-bit address inputs of the first and second random access memory. The N inputs of the first group of information inputs of the N-bit selector-multiplexer are the corresponding bits of the N-bit address input of the generator. M-bit information inputs of the first random access memory and the second random access memory are combined and are the first M-bit information input of the generator. The M-bit output of the first random access memory is connected to the M-bit information input of the comparison unit, and the M-bit output of the second random access memory is connected to the M-bit input of the element block I. Each random access memory is equipped with inverse crystal select and read / write inputs which are the corresponding inputs “Choice of crystal 1”, “Choice of crystal 2”, “Read / write 1”, “Read / write 2” of the generator. The output of the comparison unit is connected to the second control input of the block of elements I. The control input of the source of random numbers, the input of the selection of the N-bit selector-multiplexer and the control input of the block of elements AND are combined and are the control input of the generator. The inverse enable input of the N-bit selector-multiplexer is the first enable input of the generator.

The known generator provides the formation of a random finite sequence of elements of a given data set with a given distribution law.

However, the prototype device has the disadvantage of a relatively low reliability of the generated sequence of set values of the data set. At the same time, reliability should be understood as the degree to which the characteristics of the generated sequence of given values of the data set correspond to the characteristics of random processes that occur in real systems.

The low reliability of the generated sequence of set values of the data set is due to the following reasons:

1. By setting the distribution law by indicating the absolute values of the required number of observations of the given elements of the data set, which leads to a determinate frequency of their occurrence at the output of the generator and to heterogeneity of the generated sequence, expressed in the fact that in the initial period of the generator’s functioning, the sequence is determined only by the distribution law of the random source numbers used to select the next generated element, and at the final stage - the law of distribution of the source random numbers and the values of the required number of observations of elements of a given data set.

2. By limiting the length of the generated sequence by the sum of a given number of generations for each element of a given data set.

The aim of the invention is to develop a random sequence generator that provides higher reliability of the generated sequence of values from a given data set by ensuring that the choice of the next generated value depends only on the probability distribution of the appearance of this value specified by the law.

The goal in the claimed random sequence generator is achieved by the fact that in the known random sequence generator of the given values of the data set containing the random number source, the first and second random access memory, N-bit selector-multiplexer, where N≥1 is the number of bits sufficient for addressing the elements of a given data set, a comparison unit and a block of AND elements, whose M-bit output, where M≥2 is the bit capacity of the generated numbers, is the “Result” M-bit output generator, the bits of the N-bit output of the random number source are connected to the corresponding inputs of the second group of information inputs of the N-bit selector-multiplexer, the N-bit output of which is connected to the N-bit address inputs of the first and second random access memory, N inputs of the first group of information inputs TV-bit selector-multiplexer are the corresponding bits of the N-bit address input of the generator, M-bit information inputs of the first random access memory two of the second random access memory are combined and are the first M-bit information input of the generator, the M-bit output of the first random access memory is connected to the M-bit information input of the comparison unit, and the M-bit output of the second random access memory is connected to the M-bit input block of elements And, each random access memory is equipped with inverse inputs of the choice of the chip and read / write, which are the corresponding inputs of the "Select crystal 1 ”,“ Choice of crystal 2 ”,“ Read / write 1 ”,“ Read / write 2 ”of the generator, the output of the comparison unit is connected to the second control input of the block of elements And, the control input of the source of random numbers, the input of the selection of the N-bit selector multiplexer and the control input of the block of elements AND are combined and are the control input of the generator, the inverse enable input of the N-bit selector-multiplexer is the first enable input of the generator, K K-bit registers are additionally introduced, where K≥2 is the number of elements in a given set D data, and R≥2, priority encoder, N inverters (K-1) comparison blocks. The random number source is made with a P-bit output. The initialization inputs of the P-bit registers are combined and are the input “Installation” of the generator. P-bit information input of the k-th P-bit register, where k = 1, 2, ..., K, is the k-th first P-bit input "Upper boundary" of the generator, P-bit output "Random number" of the source random numbers connected to the P-bit inputs of the comparison blocks. The P-bit output of the k-th P-bit register is connected to the second P-bit input "Upper boundary" of the k-th comparison block. The “Comparison Result” output of the k-th comparison block is connected to the k-th inverse input of the priority encoder, the nth inverse output of which, where n = 1, 2, ..., N, is connected to the input of the nth inverter. The inverse outputs of N inverters are connected to the corresponding bits of the second N-bit information input of the N-bit selector-multiplexer, the M-bit output of random access memory is the M-bit output "Result" of the generator.

The comparison unit consists of a comparator, a P-input element OR-NOT and an OR element, the first input of which is connected to the output "Inequality" of the comparator. The second input of the OR element is connected to the inverse output of the P-input element OR-NOT. The output of the OR element is the output “Compare Result” of the comparison block. The P inputs of the first group of information inputs of the comparator are the P-bit input "Random number" of the comparison unit. The P inputs of the second group of information inputs of the comparator are connected to the corresponding inputs of the P-input element OR NOT and are the second P-bit input "Upper boundary" of the comparison unit.

This goal is achieved through the introduction of K registers, a priority encoder, N inverters and comparison blocks that provide the setting of the distribution law for the elements of a given data set by indicating the probabilities of their occurrence, as well as the dependence of the choice of the next generated element only on the probability distribution of its appearance specified by the law and independence of length the generated sequence from the source data.

The analysis of the prior art by the applicant made it possible to establish that there are no analogs characterized by sets of features identical to all the features of the claimed technical solution. Therefore, the claimed invention meets the condition of patentability "Novelty."

The search results for known solutions in this and related fields of technology, in order to identify features that match the distinctive features of the prototype of the claimed invention, showed that they do not follow explicitly from the prior art. From the prior art determined by the applicant, the influence of the transformations provided for by the essential features of the claimed invention on the achievement of the specified technical result has not been revealed. Therefore, the claimed invention meets the condition of patentability "Inventive step".

The claimed device is illustrated by drawings, in which:

figure 1 - random sequence generator;

figure 2 - block monitoring intervals.

The random sequence generator (see Fig. 1) consists of an N-bit selector-multiplexer 1, random access memory 2, a source of random numbers 3, K P-bit registers 4 ₁ -4 _K , K comparison blocks 5 ₁ -5 _K , priority encoder 6 and N inverters 7 ₁ -7 _N.

и инверсным входом чтения/записи

, которые являются соответственно входом «Выбор кристалла» 9 и входом «Чтение/запись» 8 генератора Р-разрядные информационные входы D₁-D_P каждого из К Р-разрядных регистров 4₁-4_K являются первыми Р-разрядными входами «Верхняя граница» 14₁-14_K генератора. Входы инициализации С всех К Р-разрядных регистров 4₁-4_K объединены и являются входом «Установка» 13 генератора. Р-разрядные информационные выходы Q₁-Q_P каждого из К Р-разрядных регистров 4₁-4_K подключены к соответствующим вторым Р-разрядным входам «Верхняя граница» 18₁-18_K каждого из К блоков сравнения 5₁-5_K. Р-разрядный выход «Случайное число» 17 источника случайных чисел 3 соединен с Р-разрядными входами «Случайное число» К блоков сравнения. Каждый из К выходов «Результат сравнения» 19₁-19_K всех блоков сравнения 5₁-5_K подключен к соответствующему инверсному входу шифратора приоритетов 6. N инверсных выходов

шифратора приоритетов 6 соединены с соответствующими входами N инверторов 7₁-7_N. M выходов C₁-С_M оперативного запоминающего устройства являются М-разрядным выходом «Результат» 20 генератора.The input select SE N-bit selector-multiplexer 1 is connected to the control input of the source of random numbers 3 and is the control input 11 of the generator. The first group of N information inputs A ₁ -A _{N of the} N-bit selector-multiplexer 1 is the N-bit address input 10 of the generator. The second group of N information inputs B ₁ -B _N N-bit selector-multiplexer 1 is connected to the corresponding inverse outputs of the inverters 7 ₁ -7 _N. N outputs Q ₁ -Q _{N of the} N-bit selector-multiplexer 1 are connected to the corresponding address inputs A ₁ -A _{N of} random access memory 2, M information inputs D ₁ -D _{M of} which are the corresponding bits of the M-bit information input 12 of the generator. Random access memory 2 is equipped with an inverse input of the choice of crystal

and inverse read / write input

which are respectively the “Choice of crystal” input 9 and the “Read / write” input of the 8 generator P-bit information inputs D ₁ -D _{P of} each of the K P-bit registers 4 ₁ -4 _K are the first P-bit inputs of “Upper limit »14 ₁ -14 _K generator. The initialization inputs C of all K P-bit registers 4 ₁ -4 _{K are} combined and are the input "Installation" 13 of the generator. The P-bit information outputs Q ₁ -Q _{P of} each of the K P-bit registers 4 ₁ -4 _{K are} connected to the corresponding second P-bit inputs “Upper Border” 18 ₁ -18 _{K of} each of the K comparison blocks 5 ₁ -5 _K. The P-bit output "Random number" 17 of the source of random numbers 3 is connected to the P-bit inputs "Random number" K of the comparison blocks. Each of the K outputs “Comparison Result” 19 ₁ -19 _{K of} all comparison blocks 5 ₁ -5 _{K is} connected to the corresponding inverse input of the priority encoder 6. N inverse outputs

priority encoder 6 connected to the corresponding inputs of N inverters 7 ₁ -7 _N. M outputs C ₁ -C _M random access memory are M-bit output "Result" 20 of the generator.

N-bit selector-multiplexer 1 is designed for switching to its N-bit output signals of one of two groups of N information inputs. An implementation scheme for an N-bit selector-multiplexer is known. See, for example, in the book of I.I. Petrovsky et al. “Logical ICs КР1533, КР1554”, a reference in two parts. Part 1. - M .: Binom, 1993, p. 211.

Random access memory 2 is intended to store the values of the elements of a given data set. A random access memory implementation scheme is known. See, for example, in the book by V. L. Shilo “Popular Digital Microcircuits”. - M .: "Radio and Communications", 1987, p.164-166.

The source of random numbers 3, intended for generating P-bit random numbers, is known and shown, for example, in the book of MP Bobnev “Generating random signals”. - M .: Energy, 1971, p.168-174.

Registers 4 ₁ -4 _K are designed to store binary codes that determine the probability of occurrence of the corresponding elements of a given data set. The description of the operation and the scheme of such registers are known and are given, for example, in the book: P. P. Maltsev, N. S. Dolidze, etc. “Digital Integrated Circuits: A Reference Book”. - M .: "Radio and Communications", 1994, p. 57-62.

Priority encoder 6 is designed to convert the value of logical zero at one of its inputs into the corresponding binary code at its output, and the conversion is carried out taking into account the priorities determined by the input number. The priority encryption implementation scheme is known. See, for example, in the book: P. P. Maltsev, N. S. Dolidze and others. Reference book “Digital Integrated Circuits”. - M.: “Radio and Communications”, 1994. p.40-41.

Inverters 7 ₁ -7 _N are designed to invert signals from the inverted outputs of the priority encoder. The inverter implementation scheme is known. See, for example, in the book of I.I. Petrovsky et al. “Logical ICs КР1533, КР1554”, a reference in two parts. Part 2. - M .: Binom, 1993, p. 471-472.

Comparison blocks 5 ₁ -5 _K are intended for comparing a random value generated by a random number source and a value at the output of the corresponding register, as well as for generating a comparison result. The comparison unit can be implemented in various ways. In particular, its circuit shown in FIG. 2 comprises a comparator 5.1, a P-input element OR NOT 5.2 and an element OR 5.3. The first input of the OR element 5.3 is connected to the output "Inequality" 5.4 (which is indicated by the symbol "A>B" in figure 2) of the comparator 5.1. The second input of the OR 5.3 element is connected to the inverse output of the P-input element OR NOT 5.2. The output of the OR element is the output “Comparison result” 19 of the comparison unit 5. The P inputs of the first group of information inputs of the comparator 5.1 are the P-bit input “Random number” 17 of the comparison unit 5. The P inputs of the second group of information inputs of the comparator are connected to the corresponding inputs of the P-input element OR NOT 5.2 and are the second P-bit input "Upper border" 18 of the comparison unit 5.

Comparator 5.1 is intended for comparing two P-bit numbers and generating a comparison result. A description of the work and the comparator circuit are given, for example, in the book: V.L.Shilo “Popular Digital Microcircuits”. - M.: “Radio and Communications”, 1987, p.183-184.

The OR-NOT 5.2 element is designed to generate a logical zero value at its output, if the logical unit values are set on all bits of the second P-bit input “Upper boundary” of the comparison unit. The implementation scheme of the elements is NOT known. See, for example, in the book of I.I. Petrovsky et al .: “Logical ICs КР1533, КР1554”, the reference book in two parts, part 1. - M .: Binom, 1993, p.246-247.

The OR element 5.3 is designed to form a logical unit value at its output if one of its inputs has a logical unit value. The implementation scheme of such an OR element is known. See, for example, in the book: B.V. Tarabrin, S.V. Yakubovsky, N. A. Barkanov and others. "Reference on integrated circuits." - 2nd ed., Revised. and add. - M .: Energy, 1981, p. 109.

In the proposed device, the choice of the value of an element from a given data set is carried out on the basis of the distribution law, which is set by indicating the required probability of occurrence of the corresponding element of a given data set. In this case, the approach is applied (Modeling of information systems. / Ed. By OI Shelukhin. Textbook. - M .: Radio engineering, 2005. - 368 pp., Ill.), Based on the use of a source of random numbers distributed uniformly in the range [0; one). This range is divided into a set of intervals, the number of which corresponds to the number of elements in a given data set. The values of the intervals correspond to the values of the required probabilities of observation of the corresponding elements of a given data set. The probability of a random number generated by a random number source falling into each interval is equal to its length.

In the proposed device, the interval number is used as an address for retrieving an element of a given data set from random access memory, and for setting intervals, their upper boundaries are indicated.

, К - количество элементов заданного набора данных, а В={b₁, b₂, ..., b_k, ..., b_K} - множество соответствующих значений верхних границ интервалов. Тогда значение верхней границы k-го интервала будет равно сумме значений вероятностей появления элементов из заданного набора данных от 1-го до k-го:The probability of occurrence of elements of a given data set is defined as follows. Let H = {h ₁ , h ₂ , ..., h _k , ..., h _K } be the set of required probabilities of occurrence of elements of a given data set, where

, K is the number of elements of a given data set, and B = {b ₁ , b ₂ , ..., b _k , ..., b _K } is the set of corresponding values of the upper boundaries of the intervals. Then the value of the upper boundary of the kth interval will be equal to the sum of the values of the probabilities of the appearance of elements from a given data set from the 1st to the kth:

Thus, the range [0; 1) will be divided into the following intervals:

In the claimed device uses a P-bit source of random numbers with a uniform distribution law. In this case, the P-bit binary code generated at the output of the random number source and the P-bit binary code used to set the upper boundary of the interval are considered as numbers from the range [0; 1) without specifying the integer part.

For example, a set of required probabilities of the appearance of elements of a given data set is given H = {0.125; 0.125; 0.25; 0.5}. Then the values of the upper bounds of the intervals will be equal to 0.125, 0.25, 0.5, and 1, respectively. In accordance with the translation rules (B.Ya. Nikitin, V.I. Skrebkov, “Theoretical Foundations of Computing Engineering,” part 2, L LVVIUS, 1988, pp. 9-11) of the correct decimal fractions in binary representation; these values in a four-digit code are represented, respectively, in the form of numbers 0.0010, 0.0100, 0.1000, 0.1111. And only the fractional part of these numbers are entered in the proposed device: the values 0010, 0100, 1000 and 1111, respectively.

Similarly, if the source of random numbers generated a value of 1101 (in decimal 0.8125), then, representing this value as a fractional part of a number from the range [0; 1), i.e. as 0.1101, and given the many upper bounds for the intervals from the previous paragraph, it can be seen that a random value fell into the interval limited by the numbers 0,1000 and 0,1111.

The claimed device operates as follows.

In the initial position, at the control input 11 and the input “Installation” 13, the values of logical zero are set, and at the input “Read / write” 8 and the input “Choice of crystal” 9 - the values of the logical unit.

The generator operates in the following modes:

preparation mode for generation;

generation mode.

The operating mode of the generator is determined by the combination of signals at the control input 11 of the generator, the input "Installation" 13, the input "Read / Write" 8 and the input "Choice of crystal" 9.

To put the device into preparation mode, it is necessary to apply the values of logical zero to the control input of the generator and the inputs “Choice of crystal” and “Read / Write”, and the value of the logical unit to the input “Installation”.

In the generation mode, the control input of the generator and the input “Read / Write” are set to the values of the logical unit, and to the inputs “Choice of the crystal” and “Setting” - the values of the logical zero.

In the mode of preparing the generator for operation, the following steps are performed.

The first step is to enter the set A = [a ₁ , a ₂ , ..., a _K } of the values of the elements of a given data set into the random access memory, while:

;0≤a _k ≤2 ^M -1 - element of a given data set, where

;

M≥2 - the number of bits that is sufficient to represent the values of the elements of a given data set;

K≥2 - the number of elements in a given data set;

N≥1 - the number of bits sufficient to address the elements of the data set.

The second step is to set the set B = {b ₁ , b ₂ , ..., b _K } of the values of the upper boundaries of the intervals into which the set of addresses of the given data set A is divided.

и

значений логического нуля по входам «Выбор кристалла» 9 и «Чтение/запись» 8 соответственно. Затем по TV-разрядному адресному входу 10 генератора на первую группу информационных входов A₁-А_N селектора мультиплексора 1 подается TV-разрядный адрес, по которому должно быть записано значение второго элемента а₂, а по М-разрядному информационному входу 12 генератора на информационные входы D₁-D_M оперативного запоминающего устройства подают значение элемента а₂ и путем установки значений логического нуля на входах «Выбор кристалла» 14 и «Чтение/запись» 15 генератора записывают значение а₁ в оперативное запоминающее устройство. Аналогичным образом в оперативное запоминающее устройство заносятся все К значений элементов заданного набора данных. После чего на входе «Чтение/запись» 8 генератора устанавливают значение логической единицы.The first step in preparing the generator for work includes the following steps. The N-bit address input of the generator 10 to the first group of information inputs A ₁ -A _{N of the} selector of multiplexer 1 is fed an N-bit address at which the value of the first element a ₁ should be recorded. At the control input 11 of the generator, a logic zero value is set, which is fed to the input SE of the selector-multiplexer 1, which leads to switching the address set at the inputs A ₁ -A _{N of the} selector-multiplexer to the second N-bit input "Random address" 16 operational memory 2. M-bit data input 12 of the generator for data inputs D ₁ -D _M random access memory serves value of the first element ₁ and a given set of data, which is written into the RAM at troystvo admission to its inputs

and

values of logical zero at the inputs "Choice of crystal" 9 and "Read / write" 8, respectively. Then TV-bit address input 10 of the generator for a first group of information inputs A ₁ -A _N selector multiplexer 1 is fed TV-bit address at which is to be recorded and the value of the second element _2, and for M-bit data input 12 of the generator for informational the inputs D ₁ -D _{M of} random access memory provide the value of element a ₂ and by setting the logic zero values at the inputs “Choice of crystal” 14 and “Read / write” 15 of the generator write the value of a ₁ in random access memory. Similarly, all K values of elements of a given data set are entered into the random access memory. Then at the input "Read / write" 8 generator set the value of the logical unit.

The second step in preparing the generator for operation is as follows. At the first P-bit inputs "Upper boundary" 14 ₁ -14 _K generator set the values of the upper boundaries of the intervals. In this case, the input b _{1 is} set to the value of b ₁ , which goes to the group of information inputs D ₁ -D _P register 4 ₁ , the input 14 ₂ is the value of b ₂ that goes to the group of information inputs D ₁ -D _P register 4 ₂ , input 14 _K - the value of b _K , which is fed to the group of information inputs D ₁ -D _P register 4 _K. To record the values of the upper boundaries of the intervals in the registers 4 ₁ -4 _K at the input "Installation" 13 devices set the value of the logical unit, which is fed to the initialization inputs from each register. Upon completion of the recording of the upper boundaries of the intervals in the corresponding registers at the input "Installation" 13 devices set the value of logical zero.

After the above steps, the generator is ready for operation.

In the generation mode, the operation of the device is as follows. The value of the logical unit is supplied to the control input 11 of the generator, which is fed to the input of the SE selection of the selector-multiplexer 1, which ensures switching of the address coming from the output of the inverters 7 ₁ -7 _N to the address inputs A ₁ -A _{N of the} random access memory 2.

The source of random numbers in the presence of 1 on the control input of the generator 11 generates a value of logic-one F-bit random address value which is sent simultaneously to the first group of information inputs A ₁ -A _P all comparators 5.1 ₁ -5.1 _K comparison unit 5 where a comparison of a random address values with the upper bounds of the specified intervals B = [b ₁ , b ₂ , ..., b _K }. If the received address value belongs to the kth interval, i.e. it is less than or equal to the value of the upper boundary of the kth interval, then the output of the "Inequality" of the comparators 5.1 ₁ -5.1 _k-1 values of the logical unit are formed, and the outputs of the "Inequality" of the other comparators are the values of the logical zero.

шифратора приоритетов.The signals from the outputs "Inequality" of each comparator are fed to the corresponding inverse inputs

priority encoder.

шифратора приоритетов 6 будут установлены значения логической единицы, а на входах

- значения логического нуля. В этом случае на N-разрядном выходе

шифратора приоритетов 6 будет сформирован двоичный код в инверсном представлении, соответствующий значению первого номера входа

с установленным значением логического нуля, т.е. код, соответствующий числу k - номеру интервала, которому принадлежит значение а_k. Полученный код после инвертирования в элементах 7₁-7_N поступает на первый N-разрядный вход «Случайный адрес» 15 второй группы информационных входов селектора-мультиплексора 1 и далее на адресные входы A₁-А_N оперативного запоминающего устройства 2. При этом по входу «Выбор кристалла» 9 генератора на вход

оперативного запоминающего устройства 2 подают значение логического нуля, а по входу «Чтение/запись» 15 генератора на вход

оперативного запоминающего устройства 2 подают значение логической единицы, что соответствует операции чтения данных. Таким образом, в соответствии со случайными адресами, формируемыми источником случайных чисел, происходит чтение значений элементов А={а₁, а₂, ..., а_k} заданного набора данных из оперативного запоминающего устройства, которые поступают на выход «Результат» 20 генератора.Thus, under the condition b _k-1 <a _k <b _k , at the inputs

priority encoder 6 will be set to a logical unit, and at the inputs

- values of logical zero. In this case, at the N-bit output

priority encoder 6, a binary code will be generated in the inverse representation corresponding to the value of the first input number

with a set value of logical zero, i.e. the code corresponding to the number k is the number of the interval to which the value of a _k belongs. The resulting code after inverting in elements 7 ₁ -7 _N goes to the first N-bit input "Random address" 15 of the second group of information inputs of the selector-multiplexer 1 and then to the address inputs A ₁ -A _{N of} random access memory 2. Moreover, the input “Choice of crystal” 9 generator input

random access memory 2 serves the value of logical zero, and the input "Read / write" 15 of the generator to the input

random access memory 2 serves the value of a logical unit, which corresponds to the data reading operation. Thus, in accordance with random addresses generated by the source of random numbers, the values of the elements A = {а ₁ , а ₂ , ..., а _k } of the given data set are read from the random access memory, which are output to the “Result” 20 generator.

оперативного запоминающего устройства подают значение логической единицы.The generator stops working when a logical zero value is supplied to its control input 11, which corresponds to the termination of the generation of random numbers by the source of random addresses, or when the input to the Choice Crystal 9 of the generator is input

random access memory serves the value of a logical unit.

Unlike the prototype device, in the proposed device, the choice of the next generated element depends only on the probability distribution of its occurrence specified by the law and, at the same time, the length of the generated sequence does not depend on the source data. Thus, in the proposed device provides a higher degree of compliance of the characteristics of the generated sequence of given values of the data set with the characteristics of random processes occurring in real systems, which, ultimately, increases the reliability of the generated sequence of a given data set.

Claims (2)

1. A random sequence generator containing an N-bit selector-multiplexer, where N≥1 is the number of binary bits sufficient to address the elements of a given data set, a random number source, a first comparison unit, random access memory, M, where M≥2 - the width of the generated numbers, the information inputs of which are the M-bit information input of the generator, while the N inputs of the first group of information inputs of the N-bit selector-multiplexer are the N-bit address input of the generator , the input input of the N-bit selector-multiplexer is connected to the control input of the random number source and is the control input of the generator, N outputs of the N-bit selector-multiplexer are connected to the corresponding N address inputs of random access memory, inverse inputs of the chip selection and read / write random access memory the devices are respectively the inputs “Choice of crystal” and “Read / write” of the generator, characterized in that K-bit registers are additionally introduced, where K≥2 is the number of in elements in a given data set, and P≥2, priority encoder, N inverters, (K-1) comparison blocks, and the random number source is made with a P-bit output, and the initialization inputs of the P-bit registers are combined and are the input "Installation ”Of the generator, the P-bit information input of the k-th P-bit register, where k = 1, 2, ..., K, is the k-th first P-bit input“ Upper boundary ”of the generator, the P-bit output“ Random number "source of random numbers connected to the P-bit inputs" Random number "K blocks of comparison, P-times the row output of the k-th P-bit register is connected to the second P-bit input “Upper boundary” of the k-th comparison block, the output “Comparison result” of the k-th comparison block is connected to the k-th inverse input of the priority encoder, the n-th inverse the output of which, where n = 1, 2, ..., N, is connected to the input of the nth inverter, the inverse outputs of N inverters are connected to the corresponding bits of the second N-bit information input of the N-bit selector-multiplexer, the M-bit output of the operational the storage device is an M-bit output "Result al "generator. 2. The device according to claim 1, characterized in that the comparison unit consists of a comparator, a P-input element OR-NOT and an OR element, the first input of which is connected to the output "Inequality" of the comparator, the second input of the OR element is connected to the inverse output P- the input element OR NOT, the output of the OR element is the output “Comparison result” of the comparison unit, P inputs of the first group of information inputs of the comparator are P-bit input “Random number” of the comparison unit, and P inputs of the second group of information inputs of the comparator are connected to the corresponding inputs of the P-input element OR NOT and are the second P-bit input "Upper boundary" of the comparison unit.

Images