RU2395834C1 - Random permutation generator - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: in order to speed up formation of permutations in a random permutation generator which comprises series-connected analogue noise generator, pulse former and pseudorandom sequence generator on a shift-register with a control unit, the output of the control unit is connected by an n-bit data bus to a code permutation storage register which is connected by a 2ⁿ-bit data bus with an interface to a non-volatile memory controller which in turn is connected through the control output and input to the control unit. According to the invention, the generator also includes a decoder, a second pseudorandom sequence generator on a shift-register and a high-speed generator. The output of the decoder is connected to the write input of permutation code storage register. The control input of the decoder is connected to the output of the control unit, while the code input is connected to the second pseudorandom sequence generator on a shift-register, the clock input of which is electrically connected to the high-speed generator.

EFFECT: high speed operation of the device which generates unique random numbers through generation and loading elements from a set of 2ⁿ-bit numbers.

2 dwg, 1 tbl

Description

The device relates to computing, information and measuring radio engineering and can be used in information protection systems against unauthorized access.

) и i-го разрядов первого регистра сдвига подключены соответственно к первому и второму входам первого сумматора по модулю два, выход k-го и (i+1)-го (где

,

разрядов 1-го регистра сдвига подключены соответственно к первому и второму входам 1-го сумматора по модулю два, выход первого сумматора по модулю два соединен с информационным входом одноименного регистра сдвига и с одноименным выходом блока управления, выход каждого регистра сдвига подключен к второму входу одноименного элемента И, выходы элементов И являются выходами генератора (см. авторское свидетельство СССР №2081450, МПК G06F 7/58).A device of the generator of an n-digit pseudo-random sequence containing n AND elements, a control unit equipped with n outputs, the first inputs of which are connected to the corresponding outputs of the control unit, n adders modulo two and n shift registers, and the outputs of the jth (where

) and the i-th bits of the first shift register are connected respectively to the first and second inputs of the first adder modulo two, the output of the k-th and (i + 1) -th (where

,

the bits of the 1st shift register are connected respectively to the first and second inputs of the 1st adder modulo two, the output of the first adder modulo two is connected to the information input of the same shift register and the same output of the control unit, the output of each shift register is connected to the second input of the same name of the element And, the outputs of the elements And are the outputs of the generator (see USSR author's certificate No. 2081450, IPC G06F 7/58).

With the length of the shift register n, 2 ⁿ unique codes of length n can be obtained, however, they are not random, since, knowing the device of the generator and the current generated code, the remaining codes can be restored.

A device for a pseudo-random number generator is known in which a shift register with linear feedback and a nonlinear circuit are used. The device generates pseudo-random numbers with a given distribution. The generator has a shift register, to which the output of the nonlinear circuit is connected, a circuit for setting random initial values in a shift register with linear feedback, and a shift register and adder for adding up the predefined bits of the parallel register output and the output of the pseudo-random number stream (see US patent No. 5566099, IPC G06F 7/58; G09C 1/00; H03K 3/84).

However, this generator is not a random number generator, since, knowing the generator device and the current generated code, you can restore the remaining codes.

Closest to the proposed solution is a random number generator containing a pseudo-random sequence generator on a shift register of length n with linear inverted connections, the output of which is connected to the control unit, an analog noise generator and a pulse shaper, one output of the shaper is connected to the clock input of the pseudo-random sequence generator, and the second - to the control unit, an additional shift register for storing permutations of numbers of length n, data output, clock input and data input to They are connected to the control unit, the interface to the non-volatile memory controller, the input and output of which are connected to the control unit (see RF patent No. 2340931, IPC G06F 7/58).

The disadvantage of this generator is its low speed, since high-quality data mixing in the shift storage register of number permutations requires at least (2 ⁿ ) shift and transposition operations.

The objective of this solution is to create a high-performance random number generator to control the permutation in the information stream in order to ensure its confidentiality.

The technical result is to provide a high speed device that generates unique random numbers by generating and loading elements from a set of 2 ⁿ n-bit numbers.

The problem is solved in that in order to accelerate the formation of a permutation into a random permutation generator containing an analog noise generator, a pulse shaper and a pseudo-random sequence generator on a shift register with a control unit, a code permutation storage register is connected to the output of the control unit n-bit data bus, Compound 2 ⁿ -bit data bus interface with a non-volatile memory controller which, in turn, the input and output is governed I am connected to the control unit, according to the decision, a decoder, a second pseudo-random sequence generator on the shift register and a high-speed generator are added to it, while the decoder output is connected to the write input of the code permutation storage register, the decoder control input is connected to the control unit output, and the code input - with a second pseudo-random sequence generator on a shift register, the clock input of which is electrically connected to a high-speed generator.

As a result, the permutation is formed in 2 ⁿ write operations in the code permutation storage register.

The invention is illustrated by drawings, where in Fig. 1 is a block diagram of a device, in Fig. 2 is a diagram of a decoder of a recording cell number for n = 2.

1 - analog noise generator;

2 - pulse shaper;

3 - pseudo-random sequence generator on a shift register;

4 - control unit;

5 - register storage permutations of codes;

6 - interface with a non-volatile memory controller;

7 - high-speed generator;

8 - the second generator of a pseudo-random sequence in a shift register;

9 - decoder;

D ₁ - logical elements of the nodes of the decoder cell number records;

D ₂ - logical elements of the output stages of the decoder of the recording cell number;

A ₁ , A ₂ - inputs of the decoder of the recording cell number;

S ₁ , S ₂ , S ₃ , S ₄ - the output pulses of the recording pulse of the decoder of the number of the recording cell;

S - input pulse recording decoder cell number recording;

R is the input of the reset pulse of the triggers of the logical elements D2 of the decoder of the recording cell number.

The random permutation generator consists of an analog noise generator 1 connected through a pulse shaper 2 to the clock input of a pseudorandom sequence generator on a shift register of length n 3. Shift register 3 is connected by an n-bit data bus to control unit 4. Control unit 4 is connected by an n-bit bus data with inputs of the register of permutations storage of codes 5. The device includes a high-speed pulse generator 7, which is electrically connected by its output to the second pseudo-random generator th sequence in the shift register 8 are electrically connected n-bit bus data decoder room entry cell 9, the outputs of which are electrically connected to inputs of recording 2 ^{n n-bit} cells storing the permutation code register and the input of the write pulse and the reset trigger logic elements is electrically connected with control unit. The control unit 4 is also connected by a data and control bus with an interface with a non-volatile memory controller 6. Any standard interface used to connect peripheral devices to a computer can be used as an interface.

The device operates as follows.

дешифратора номера ячейки записи 9. Схема дешифратора для N=2 представлена на фиг.2. Каждый узел дешифрации выполнен в виде логических элементов D₁ с двумя входами x₁, х₂ и двумя выходами u₁, u₂, реализующих логическую функцию

, u₂=х₁×х₂ и образующих двоичное дерево. Для предотвращения многократной записи данных в ячейки с одинаковым номером регистра хранения перестановок кодов выходные каскады дешифратора 9 выполнены на логических элементах D₂. Логические элементы D₂ имеют два входа x₁, x₂, два выхода u₁, u₂, вход сброса x₁ внутреннего триггера. Триггер устанавливается в состояние высокого логического уровня при осуществлении записи данным выходным каскадом дешифратора. Представленная ниже таблица истинности логических элементов D₂ иллюстрирует процесс записи кода в текущую ячейку или переноса в следующую ячейку. Если в текущем цикле работы запись в ячейку была осуществлена, данные переносятся в следующую ячейку и так далее до достижения пустой ячейки.After turning on the generator, the signal from the analog noise generator 1 through the pulse shaper 2 is fed to the clock input of the pseudo-random sequence generator on shift register 3, the data outputs of which generate a pseudo-random sequence of codes of length n. Data shift occurs on the leading edge of the pulses. The clock pulses from the high-speed generator 7 are fed to the second generator of the pseudo-random sequence 8 on the shift register, which also generates a pseudo-random sequence of codes of length n on its data outputs. The repetition rate of the clock pulses of the high-speed generator 7 is 2 ⁿ times higher than the average pulse repetition rate of the pulse shaper 2. The codes of the second generator of the pseudo-random sequence 8 on the shift register are input

the decoder of the cell number of the recording 9. The scheme of the decoder for N = 2 is presented in figure 2. Each decryption node is made in the form of logic elements D ₁ with two inputs x ₁ , x ₂ and two outputs u ₁ , u ₂ that implement a logical function

, u ₂ = x ₁ × x ₂ and forming a binary tree. To prevent multiple data recording in cells with the same number of the code permutation storage register, the output stages of the decoder 9 are made on logic elements D ₂ . Logic elements D ₂ have two inputs x ₁ , x ₂ , two outputs u ₁ , u ₂ , reset input x _{1 of an} internal trigger. The trigger is set to a high logic level when recording with this output stage of the decoder. The logical truth table D ₂ below illustrates the process of writing code to the current cell or transferring it to the next cell. If a write to a cell has been made in the current work cycle, the data is transferred to the next cell, and so on, until an empty cell is reached.

The truth table of the logic elements D ₂ x ₁ x ₂ x ₃ u ₁ u ₂ Note 0 0 0 0 0 0 one 0 0 one write to current cell one 0 0 0 one write to current cell one one 0 0 four write to current cell 0 0 one 0 0 0 one one one 0 transfer to the next cell one 0 one one 0 transfer to the next cell one one one one 0 transfer to the next cell

When the non-volatile memory 6 receives a signal for issuing a code from the controller 6, the control unit 4 sends a short pulse to the input S of the decoder 9 of the recording cell number along the trailing edge of the signal of the pulse shaper. This pulse records the code of the second generator of the pseudo-random sequence 8 on the shift register in the cell of the code permutation storage register, whose number is determined by the code of the second generator of the pseudo-random sequence on the shift register and the state of the decoder. In the recording process, the trigger of the output stage of the decoder 9 performing the recording is set to a state with a high logical level. The process is repeated 2 ⁿ times, after which the control unit 4 supplies a reset signal to the input R, by which the triggers of the decoder output stages go into a state with a low logic level. After the permutation is generated, the data of the code permutation storage register is written to non-volatile memory through the interface with the non-volatile memory controller 6. Since the write signals to the code permutation storage register 5 are random in nature, linear shift feedback register codes are written to cells with random numbers.

Thus, the proposed solution provides for 2 ⁿ cycles of the pulse shaper record a set of 2 ⁿ unique codes of length n, following in random order.

Claims (1)

A random permutation generator containing an analog noise generator, a pulse shaper, and a pseudorandom sequence generator on a shift register with a control unit connected to the output of the control unit by an n-bit data bus is connected to a code permutation storage register connected by a 2 ^n- bit data bus with an interface to the controller non-volatile memory, which, in turn, is connected to the control unit by the input and output of the control, characterized in that it is additionally introduced into it This is a decoder, a second pseudo-random sequence generator on the shift register and a high-speed generator, while the decoder output is connected to the write input of the code permutation storage register, the decoder control input is connected to the control unit output, and the code input is connected to the second pseudo-random sequence generator on the shift register whose input is electrically connected to a high-speed generator.

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