JPH04195899A - Semiconductor device - Google Patents

Abstract

PURPOSE:To measure a threshold voltage and externally output without providing a terminal for the measurement of the threshold voltage by integrally providing a binary data generating circuit, D-A converter, and comparator for the purpose of measuring the threshold voltage of a nonvolatile memory element. CONSTITUTION:An (n) bit binary data is generated while its value being changed by the (n) bit binary data generating circuit 1, and the binary data is converted by the D-A converter 2 to an analog voltage under a power source voltage 10 as the maximum voltage with 1/2'' resolution and is added to the voltage input terminal of the nonvolatile memory element 3 at the time of measuring the threshold voltage. And, through the comparator 6, the expected value of the output data from the nonvolatile memory element 3 and the output value of a sense amplifier 5 are compared, and depending on the result of the comparison, the change of the binary data of the binary data generating circuit 1 is stopped. Thus, without providing the terminal for the purpose of measuring the threshold voltage of the nonvolatile memory element 3, the threshold voltage is measured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device including a nonvolatile memory element.

[Conventional technology]

One of the important characteristics of a nonvolatile memory element is data retention characteristics, and measuring the second retention characteristic during inspection is important for product reliability. To measure this retention characteristic, it is necessary to accurately measure the threshold voltage of the nonvolatile memory element.

FIG. 3 shows a circuit configuration diagram for measuring the threshold voltage of a conventional nonvolatile memory element. A voltage from a variable voltage external power supply 37 obtained from a memory tester or the like is applied to the gate electrode of the nonvolatile memory element 3 via a threshold voltage monitoring terminal 35 provided on the semiconductor chip. In some cases, the voltage is applied to a source electrode, a train electrode, or a substrate electrode instead of the gate it electrode. The sense amplifier 5 detects a change in the output of the nonvolatile memory element 3 in response to a change in the voltage of the external power supply 37, leads the output of the sense amplifier 5 to the data output terminal 36, and uses the voltage at the data output terminal 36 to detect a change in the output of the nonvolatile memory element 3 in response to a change in the voltage of the external power supply 37. The external data comparator 38 reads the output data, and compares the expected value of the output of the nonvolatile memory element 3 with the data read from the sense amplifier 5 without changing the voltage of the external power supply 37. It has been common practice to measure the threshold voltage of the memory element 3.

Note that 4 is a load, 10 is a power supply voltage, and II is a reference voltage.

[Invention or problem to be solved]

However, in recent years, when a nonvolatile memory element and a microcontroller are used in a single chip configuration,
For data security and data destruction prevention reasons, the external terminals are power supply terminal and ground (GND).
It is necessary to limit the number of terminals to five terminals: a terminal, a serial input/output terminal, a clock terminal, and a reset terminal.I) It is not possible to provide a terminal for measuring the threshold voltage of the nonvolatile memory element 3.

Furthermore, when a threshold voltage measurement circuit is provided in a semiconductor chip, the number of threshold voltage measurement data must be increased in order to accurately measure the threshold voltage of the nonvolatile memory element 3. .

For example, in order to measure the threshold voltage with an accuracy of 1/2n of the power supply voltage, it is necessary to prepare or generate 2a types of threshold voltage measurement data.

Furthermore, if these 2'' types of threshold voltage measurement data are simply used, a maximum of 2' sense operations will be required, leading to an increase in inspection time and inspection costs. be.

A first object of the present invention is to provide a semiconductor device that can measure the threshold voltage of a nonvolatile memory element without providing a terminal for measuring the threshold voltage.

A second object is to provide a semiconductor device that can measure the threshold voltage of a nonvolatile memory element at high speed and with high precision, in addition to achieving the first object.

Means for Solving Problem C] The semiconductor device according to claim (1) comprises: a non-volatile memory element that stores predetermined data; a sense amplifier that detects the storage contents of the non-volatile memory element; and binary data that is generated. A binary data generation circuit of n bits (n is any natural number) that can change the output voltage, and the binary data output from this binary data generation circuit is converted into an analog voltage with a resolution of 1/2" using the power supply voltage as the highest voltage. A digital-to-analog converter (hereinafter referred to as rD-A converter) is applied to the voltage input terminal of the nonvolatile memory element when measuring the threshold voltage, and the expected value of the output data of the nonvolatile memory element is compared with the output value of the sense amplifier. The semiconductor device according to claim (2), further comprising a comparator that stops the change in the binary data of the binary data generating circuit according to the comparison result, is the binary data generating circuit according to claim (1). After inputting 1-bit data of "1" or "0" to the most significant bit, shift it sequentially every time a clock signal is input until it exits the least significant bit.
They are provided for each stage of the shift register and each stage of the one-stage shift register, and are set when the output of each stage becomes 1-bit data of "]" or "0". n latch circuits that are reset by the comparison signal output from the comparator, and each of the outputs of the second to nth stages of the shift register.
n- corresponding to each of the first to n-th stages of the shift register according to the comparison signal output from the comparator when the data becomes 1-bit data of 0 or 0.
It is characterized in that it is composed of n-1 logic gates that each reset one latch circuit.

[Effect]

According to the configuration described in claim (1), the n-bit (n is any natural number) binary data generation circuit generates n-bit binary data without changing its value, and the D-A converter generates binary data. The binary data output from the data generation circuit is converted into an analog voltage with a resolution of 1/2'' using the power supply voltage as the highest voltage, and is applied to the voltage input terminal of the nonvolatile memory element when measuring the threshold voltage. The comparator compares the expected value of the output data of the nonvolatile memory element with the output value of the sense amplifier, and stops changing the initial data of the binary data generation circuit based on the comparison result.

As described above, in addition to the nonvolatile memory element and the sense amplifier, this semiconductor device also includes a binary data generation circuit, a D-
Since the A converter and comparator are integrated, it is possible to measure the threshold voltage of a nonvolatile memory element without providing a power supply terminal or a terminal for reading data from the nonvolatile memory element. It can be measured and output externally. As a result, it is effective in terms of security of data stored in the nonvolatile memory element and prevention of data destruction.

According to the structure recited in claim (2), the binary data generation circuit includes an n-stage shift register, n launch circuits, and n stages.
- It consists of one logic gate and performs binary search, which determines the value in order from the most significant bit of the binary signal according to the comparison signal of the comparator, so it is sufficient to perform n sense operations and comparison operations. So, 1 of the power supply voltage
It is possible to measure the threshold voltage of a non-volatile memory element with an accuracy of /2". With this method, the threshold voltage of a non-volatile memory element can be measured with high precision and at high speed, reducing the test time. It is also possible to reduce inspection costs.

〔Example〕

First Embodiment A first embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a circuit diagram of a semiconductor device according to a first embodiment of the present invention.

In FIG. 1, a nonvolatile memory element 3 made of a MOS transistor is connected in series with a load 4, and a power supply voltage 10 is applied to one end, and a reference voltage 11 is applied to the other end. Then, the voltage at the connection point between the nonvolatile memory element 3 and the load 4 is detected by the sense amplifier 5.

The above configuration is related to the nonvolatile memory element 3 and its read operation. Next, the configuration of the threshold voltage measuring circuit section of the nonvolatile memory element 3 will be explained.

Binary data generation circuit 1 receives data input signal D1.
The clock signal CK and the comparison signal CP output from the comparator 6 are inputted to generate n-bit binary data. The generated binary data is input to the D-A converter 2, and the D-A converter 2 generates a voltage with a resolution of 1/2'' with the power supply voltage 10 as the maximum value according to the input binary data, and converts it into a non-volatile The voltage is applied to the gate of the memory element 3.

When the gate voltage of the nonvolatile memory element 3 is lower than its threshold voltage, the nonvolatile memory element 3 is off, and the voltage is input to the sense amplifier 5 via the power supply voltage 10 or the load 4. When predetermined data is written to the nonvolatile memory element 3 and the gate voltage of the nonvolatile memory element 3 exceeds its threshold voltage, the input to the sense amplifier 5 changes from the power supply voltage 10 to the load 4 and the nonvolatile memory element 3. The voltage is divided by the memory element 3, and the output of the sense amplifier 5 is reversed.

The comparator 6 outputs the output value of the sense amplifier 5 and expected value data (data to be output by the nonvolatile memory element 3)
A is compared with A, and the comparison result is provided to the binary data generation circuit I as binary data indicating whether the two match or do not match.

The binary data generation circuit 1 automatically changes the binary data generated every time one clock signal CK is input, causes the sense amplifier 5 to perform the next sensing operation, and converts the binary data according to the output value of the comparator 6. Controls change, continuation, and termination of sense operation.

For example, a binary counter is used as the binary data generation circuit 1, and the gate voltage of the nonvolatile memory element 3 is sequentially lowered by 1/2" of the power supply voltage 10 from the maximum value of the power supply voltage 10, so that the sensing operation is performed. If the binary counter's counting operation is stopped and the information of the binary counter is read when the output of the comparator 6 first changes, the non-volatile memory element 3 can be read with a maximum of 2n sense operations. The threshold voltage can be measured. Alternatively, the gate voltage of the nonvolatile memory element 3 can be measured by
It is also possible to measure the threshold voltage of the nonvolatile memory element 3 by sequentially increasing the power supply voltage 1/2' volts from 0 volts by performing a sensing operation and a comparison operation.

In this embodiment, the output of the D-A converter 2 is inputted to the gate electrode of the nonvolatile memory element 3, but the output of the D-A converter 2 is inputted to the source electrode, train electrode, or substrate electrode of the nonvolatile memory element 3. A configuration for measuring the threshold voltage of 3 is also conceivable.

Second embodiment Next, a second embodiment of the invention will be described.

The semiconductor device according to the second embodiment of the present invention uses, as the binary data generating circuit 1 shown in FIG. It is possible to measure the same threshold voltage as when using the binary counter described above. This configuration will be explained with reference to FIG. 2.

FIG. 2 is a circuit configuration diagram of a binary data generation circuit built into the semiconductor device of the second embodiment.

This binary data generation circuit generates, for example, 4-bit binary data, and as shown in FIG. 2, includes four flip-flops 12. +3°14, 15
The output AI of the four-stage shift register 25 consisting of
A2. A3. A4 or latch circuit with set input and reset input + 6.17.18.19 set manual S
is entered as . Furthermore, the outputs A2 . of the second, third, and fourth stages of the shift register 25. A3. A4 are input to the AND circuits 22, 23, 24 together with the comparison signal CP given from the comparator 6, respectively, and the outputs 81, . B2.
B3 is reset manually to latch circuit 16.17.18 R
is entered as . A comparator signal CP is directly input to the latch circuit 19 as the human reset power R. R3 is a reset signal for simultaneously resetting the four latch circuits B16, 17, 18, and 19. In addition,
Each of the latch circuits +6, 17, 18, and 19 is composed of, for example, two NOR circuits 20, 21.

The operation of the binary data generation circuit shown in FIG. 2 will be explained below. First, latch circuit 16.17°18,1
9 output (=output of binary data generation circuit) C1, C
2, C3, C4 and the output AI of the shift register 25.

A2. A3. After resetting A4 to (0, 0, 0, O) respectively, "1" is inputted to the flip-flop 12 constituting the shift register 25 by the data input signal DI, and the outputs of the shift register 25 are AI and A2. ．．
A3゜A4 becomes (1,0,0,0), which is transmitted to the latch circuit 16.17.18.19, and the output C1 of the latch circuit 16 is "1', the latch circuit B17.18.19
The outputs C2, C3, and C4 are each set to "0". At this time, the comparator signal CP is rOJ, and the latch circuit MIK16. 17. 18. Since the contents of 19 are not reset, the latch circuit +6.17.18.1
9's output CI, C2, C3, C4 are (], 0.
0. 0) is maintained.

Next, when one clock signal CK is input, since the data input signal DI is returned to "0" at this time, the outputs AI, A2 . A3. A4 changes from (], 0, 0.0) to (0, 1, 0, 0),
The contents of latch circuit]7 are set to "1". Latch circuit +6.17.18.19 output CI, C2, C3
Comparator signal CP when ゜C4 (], 0, 0.0)
If rOJ, that is, if the gate voltage applied from the D-A converter 2 to the nonvolatile memory element 3 corresponding to (1,0,0,0) is lower than the threshold voltage, the latch circuit +6.17 Since the contents of .18.19 are not reset, the output CI of latch circuit 16.17.18°19,
C2, C3, and C4 are (], l, 0.0). Conversely, if the comparison signal CP or rlJ is (1
, 0, 0, 0), if the gate voltage applied from the D-A converter 2 to the nonvolatile memory element 3 is higher than the threshold voltage, the contents of the latch circuit 6 are set, and the flip-flop 13 is set. Together with the output A2 or the two that became "1'", the launch circuit 16. +7.18.19
The outputs C1, C2, C3°C4 become (0,], 0.0). Note that at this time, the output A3. of the flip-flop 14.15. Since both A4 and A4 are "0", the latch circuit BI7.18 is not reset and the previous state is maintained. Moreover, the comparison signal CP is directly applied to the latch circuit 19, and the comparison signal CP or "
The latch circuit I9 is reset every time the latch circuit 1j dejs, or it holds the data of the final stage flip-flop 15, and before that, it is always in the "0" state, so there is no problem.

The above operation is repeated every time the clock signal CK is input. As a result, when the second clock signal CK is input,
Output AI of shift register 25, A2. A3゜A4
changes from (0,], 0.0) to (0, O, 1, 0>, and the contents of the latch circuit 18 are sent to rx. Here, the output of the latch circuit +6.17.18.19 CI, C
2, C3, C4 (*, ], 0.0) [* is 1 or 0] Comparator signal CP or ['OJ, if
Since the contents of the latch circuit J6.17.18.19 are not reset, the outputs CI, C2, C3, and C4 of the latch circuit +6.17.18.19 become (*, ], 1.O). Conversely, the comparator signal CP or rlJ is set to 1 depending on the contents of the launch circuit 17.19, so the launch circuit 16. +7.18.19 output C1, C2, C
3, C4 becomes (*, 0, 1.O').

Next, after the third clock signal CK is input and the same comparison operation as above is performed, the clock signal CK is input. Meta 25 output Al, A2. A3. A4 is (0, 0, 0, 1
), and the latch circuit 16. +7.18.19 (7)
The outputs C1, C2°C3, C4 become (*, *, L l) [* is 1 or 0].

After this, when the fourth clock signal CK is input, 5
Output AI of shift register 25, A2. A3. A
4 becomes (0°0.0.0), and the contents of the latch circuit 19 hold r]J if the comparison signal CK is rOJ, and reset to "o" if the comparison signal CK is 1j. be done. In addition, at this time, the latch circuit is 16 degrees. 17
．． 18. The contents are not reset and retain their previous state.

With this configuration, by performing the sensing operation four times, it is possible to generate the optimal binary data from among 2'' types and perform binary search, and the final latch circuit 16.17.18.19 output CI.

C2, C3, C4 correspond to the threshold voltage of the nonvolatile memory element 3 determined with an accuracy of 1/2' of the power supply voltage 10, and the final launch circuit 16.1? ,
By outputting the outputs CI, C2, C3, and C4 of 18°19 to the outside, the threshold voltage of the nonvolatile memory element 3 can be notified.

In addition, in this embodiment, the latch circuit +6.17.18°1
Logical case 1 of 9's set human power S and reset human power R is N
Consisting of OR circuits 20.21 and launch circuits 16. +7
By configuring the logic gate that generates the signal to reset ゜18 and 19 with AND circuits 22, 23, and 24,
Output Al of shift register 25, A2. A3. A
4 as (1,0°0.0) → (0, l, 0.0) → (0
,0,], 0)→(0,0,O,])→(0,0,0
, 0), or the latch circuit +6.17°18
, 19 set manual power S and reset manual power R logic gates are constructed with NAND circuits, and latch circuits 16.17°18.
OR the logic gate that generates the signal to reset 19.
By configuring the circuit, the output A1. A2. A3. A4 (0,1,1,1)
-(1,0°1.1) -(+,1.0.1) -(1
, 1, 1, 0) - (1, 1, 1, l), the threshold voltage can be measured by the same operation as above.

Although the above embodiment has been described with n=4, the value of n is not limited to this.

〔Effect of the invention〕

The semiconductor device according to claim (1) includes, in addition to the nonvolatile memory element and the sense amplifier, a binary data generation circuit and a D-
Since the A converter and comparator are integrated, it is possible to measure the threshold voltage of a nonvolatile memory element without providing a power supply terminal or a terminal for reading data from the nonvolatile memory element. It is possible to measure and output it externally. As a result, it is effective in terms of security of data stored in the nonvolatile memory element and prevention of data destruction.

In the semiconductor device according to claim (2), the binary data generation circuit includes an n-stage shift register, n latch circuits, and n
-] logic gates, and performs binary search in which the value is determined sequentially from the most significant bit of the binary signal according to the comparison signal of the comparator, so it is possible to perform n times of sensing and comparison operations. Therefore, the power supply voltage I
The threshold voltage of a nonvolatile memory element can be measured with an accuracy of /2n. Therefore, the threshold voltage of a nonvolatile memory element can be measured with high precision and at high speed, and it is possible to reduce testing time and testing cost.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a circuit diagram of a binary data generation circuit in a semiconductor device according to a second embodiment of the present invention, and FIG. 3 is a conventional circuit diagram of a semiconductor device according to a second embodiment of the present invention. FIG. 3 is a circuit configuration diagram for measuring the threshold voltage of a nonvolatile memory element. 2... D-A converter, 3... Nonvolatile memory element, 5... Sense amplifier,
6. Comparator, DI, data input signal, CK clock signal, DA...expected value data,! 2.13゜1
4, 15...Flip-flop, 16. 17. 1
8. 19...Latch circuit, 22.23.24...A
ND circuit, CP... Comparator signal patent applicant Matsushita Electric Industrial Co., Ltd. Agent Patent attorney Akio Kanai

Claims (2)

[Claims] (1) A nonvolatile memory element that stores predetermined data, a sense amplifier that detects the memory contents of the nonvolatile memory element, and n-bit (n is any natural number) binary data that can change the generated binary data. A generator circuit converts the binary data output from the binary data generator circuit into an analog voltage with a resolution of 1/2^n using the power supply voltage as the highest voltage, and inputs the binary data to the voltage input terminal of the nonvolatile memory element during threshold voltage measurement. and a comparator that compares the expected value of the output data of the nonvolatile memory element with the output value of the sense amplifier, and stops changing the binary data of the binary data generation circuit based on the comparison result. semiconductor device. (2) Binary data generation circuit is “1” or “0”
an n-stage shift register that sequentially shifts 1-bit data from input to the most significant bit until output from the least significant bit each time a clock signal is input; are set when the output of each stage becomes 1-bit data of "1" or "0", and only the one corresponding to the nth stage of the shift register is reset by the comparator signal output from the comparator. n latch circuits, and each of the outputs of the second to nth stages of the shift register
n-1 latch circuits corresponding to each of the first stage to the n-1th stage of the shift register in response to a comparison signal output from the comparator when the data becomes 1-bit data of "" or "0". 2. The semiconductor device according to claim 1, comprising n-1 logic gates each of which is reset.