RU2717629C1 - Random sequence generator - Google Patents

Abstract

FIELD: computer equipment.SUBSTANCE: invention relates to computer engineering and is intended to generate a random sequence of values from a given plurality of values with the required characteristics of the generated sequence. Random sequence generator comprises: first selector-multiplexer, second selector-multiplexer, first register, source of random numbers, random access memory, K≥2 units for storing boundaries of intervals, K comparator units, a priority encoder, N≥1 inverters, a second register, a unit for checking transition probabilities, a unit for correcting transition probabilities.EFFECT: design of a random sequence generator, which improves reliability of the generated sequence.3 cl, 4 dwg

Description

The invention relates to computer technology and is intended to generate a random sequence of values from a given set of values with the required characteristics of the generated sequence.

Known random sequence generator according to the patent of Russian Federation No. 2250489 "Random sequence generator", IPC G06F 7/58, H03K 3/84 published April 20, 2005, Bull. No. 11, including a random number source, N-bit selector-multiplexer, random access memory, interval control unit, number of generations control unit, J-input OR element, I element block. This analogue provides the formation of a final sequence of given values of a data set for a given in the interval form, the distribution law with a random frequency of occurrence of values within the intervals.

The disadvantage of this device is the formation of a limited sequence of set values of the data set, which is due to the approach implemented in the device to set the distribution law, which involves indicating the absolute values of the required number of observations of elements of a given data set at the output of the device for each of the intervals.

Known random sequence generator according to the patent of Russian Federation No. 2313125 "Random sequence generator" IPC G06F 7/58, H03K 3/84, G07C 15/00, published 20.12.2007, Bull. Number 35. This device contains a random number source, random access memory, N-bit selector-multiplexer, K P-bit registers, K comparison blocks, priority encoder, N inverters. The device provides the formation of an unlimited sequence of set values of the data set, the frequency of occurrence of which is determined only by a given distribution law.

However, this device has a drawback - a narrow scope, limited by the ability to simulate discrete random processes characterized by the absence of a probabilistic relationship between the states of a random process (between the generated values of a given data set), the absence of a probabilistic dependence of each successive state of a random process on the previous one.

Of the known closest analogue (prototype), in its technical essence, the claimed device is a random sequence generator according to RF patent No. 2542903 "Random sequence generator", IPC G06F 7/58, G06F 1/02, published on 02.27.2015, Bull. No. 6. The prototype device contains a source of random numbers, random access memory, first and second selector multiplexers, K blocks for storing the boundaries of intervals, K comparison blocks, a priority encoder, N inverters, the first and second register. The prototype device provides the formation of the values of the elements of a random process, taking into account the probabilistic relationships between the states of this process.

However, the prototype has a drawback - a relatively low reliability of the generated sequence of given values of the data set under conditions characteristic of random processes occurring in real systems, in real computer technology, when the values of the elements of the random process depend not only on probabilistic, but also on unreliable (not enough, incomplete and contradictory given) connections between the states of this process.

This device allows you to obtain the current probabilistic-temporal values of the elements of a given data set, taking into account the presence of a probabilistic (quantified) relationship of each successive value with the previous one, while neural network models are widely used in the study of many random processes that occur in real systems [1 ], objectively based on unreliably (insufficiently, ambiguously, incompletely and inconsistently) given values of parameters of a random process, where the connection of each successive value is tions with the previous (transition probabilities) of the generated sequence of values is not only quantitative probabilistic (reliably identified), but also ambiguous (incomplete and contradictory) character traditionally described with the assistance of mathematics of artificial neural networks.

The aim of the invention is to develop a device that improves the reliability of the generated sequence by enabling the generation of given values of the data set taking into account the presence of not only probabilistic, but also ambiguous (incomplete, contradictory) connection of each successive value with the previous one, the creation of a random sequence generator capable of high form reliability values of the elements of a random process that characterizes the real behavior of a complex computing system systems - when the relationship of the parameters of a random process, the relationship of each of the next sequence of generated values with the previous value has both quantitative (probabilistic) and qualitatively (ambiguous, incomplete and contradictory) expressed physical meaning.

This goal is achieved by the fact that in a known random sequence generator containing K comparison blocks, where K≥2 is the maximum possible power of a given set of generated values, the first selector-multiplexer, the second selector-multiplexer, random access memory, priority encoder, N inverters, where N = [log ₂ K] is the number of binary digits sufficient to address the elements of a given set of generated values, K blocks of storage of the boundaries of the intervals, made in the form of random access memory properties, the first register, the second register and the source of random numbers, an additional block is included for checking the values of transition probabilities, intended for preliminary analysis, identification (selection) of ambiguously (incomplete, contradictory) identifiable probabilities of transitions of a random process from state to state, and a block for correcting values transition probabilities, designed to transform the source data (values of the probabilities of transitions of a random process from state to state) specified in a significant (incomplete, contradictory) form to a form that allows one to reliably (uniquely, completely, consistently) identify and interpret the values of the probabilities of transitions of a random process from state to state. Moreover, the P-bit, where P> N, the output "Random number" of the source of random numbers is connected to the P-bit inputs "Random number" of K comparison blocks, the P-bit output of the k-th block for storing the boundaries of the intervals, where K = 1, 2, ..., K, is connected to the P-bit input “Upper boundary” of the k-th block of comparison. The “Comparison Result” output of the k-th comparison block is connected to the k-th inverse input of the priority encoder, the nth inverse output of which, where n = 1, 2, ..., N, is connected to the input of the nth inverter. The input of the selection of the first selector-multiplexer is connected to the control input of the random number source and is the control input of the generator, the first N-bit information input of the first selector-multiplexer is the first N-bit address input of the generator, the N-bit output of the first selector-multiplexer is connected to N- bit address input of random access memory, the inverse inputs “Read / write” and “Choice of crystal” which are respectively the first input “Read / write” and the first input “Select p crystal "generator. Moreover, the M-bit output of random access memory, where M≥2 is the number of bits sufficient to represent the maximum value from the number of values that make up a given set of generated values, is the M-bit output "Result" of the generator, the M-bit information input of the operational the storage device is an M-bit information input of the generator. In this case, the P-bit information input of the k-th interval boundary storage unit is the k-th P-bit information input of the generator, the n-th bit of the N-bit information input of the second register is connected to the inverse output of the n-th inverter, and the N-bit output the second register is connected to the N-bit input of the block of probabilities of transitions, the N-bit correction output of which is connected to the N-bit correction input of the block of values of transition probabilities, the control input of which is connected to the relay output of the transition probability checking unit, the N-bit direct output of which is connected to the N-bit direct output of the transition probability correction block and is connected to the second N-bit information input of the first selector-multiplexer and to the second N-bit information input of the second selector - a multiplexer, the first N-bit input of which is the second N-bit address input of the generator, and its N-bit output is connected to the N-bit information input of the first register, N-bit the output of which is connected to the N-bit address inputs of each of the K blocks for storing the boundaries of the intervals, the corresponding inverse inputs of which are “Crystal Choice” and “Read / Write” which are interconnected and are respectively the second input “Crystal Choice” and the second input “Read / record "generator. The input of the selection of the second selector-multiplexer is connected to the control input of the random number source, the initialization inputs of the first and second registers are the first and second input “Setup” of the generator, and the reset inputs of the first and second registers are combined and are the input “Zero” of the generator.

The unit for checking the values of transition probabilities intended for preliminary analysis (selection) of data on the true values of the probabilities of transitions of a random process from state to state and deciding on the mathematical nature of these data - data characterizing the values of the probabilities of transitions are identified (determined) unambiguously or ambiguously (incompletely, contradictory) and need verification, as well as for recording data characterizing the values of the transition probabilities and the conversion of these data from the parallel code into the serial one, consists of a selector of transition probability values and a transition probability value converter, the N-bit output of which is the N-bit corrective output of the transition probability value verification unit, the transfer output of the transition probability value converter is the control output of the transition probability value verification block, allowing the output of the transition probability value converter is connected to the inverse enable input of the value selector of transitions, the N-bit output of which is the N-bit direct output of the block of probabilities of transitions, the prohibiting input of the converter of values of transition probabilities is connected to the inhibiting output of the selector of values of transition probabilities, the N-bit input of which is connected to the N-bit input of the converter of values of transition probabilities and is the N-bit input of the transition probability checking unit.

The block of values of transition probabilities intended to transform the initial data (values of the probabilities of transitions of a random process from state to state) given in an ambiguous (incomplete, inconsistent) form to a form that allows reliable (unambiguous, complete, consistent) identification and interpretation of values of transition probabilities random process from state to state, for recording and storing verified results of analysis of transition probability values, as well as for converting these x of data from serial to parallel code, consists of a programmable computer and a storage element, while the N-bit input I of the programmable computer is an N-bit correction input of the block of probabilities of transitions, the input resolution of the outputs of the programmable calculator is a control input of the block of values of transition probabilities , N outputs of the programmable calculator are connected to the corresponding N inputs of the storage element, the N-bit output of which is N-bit direct output of the block of values of transition probabilities 12.

Due to the new set of essential features, by introducing a block of transition probability values that provides preliminary identification (selection) of ambiguously (inaccurate, incomplete) identifiable transition probabilities and deciding on their mathematical nature, as well as a block of correction of transition probabilities providing a record, storing the results of the analysis of the values of transition probabilities and the mathematically correct computational transformation (recognition) of these values With the use of neuromathematical methods, in the inventive random sequence generator, it is possible to increase the reliability of the generated sequence of given values of a data set by providing the possibility of generating a sequence from a given set of values, taking into account the presence of not only probabilistic, but also ambiguous (incomplete, contradictory) relationships of each successive value with the previous one.

The claimed device is illustrated by drawings, in which:

in FIG. 1 is a block diagram of a random sequence generator;

in FIG. 2 is a block diagram of a block for verifying transition probabilities 11;

in FIG. 3 is a block diagram of a correction block of transition probability values 12;

in FIG. 4 is a block diagram of a comparison unit.

The random sequence generator (see Fig. 1) consists of the first selector-multiplexer 1, the second selector-multiplexer 2, the first register 3, the source of random numbers 4, random access memory 5, K blocks of storage of the boundaries of the intervals 6 ₁ -6 _K , K comparison units 7 ₁ -7 _K , priority encoder 8, N inverters 9 ₁ -9 _N , second register 10, unit for checking probability values of transitions 11 and block for correction of values of transition probabilities 12.

) и «Выбор кристалла» 51 (вход

) которого являются соответственно первым входом «Чтение/запись» 02 и первым входом «Выбор кристалла» 04 генератора. Причем М-разрядный выход 55 (выход для разрядов C₁-С_М) оперативного запоминающего устройства 5 является М-разрядным выходом «Результат» 013 генератора, М-разрядный информационный вход 53 (вход для разрядов D₁-D_M) оперативного запоминающего устройства 5 является М-разрядным информационным входом 03 генератора. При этом Р-разрядный информационный вход 63_k (вход для разрядов D₁-D_P) k-го блока хранения границ интервалов 6_k является k-м Р-разрядным информационным входом 09_k генератора, n-й разряд N-разрядного информационного входа 101 второго регистра 10 соединен с инверсным выходом 92_n n-го инвертора 9_n, а N-разрядный выход 104 второго регистра 10 соединен с N-разрядным входом 111 блока проверки значений вероятностей переходов 11, N-разрядный корректировочный выход 113 которого подключен к N-разрядному корректировочному входу 121 блока коррекции значений вероятностей переходов 12, контрольный вход 123 которого соединен с контрольным выходом 114 блока проверки значений вероятностей переходов 11, N-разрядный прямой выход 112 которого соединен с N-разрядным прямым выходом 122 блока коррекции значений вероятностей переходов 12 и подключен ко второму N-разрядному информационному входу 0012 (входу для разрядов B₁-B_N) первого селектора-мультиплексора 1 и ко второму N-разрядному информационному входу 22 (входу для разрядов B₁-B_N) второго селектора-мультиплексора 2, первый N-разрядный вход 21 которого является вторым N-разрядным адресным входом 05 генератора, а его N-разрядный выход 24 соединен с N-разрядным информационным входом 31 первого регистра 3, N-разрядный выход 34 которого соединен с N-разрядными адресными входами 62₁-62_K K блоков хранения границ интервалов 6₁-6_K, соответствующие инверсные входы «Выбор кристалла» 61₁-61_K (входы

) и «Чтение/запись» 64₁-64_K (входы

) которых объединены между собой и являются соответственно вторым входом «Выбор кристалла» 08 и вторым входом «Чтение/запись» 010 генератора. Вход выбора 23 (вход SE) второго селектора-мультиплексора 2 соединен с управляющим входом 41 источника случайных чисел 4, входы инициализации 33 и 103 (входы С) первого 3 и второго 10 регистров являются соответственно первым 06 и вторым 012 входом «Установка» генератора, а входы сброса 32 и 102 (входы R) первого 3 и второго 10 регистров объединены и являются входом «Обнуление» 011 генератора.The elements are interconnected as follows (see Fig. 1). The random number P-bit output 42 of the random number source 4 is connected to the Random number P-bit inputs 71 ₁ -71 _K K comparison blocks 7 ₁ -7 _K , the P-bit output 65 _{k of the} kth interval storage unit 6 _k , where k = 1, 2, ..., K, is connected to the P-bit input “Upper boundary” 72 _{k of the} k-th comparison block 7 _k . Comparison Result output 73 _{k of the} kth comparison block 7 _{k is} connected to the k-th inverse input 81 _{k of the} priority encoder 8, the n-th inverse output 82 _{n of} which, where n = 1, 2, ..., N, is connected to the input 91 _{n of the} n-th inverter 9 _n . The selection input 0013 (input SE) of the first selector-multiplexer 1 is connected to the control input 41 of the random number source 4 and is the control input 07 of the generator, the first N-bit information input 0011 (input for bits A ₁ -A _N ) of the first selector-multiplexer 1 is the first N-bit address input 01 of the generator, N-bit output 0014 (output for bits Q ₁ -Q _N ) of the first selector-multiplexer 1 is connected to N-bit address input 52 (input for bits A ₁ -A _N ) of random access memory devices 5, inverse read / write inputs 54 (entrance

) and “Crystal Choice” 51 (input

) which are respectively the first input “Read / Write” 02 and the first input “Choice of crystal” 04 of the generator. Moreover, the M-bit output 55 (output for bits C ₁ -C _M ) of random access memory 5 is the M-bit output "Result" 013 of the generator, M-bit information input 53 (input for bits D ₁ -D _M ) of random access memory 5 is an M-bit information input 03 of the generator. In this case, the P-bit information input 63 _k (input for bits D ₁ -D _P ) of the k-th block for storing the boundaries of the intervals 6 _k is the k-th P-bit information input 09 _{k of the} generator, the n-th bit of the N-bit information input 101 of the second register 10 is connected to the inverse output 92 _{n of the} n-th inverter 9 _n , and the N-bit output 104 of the second register 10 is connected to the N-bit input 111 of the block for checking the probabilities of transitions 11, the N-bit correction output 113 of which is connected to N -bit correction input 121 of the block correction values of probability th transitions 12, the control input 123 of which is connected to the control output 114 of the block of probabilities of transitions 11, the N-bit direct output 112 of which is connected to the N-bit direct output 122 of the block of correction of values of transition probabilities 12 and connected to the second N-bit information input 0012 (input for bits B ₁ -B _N ) of the first selector-multiplexer 1 and to the second N-bit information input 22 (input for bits B ₁ -B _N ) of the second selector-multiplexer 2, the first N-bit input 21 of which is the second N-discharge by the address address 05 of the generator, and its N-bit output 24 is connected to the N-bit information input 31 of the first register 3, the N-bit output 34 of which is connected to the N-bit address inputs 62 ₁ -62 _K K interval storage units 6 ₁ -6 _K , corresponding inverse inputs “Choice of crystal” 61 ₁ -61 _K (inputs

) and Read / Write 64 ₁ -64 _K (inputs

) which are interconnected and are respectively the second input "Choice of crystal" 08 and the second input "Read / write" 010 generator. The selection input 23 (input SE) of the second selector-multiplexer 2 is connected to the control input 41 of the random number source 4, the initialization inputs 33 and 103 (inputs C) of the first 3 and second 10 registers are respectively the first 06 and second 012 input "Installation" of the generator, and reset inputs 32 and 102 (inputs R) of the first 3 and second 10 registers are combined and are the input “Zeroing” 011 of the generator.

The number "N, (N = [log ₂ K]; N≥1)" (blocks, bits, inputs, outputs, etc.) is determined in accordance with the number of binary bits sufficient to address the elements of a given set of generated random sequence values (i.e. for addressing data set elements) and, as a rule, ranges from 2 (two) to 10 (ten).

The number "K, (K≥2)" characterizes the maximum possible power of a given set of generated values of a random sequence (ie, the number of elements in a given data set) and, as a rule, ranges from 2 (two) to 500 (five hundred).

The number "M, (M≥2)" characterizes the number of binary bits sufficient to represent the maximum value from the number of values that make up a given set of generated values of a random sequence (ie, to represent the values of the elements of a given data set) and, as a rule , is from 2 (two) to 10 (ten).

The number "P, (P> N)" characterizes the capacity of the information inputs of the generator and is determined in accordance with the number greater than the number of binary bits sufficient to address the elements of a given set of generated values of a random sequence and, as a rule, is from 3 (three) up to 11 (eleven).

The transition probability checking unit 11 shown in FIG. 2, is intended for preliminary analysis (selection) of data on the true values of the probabilities of transitions of a random process from state to state and making decisions about the mathematical nature of these data - data characterizing the values of the probabilities of transitions are identified (defined) unambiguously or ambiguously (incomplete, contradictory) and need in verification, as well as for recording data characterizing the values of the transition probabilities and converting this data from parallel to serial code.

селектора значений вероятностей переходов 11.1, N-разрядный выход которого является N-разрядным прямым выходом 112 блока проверки значений вероятностей переходов 11. Запрещающий вход DST преобразователя значений вероятностей переходов 11.2 подключен к запрещающему выходу МТ селектора значений вероятностей переходов 11.1, N-разрядный вход которого соединен с N-разрядным входом преобразователя значений вероятностей переходов 11.2 и является N-разрядным входом 111 блока проверки значений вероятностей переходов 11.The block of checking probabilities of transitions 11 (Fig. 2) consists of a selector of values of probabilities of transitions 11.1 and a converter of values of probabilities of transitions 11.2, the N-bit output of which is the N-bit correction output 113 of the block of checking probabilities of transitions 11, the output of the transmission TxD of the converter of probability values transitions 11.2 is the control output 114 of the block of probabilities of transitions 11, allowing the DSR output of the converter of values of the probabilities of transitions 11.2 is connected to the inverse decisive input

the transition probability value selector 11.1, the N-bit output of which is the N-bit direct output 112 of the transition probability value checking unit 11. The inhibit input DST of the transition probability value converter 11.2 is connected to the inhibit output MT of the transition probability value selector 11.1, the N-bit input of which is connected with an N-bit input of the transition probability value converter 11.2 and is an N-bit input 111 of the transition probability value verification unit 11.

The selector of values of transition probabilities 11.1 of the block of checking the values of transition probabilities 11 is designed to carry out a preliminary analysis (selection) of data on the true values of the probabilities of transitions of a random process from state to state and to decide on the mathematical nature of these data - data characterizing the values of transition probabilities are identified (defined ) unambiguously or ambiguously (incomplete, contradictory) and need verification. The selector of transition probability values 11.1 can be technically implemented as a commercially available selector on CMOS structures with one inverse enable input and one inhibit output, based on an 564 series integrated circuit (for example, SEL K564KP2), as shown in the literature [Shilo V .P. Popular CMOS chips. Directory. - M .: Hot line Telecom, 2001 .-- 116 p. S. 68-73].

The converter of the values of the probabilities of transitions 11.2 of the block of checking the values of the probabilities of transitions 11 is intended for recording data on the values of the probabilities of transitions of a random process from state to state and converting these data from parallel to serial code. The converter of transition probability values 11.2 can be technically implemented as a chip of the programmable parallel interface КР580ВВ55 described in [Microprocessor technology. Version 1.0 [Electronic resource]: electron, textbook. allowance / VB Molodetsky, M.V. Krivenkov, A.N. Pakhomov et al. - Electron, Dan. - Krasnoyarsk: IPK SFU, 2008 .-- 126 p. S. 41-43, fig. 8.5]

The transition probability correction value block 12 shown in FIG. 3, is intended to transform the initial data (values of the probabilities of transitions of a random process from state to state) specified in an ambiguous (incomplete, contradictory) form to a form that allows one to reliably (uniquely, completely, consistently) identify and interpret the probabilities of transitions of a random process from a state to a state for recording and storing verified results of analysis of transition probability values, as well as for converting this data from serial to parallel code.

The block of correction of the values of the transition probabilities 12 (Fig. 3) consists of a programmable calculator 12.1 and a storage element 12.2. In this case, the N-bit input I of the programmable calculator 12.1 is the N-bit correction input 121 of the block of correction of values of transition probabilities 12. The input OE _{I of the} output resolution A of the programmable calculator 12.1 is the control input 123 of the block of correction of values of the probabilities of transitions 12, N of the outputs A (A ₁ -A _N ) of programmable calculator 12.1 connected to the corresponding N inputs 12.2-1 ₁ -12.2-1 _N memory element 12.2, the N-bit output of which is N-bit direct output 122 of the block correction values of transition probabilities 12.

Programmable calculator 12.1 of the block of values of transition probabilities 12 is designed to carry out the procedure for converting the initial data (probabilities of transitions of a random process from state to state) specified in an ambiguous (incomplete, inconsistent) form to allow for reliable (unambiguous, complete, consistent) identification and interpret the values of the probabilities of transitions of a random process from state to state. Programmable calculator 12.1 is a commercially available microprocessor section (MPS or MPS - Micro-Processingoring Section) of the type MPS K1804BC1, described, for example, in [Grishin G.G., Moshkov A.A., Olshansky O.V. and other Microprocessors: A reference guide for developers of ship REA. 2nd ed. - L .: Shipbuilding, 1988.S. 243-281, Fig. 7.1 and 7.2] and in [Ugryumov EP Digital circuitry: textbook. manual for universities. - 3rd ed., Revised. and additional - St. Petersburg: BHV-Petersburg, 2010 .-- 816 p., S. 371-376, fig. 6.14].

The storage element 12.2 of the block of values of transition probabilities 12 is designed to record and store the verified results of the analysis of the values of the transition probabilities, as well as to convert this data from serial to parallel code. The storage element 12.2 can be technically implemented on the basis of a commercially available programmable dynamic random access memory with N inputs and N-bit output, in accordance with the description presented in [Fundamentals of Electronics: textbook for STR / OV Milovzorov, I.G. Punk - 5th ed., Revised. and add. - M .: Publishing house Yurayt, 2016 .-- 407 p. S. 229-231, Fig. 4.3.2].

The first selector-multiplexer 1, which is part of the general block diagram of a random sequence generator, is designed to switch one of two groups of signals to its N-bit output: from the first N-bit information input 0011 (input for bits A ₁ -A _N ) or second N-bit information input 0012 (input for bits B ₁ -B _N ). The construction scheme of the first selector-multiplexer 1 is known, it can be technically implemented on the basis of a commercially available N-bit multiplexer, as shown in [Ugryumov EP Digital circuitry: textbook. manual for universities. - 3rd ed., Revised. and add. - St. Petersburg: BHV-Petersburg, 2010. - 816 p., S. 94-95].

The second selector-multiplexer 2, which is part of the general block diagram of a random sequence generator, is designed to switch one of two groups of signals to its N-bit output: from the first N-bit input 21 (input for bits A ₁ -A _N ) or from the second N-bit information input 22 (input for bits B ₁ -B _N ). He is responsible for recording new values (for this step) of the upper boundaries of the intervals into which the set of addresses of a given data set is divided, determined at each subsequent step by the given verified (using a neural network algorithm) probabilities of transitions of a random process from state to state [1]. The construction scheme of the second selector-multiplexer 2 is known and similar to the scheme of the first selector-multiplexer 1. It can be technically implemented on the basis of a commercially available N-bit multiplexer, as shown in [Ugryumov EP Digital circuitry: textbook. manual for universities. - 3rd ed., Revised. and add. - St. Petersburg: BHV-Petersburg, 2010. - 816 p., S. 94-95].

The first register 3, which is part of the general structural diagram of a random sequence generator, is designed to register and store binary codes that determine the generation of a sequence of verified (using a neural network algorithm) values from a given set of values, taking into account the existence of a connection between each next value and the previous one. He is responsible for recording and storing the values of new (for each subsequent step) upper bounds of intervals, the value of which dynamically changes according to the methods of Markov chains, depends on the probability of the transition of a random process from state to state and corresponds to the values of the probabilities required at this step to observe the corresponding elements of a given set data. The description of the work and the scheme of such registers are known and are given, for example, in the book [O. Averchenkov. Circuitry: equipment and programs. - M .: DMK Press, 2012. - 588 p., S. 443-445].

The source of random numbers 4, which is part of the general block diagram of a random sequence generator, is designed to generate P-bit random numbers, is known, and can be technically implemented, as shown, for example, in [Ugryumov EP Digital circuitry: textbook. manual for universities. - 3rd ed., Revised. and add. - St. Petersburg: BHV-Petersburg, 2010. - 816 p., S. 260-261].

Random access memory 5, which is part of the general structural diagram of a random sequence generator, is designed to store the values of the elements of a given data set. The scheme for constructing random access memory is known; it can be technically implemented on the basis of a commercially available random access memory, as shown in [Averchenkov O.E. Circuitry: equipment and programs. - M.: DMK Press, 2012. - 588 p., S. 246-247].

Blocks for storing the boundaries of the intervals 6 ₁ -6 _K included in the general structural diagram of the random sequence generator are intended for storing binary codes that determine the boundary values of the probability of occurrence of the corresponding elements of a given data set (data set in a given interval). They are made in the form of random access memory, the structure of their construction is known, they can be technically implemented on the basis of commercially available random access memory, as shown in [Averchenkov O.E. Circuitry: equipment and programs. - M.: DMK Press, 2012. - 588 p., S. 246-247].

The comparison blocks 7 ₁ -7 _K included in the general block diagram of the random sequence generator are used to compare the random value generated by the random number source and the value at the output of the corresponding register, as well as to generate the comparison result. Comparison unit 7 _k may be technically implemented as shown in FIG. 4, contains a comparator 7.1 _k , a P-input element OR NOT 7.2 _k and an element OR 7.3 _k whose first input 7.3 _k -1 is connected to the output "Inequality" 7.1 _k -3 (output A> B) of the comparator 7.1 _k . The second input 7.3 _k -2 of the OR element 7.3 _{k is} connected to the inverse output 7.2 _k -2 of the P-input element OR NOT 7.2 _k , the output 7.3 _k -3 of the OR element 7.3 _k is the output “Comparison result” 73 _k of the 7 _k comparison unit. The P inputs (inputs A ₁ -A _P ) of the first group 7.1 _k -1 of the information inputs of the comparator 7.1 _k are the P-bit input "Random number" 71 _k of the comparison unit 7 _k , P inputs (inputs B ₁ -B _P ) of the second group 7.1 _k -2 information inputs of the comparator 7.1 _{k are} connected to the corresponding inputs 7.2 _k -1 ₁ -7.2 _k -1 _{P of the} P-input element OR NOT 7.2 _k and are the second P-bit information input “Upper boundary” 72 _k of the comparison block 7 _k .

The comparator 7.1 _k of the comparison unit 7 _{k is} intended for comparing two P-bit numbers and generating a comparison result. The job description and the comparator circuit are known, for example, are given in the book [O. Averchenkov. Circuitry: equipment and programs. - M .: DMK Press, 2012. - 588 p., S. 428-429].

The OR-NOT 7.2 _k element of the 7 _k comparison block is designed to generate a logic zero on its output if all logical bits of the second P-bit input “Upper boundary” 72 _k of the 7 _k comparison block are set to logical units. The OR-NOT 7.2 _k element can be technically implemented on the basis of a commercially available OR-NOT element, as shown in [Ugryumov EP Digital circuitry: textbook. manual for universities. - 3rd ed., Revised. and add. - St. Petersburg: BHV-Petersburg, 2010. - 816 p., S. 308-309].

The OR element 7.3 _k of the comparison unit 7 _{k is} designed to generate a logical unit value at its output, if one of its inputs has a logical unit value, the implementation scheme of such an OR element is known and described, for example, in [Averchenkov O.E. Circuitry: equipment and programs. - M.: DMK Press, 2012. - 588 p., S. 39-40].

Priority encoder 8, included in the general scheme of the random sequence generator, is designed to convert the value of logical zero at one of its inputs into the corresponding binary code at its output, and the conversion is carried out taking into account the priorities determined by the input number. The priority encoder implementation scheme is known and described in detail, for example, in [Averchenkov O.E. Circuitry: equipment and programs. - M .: DMK Press, 2012. - 588 p., S. 414-418].

Inverters 9 ₁ -9 _N included in the general circuit of the random sequence generator are designed to invert signals from the inverse outputs of the priority encoder. The implementation scheme of the inverter is known and described in detail, for example, in [Averchenkov O.E. Circuitry: equipment and programs. - M.: DMK Press, 2012. - 588 p., S. 426].

The second register 10, included in the general scheme of the random sequence generator, is designed to store binary codes that determine the probability of occurrence of the corresponding elements of a given data set. He is responsible for recording and storing the values of the previous (for the last step) upper boundaries of the intervals (obtained taking into account the presence of not only probabilistic, but also ambiguous (incomplete, contradictory) relationships of each successive value with the previous one), the value of which dynamically changes according to the methods of Markov chains, depends on the probability of the transition of a random process from state to state and corresponds to the values of the probabilities required at the last step for observing the corresponding elements of a given data set. It is similar to the first register 3, a description of the work and the scheme of such registers are known and are given, for example, in the book [O. Averchenkov. Circuitry: equipment and programs. - M .: DMK Press, 2012. - 588 p., S. 443-445].

In the claimed device, the generation of given values of a data set taking into account both probabilistic and ambiguous (incomplete, contradictory) relationships of each successive value with the previous one is carried out in stages, the first step is to take into account the probabilistic relationship of each successive value with the previous one, implemented on the basis of the distribution law, which is set by indicating the required probability of occurrence of the corresponding element of a given data set. In this case, the approach [2] is applied, based on the use of a source of random numbers distributed uniformly in the range [0; 1). This range is divided into a set of intervals, the number of which corresponds to the number of elements in a given data set. The values of the intervals correspond to the values of the required probabilities of observation of the corresponding elements of a given data set. The probability of a random number generated by a random number source falling into each interval is equal to its length. The interval number is used as the address for retrieving an element of a given data set from the random access memory, and for setting intervals, their upper boundaries are indicated.

The initial task of the initial probabilities of the appearance of elements of a given data set, at the first step - without taking into account the presence of a probabilistic connection of each next value with the previous one, is carried out as follows.

K - количество элементов заданного набора данных, а В={b₁, b₂, …, b_k, …, b_K} - множество соответствующих значений начальных верхних границ интервалов. Тогда начальное значение верхней границы k-го интервала будет равно сумме значений вероятностей появления элементов из заданного набора данных от 1-го до k-го:Let H = {h ₁ , h ₂ , ..., h _k , ..., h _K } be the set of required probabilities of occurrence of elements of a given data set, where

K is the number of elements of a given data set, and B = {b ₁ , b ₂ , ..., b _k , ..., b _K } is the set of corresponding values of the initial upper boundaries of the intervals. Then the initial value of the upper boundary of the kth interval will be equal to the sum of the values of the probabilities of the appearance of elements from a given data set from the 1st to the kth:

Thus, the range [0; 1) at the first generation step it will be divided into the following intervals:

A P-bit random number source with a uniform distribution law is used. In this case, the P-bit binary code generated at the output of the random number source and the P-bit binary code used to specify the initial (for the first step) upper boundary of the interval are considered as numbers from the range [0; 1) without specifying the integer part.

For example, a set of required probabilities of the appearance of elements of a given data set is given H = {0.125; 0.125; 0.25; 0.5}. Then the values of the upper boundaries of the intervals will be equal to 0.125, 0.25, 0.5, and 1, respectively. In accordance with the rules for translating [3] the correct decimal fractions into binary representation, these values in the four-digit code are represented, respectively, in the form of numbers 0.0010, 0, 0100, 0.1000, 0.1111. And only the fractional part of these numbers is entered into the device: the values 0010, 0100,1000 and 1111, respectively.

Similarly, if the source of random numbers generated a value of 1101 (in decimal 0.8125), then, representing this value as a fractional part of a number from the range [0; 1), i.e. as 0.1101, and given the many initial upper boundaries of the intervals from the previous paragraph, it is clear that a random value fell into the interval limited by the numbers 0.1000 and 0.1111.

In order for the random sequence generator to be able to model discrete random processes occurring in real systems, taking into account the probabilistic (at the first stage) and taking into account the ambiguous, incomplete and contradictory (at the second stage) relationship between the states of the random process (between the generated values of a given data set), in accordance with the theory of Markov processes [4], set the initial probability values of transitions of a random process from state to state.

At the same time, at each subsequent step in the functioning of the generator, the probabilities of the appearance of elements of a given data set will have new values of the upper boundaries of the intervals determined in accordance with the Markov model, and random values generated at each new step will fall into a new one (only for this step) interval. This step-by-step refinement, identification of the values of the probability of transitions of the Markov chain [4] and the corresponding step-by-step refinement (step-by-step correction) of the set of upper boundaries of the intervals allows one to obtain element values from a given data set taking into account the presence of a probabilistic and ambiguous (incomplete and contradictory) relationship of each successive value with the previous .

Taking into account not only the probabilistic, but also the ambiguous (incomplete and inconsistent) connection of each successive value with the previous one, implemented in the proposed random sequence generator, is the second stage, which is based on the known results of studies in the theory of artificial neural networks described in [1, 5-9]. An analysis of [1, 5–9] allows one to form a mathematically correct algorithm for reducing incompletely defined, ambiguously (inconsistently) identified source data (probability values of Markov chain transitions and corresponding values of the upper bounds of intervals) to the nearest complete (unambiguous given) set. Thus, in the framework of modeling discrete random processes formed taking into account both quantitatively (probabilistically) and qualitatively (ambiguously, incompletely, and contradictory) identified relationships of each successive value with the previous one, a number of characteristics of the generated process are modeled on the basis of parametrically (probabilistically) given initial data, by traditional methods, and modeling is ambiguous, incomplete and contradictory given parameters of relations of each next value with the previous one (elements of the set the probabilities of transitions of a random process from state to state, which determine the value of the upper boundary of the interval), by successive transformations using methods of the theory of artificial neural networks, reduces to the possibility of them with respect to parametric modeling, i.e. a transition is made from the ambiguous, incomplete and contradictory task to the parametric one.

It is known [1, 5–9] that from the point of view of verifying the probability values of transitions of a Markov chain, it is possible to recognize (determine) these values given both quantitatively and qualitatively (ambiguously, incompletely, and contradictory). This possibility is realized using neural network computational methods and algorithms that make it possible, through successive neural network transformations, to make the transition from ambiguously, incompletely, and inconsistently recognized (defined) values of transition probabilities to a form suitable for an unambiguous decision on the values of these probabilities.

Moreover, the probability values of Markov chain transitions can be verified on the basis of mathematical decision-making methods in poorly structured problems — neural network computational methods and algorithms that can quite easily be implemented in hardware. Neural network computational methods and algorithms work on the basis of expert estimates, and to solve the problem of combining the opinions of experts whose knowledge is used, for example, to verify transition probability values, one of the typical computational algorithms of the theory of artificial neural networks is used - a neural network extrapolating computational algorithm, or, so called extrapolating neural network (ENS), which is a type of well-known computational models of associative memory [5-9].

A computational neural network algorithm (extrapolating neural network) of this class consists of two layers of calculators (neurons) - the input layer U _a and the output layer U _b . The input layer U _a is composed of N _Rin neurons possessing a set of forward and reverse links with N _O neurons of the output layer U _b, wherein the number of input and output images N corresponds to the code addressing elements of a data set equal to N = [log ₂ K] and depends on the the number of binary bits sufficient for addressing the elements of a given set of generated values of a random sequence, from the number of experts and the corresponding number of inputs of devices for the hardware implementation of the neural network algorithm.

In our case, N can take values from 2 (two) to 10 (ten), corresponding to the number of inputs of the microprocessor section of the MPS K1804BC1, on the basis of which the programmable calculator 12.1 of the block of correction of values of transition probabilities 12 is built.

In the ENS, the so-called cognitive map is used, which is completely defined by the matrix of connections and characterizes the cause-effect relations of the current values of the transition probabilities, which influence the obtaining of unambiguous (reliable) results of the generation of random sequence values. The cognitive map is formulated by experts, the principle of forming cognitive maps is described in detail in [5, 7]. At the same time, N branches of the algorithm are responsible for transforming the opinions of experts on the ambiguously (incomplete and contradictory) recognized (defined) value of the probabilities of transitions to a form that allows one to reliably (uniquely, completely, consistently) identify and interpret the probabilities of transitions of a random process from state to state.

An input image is received at the input of a computational neural network algorithm (ENS) - data characterizing the values of transition probabilities and recognized (determined) both quantitatively and qualitatively (ambiguous, incomplete and contradictory). It is determined which of the data characterizing the values of the transition probabilities is quantitatively recognized at a given time, and which data is identified ambiguously (incomplete and contradictory). In order to verify the values of transition probabilities, it is necessary, mathematically correct, using the ENS, to convert the data recognized ambiguously (incompletely).

The stages of functioning of a computational neural network algorithm (ENS) are described in detail, algorithmically and analytically in [5]. At the output of a computational neural network algorithm (ENS), we have an output image - data that reliably (unambiguously, completely, consistently) characterizes the integrated opinion of experts about whether the probability values of transitions belong to the space of reliable, verified values.

The computational neural network algorithm considered in [1, 6, 8] and described in detail in [5] makes it possible to eliminate the uncertainty (ambiguity, incompleteness, and inconsistency) of data characterizing the transition probabilities and allows one to unambiguously recognize (verify) the true transition probabilities of the generated random process from state to state, and ultimately, increase the reliability of the formation of the values of the elements of a random process that characterizes the real behavior of complex computing with systems - when the relationship of the parameters of a random process, the relationship of each of the next sequence of generated values with the previous value has both quantitative (probabilistic) and qualitatively (ambiguous, incomplete and contradictory) expressed physical meaning.

In other words, an analysis of the computational neural network algorithm considered in [1, 6, 8] and described in detail in [5] allows us to conclude that it is technically feasible to implement a complete and consistent identification of the essential parameters of the generated stream of random events (with quantitative, parametric (probabilistic) and ambiguous , incomplete and contradictory given parameters) - the values of the transition probabilities and the corresponding values of the upper boundaries of the intervals. This allows to reduce the uncertainty, and, therefore, to increase the reliability of the generated sequence of given values of the data set.

With this in mind, the claimed device generates set values of the data set taking into account the presence of not only probabilistic, but also ambiguous (incomplete and contradictory) connection of each next value with the previous one.

The technical implementation of the principle of increasing the reliability of recognition of the values of transition probabilities and the corresponding values of the upper boundaries of the intervals in the claimed device is carried out by introducing a preliminary analysis (identification) of ambiguously (incompletely and contradictory) identifiable elements of the set of values of transition probabilities, as well as verifying these values using neuromathematical methods to the form , which allows to uniquely (fully, consistently) identify and interpret these values (in the claimed device, respectively, are implemented as part of a block for checking the values of the probabilities of transitions 11 and a block for correcting the values of the probabilities of transitions 12).

The random sequence generator operates as follows.

In the initial position, on the control input 07, first 06 and second 012 inputs “Setting”, the values of logical zero are set, and on the first 02 and second 010 inputs “Read / write” and on the first 04 and second 08 inputs “Select crystal” - logical values units. The generator operates in the following modes: preparation for generation mode; generation mode.

The operating mode of the generator, taking into account not only probabilistic, but also ambiguous (incomplete and contradictory) relationships between the states of the random process, is determined by the combination of signals at the control input 07, first 06 and second 012 inputs “Installation”, first 02 and second 010 inputs “Read / record ”, as well as on the first 04 and second 08 inputs of“ Crystal Choice ”. To put the device into preparation mode, it is necessary to control the input 07 of the generator, the first 04 and second 08 inputs “Choice of a crystal”, the first 02 and second 010 inputs “Read / write” to submit the values of logical zero, and the first 06 and second 012 inputs “Installation "- the value of the logical unit.

In the generation mode, at the control input of the generator 07, the first 02 and second 010 inputs “Read / write”, the values of the logical unit are set, and at the first 04 and second 08 inputs “Choice of the crystal” and the first 06 and second 012 inputs “Set” - the value of the logical zero.

In the mode of preparing the generator for operation, the following steps are performed.

The first step is to enter the set A = { a ₁ , a ₂ , ..., a _K } the values of the elements of a given data set into the random access memory, while:

0≤ a _k ≤2 ^M -1 - element of a given data set, where

M≥2 - the number of binary bits sufficient to represent the values of the elements of a given data set;

K≥2 - the number of elements in a given data set;

N≥1 - the number of bits that is sufficient to address the elements of the data set.

The second step is to set the set B = {b ₁ , b ₂ , ..., b _K } of the values of the initial upper boundaries of the intervals into which the whole set of addresses of a given data set A is divided.

The third step is to set the set quantitatively or C = {s ₁ , s ₂ , ..., c _K } or ambiguously (incompletely and inconsistently) the set values of the new (for this step) upper bounds of the intervals into which the set of addresses of the given data set A is divided, determined at each subsequent step by the probabilities of transitions of a random process from state to state [4].

и 54

значений логического нуля по первым входам «Выбор кристалла» 04 и «Чтение/запись» 02 соответственно. Затем, по первому N-разрядному адресному входу 01 генератора на первую группу информационных входов 0011 (группу входов A₁-A_N) первого селектора мультиплексора 1 подается N-разрядный адрес, по которому должно быть записано значение второго элемента а ₂, а по М-разрядному информационному входу 03 генератора на информационные входы 53 (входы D₁-D_M) оперативного запоминающего устройства 5 подают значение элемента а ₂ и, путем установки значений логического нуля на первых входах «Выбор кристалла» 04 и «Чтение/запись» 02, записывают значение а ₁ в оперативное запоминающее устройство 5. Аналогичным образом в оперативное запоминающее устройство 5 заносятся все K значений элементов заданного набора данных. После чего на первом входе «Чтение/запись» 02 генератора устанавливают значение логической единицы.The first step in preparing the generator for work includes the following steps. At the first N-bit address input 01 of the generator, the N-bit address is supplied to the first group of information inputs 0011 (group of inputs A ₁ -A _N ) of the first selector of multiplexer 1, at which the value of the first element a ₁ should be recorded. At the control input 07 of the generator, a logic zero value is set, which is fed to input 0013 (input SE) of the first selector-multiplexer 1, which leads to switching the address set at input 0011 (inputs A ₁ -A _N ) of the first selector-multiplexer 1, to N-bit address input 52 (input for bits A ₁ -A _N ) of random access memory 5. On the M-bit information input 03 of the generator to the information inputs 53 (inputs D ₁ -D _M ) of random access memory 5 is supplied the value of the first element a ₁ preset yes data, which is recorded in the random access memory 5 upon receipt of its inputs 51

and 54

logical zero values at the first inputs “Choice of a crystal” 04 and “Read / write” 02 respectively. Then, at the first N-bit address input 01 of the generator, the N-bit address is supplied to the first group of information inputs 0011 (group of inputs A ₁ -A _N ) of the first selector of multiplexer 1, at which the value of the second element a ₂ should be written, and M -digit information input 03 of the generator to the information inputs 53 (inputs D ₁ -D _M ) of the random access memory 5 are supplied with the value of the element a ₂ and, by setting the logical zero values at the first inputs "Crystal Select" 04 and "Read / Write" 02, value is recorded in a oper ₁ vnoe storage device 5. Similarly, the random access memory 5 are recorded values of all elements K predetermined data set. Then, at the first input "Read / Write" 02 of the generator set the value of the logical unit.

и 64_k

каждого k-ого блока хранения границ интервалов 6_k. По окончании записи начальных значений верхних границ интервалов в соответствующие блоки хранения границ интервалов на вторых входах «Выбор кристалла» 08 и «Чтение/запись» 010 устройства устанавливают значение логического нуля.The second step in preparing the generator for operation is as follows. On K P-bit information inputs "Upper boundary" 09 ₁ -09 _K generator set the initial values of the upper boundaries of the intervals. At the same time, input 09 _{1 is} set to b ₁ , which is fed to the group of information inputs 63 ₁ (group D ₁ -D _P ) of the interval boundary storage unit 6 ₁ , and input 09 ₂ is set to b ₂ , which is fed to the group of information inputs 63 ₂ blocks for storing the boundaries of intervals 6 ₂ , at the input 09 _K - the value of b _K , which is fed to the group of information inputs 63 _{K of the} block for storing borders of intervals 6 _K. To write the initial values of the upper boundaries of the intervals to the storage blocks of the boundaries of the intervals 6 ₁ -6 _K at the second inputs “Choice of crystal” 08 and “Read / write” 010 devices set the value of the logical unit, which is fed to the inputs 61 _k

and 64 _k

each k-th block storage interval boundaries 6 _k . Upon completion of the recording of the initial values of the upper boundaries of the intervals in the corresponding blocks for storing the boundaries of the intervals on the second inputs “Choice of crystal” 08 and “Read / write” 010 devices set the value of logical zero.

The third step of preparing the generator for operation is as follows. At the second N-bit address input 05 of the generator, the first N-bit input 21 (inputs of bits A ₁ -A _N ) of the second selector of multiplexer 2 is supplied with an N-bit address, at which the value of the first element should be written, which determines the new value of the upper boundary of this of the (first) interval, proceeding from the parametrically (quantitatively) or ambiguously (incomplete and contradictory) given probabilities of transitions of the generated random process from state to state. Similarly, in the second selector-multiplexer 2, all K new N-bit values are entered quantitatively or ambiguously (incompletely and inconsistently) given the upper boundaries of the intervals. At the control input 07 of the generator, a logical zero value is set, which is fed to input 23 (input SE) of the second selector-multiplexer 2, which leads to switching the address recorded in binary code and installed at input 21 of the second selector-multiplexer 2 to an N-bit information input 31 (input of registers D ₁ -D _N ) of the first register 3. In the mode of preparation of the generator for operation, the logical unit values are given to the reset inputs 32 and 102 (inputs R) of the first 3 and second 10 registers. The second N-bit information input 22 (input for bits B ₁ -B _N ) of the second selector-multiplexer 2 with N-bit direct outputs 112 and 122 of the blocks for checking the values of the probabilities of transitions 11 and correction of the values of the probabilities of transitions 12, respectively, is supplied with the previous (from the past step), or a verified quantitatively converted (using neural network algorithm), the value of the first element with _one of the plurality of values of the transition probabilities of a random process from state to state, which determines the new value of the upper boundaries of the interval. This value of the first element with _{1 is} written in the first register 3, and for recording new (for this step) values of the upper bounds of the intervals in the first register 3 at the first input “Installation” 06 of the device, the value of the logical unit is set, which is fed to the initialization input 33 (input C) of the first register 3. Upon completion of recording in the first register 3 new (for this step) values of the upper boundaries of the intervals in the first register 3 at the first input “Installation” 06 of the device, set the value of logical zero.

After the above steps, the generator is ready for operation.

In the generation mode, the operation of the device taking into account not only probabilistic, but also ambiguous (incomplete and contradictory) relationships between the states of a random process occurs as follows (see Fig. 1). The value of the logical unit is supplied to the control input 07 of the generator, which is fed to the input 0013 (input SE) of the first selector-multiplexer 1, which ensures switching of the verified address coming from the output 104 of the second register 10 through the block for checking the probabilities of transitions 11 and the correction block the probability values of the transitions 12 to the N-bit address input 52 (input for bits A ₁ -A _N ) of random access memory 5.

The source of random numbers 4, if there is a logical unit value at the control input 07 of the generator, generates a P-bit random value of the address, which goes simultaneously to the P-bit inputs "Random number" 71 ₁ -71 _K K comparison blocks 7 ₁ -7 _K , where comparing a random value of the address with the initial values of the upper boundaries of the specified intervals B = {b ₁ , b ₂ , ..., b _K } (see Fig. 4). If the received address value belongs to the kth interval, i.e. it is less than or equal to the value of the upper boundary of the kth interval, then the output of Inequality (output A> B) of comparators 7.1 ₁ -7.1 _k-1 forms the values of a logical unit, and at the outputs of Inequality of the other comparators the values of logical zero.

) шифратора приоритетов 8.The signals from the outputs “Inequality” of each comparator 7.1 ₁ -7.1 _K through the OR elements 7.3 ₁ -7.3 _K and the outputs “Compare result” 73 ₁ -73 _K K comparison blocks 7 ₁ -7 _K go to the corresponding inverse inputs 81 ₁ -81 _K (register inputs

) priority encoder 8.

) шифратора приоритетов 8 будут установлены значения логической единицы, а на входах 81_k-1-81_K (входах регистров

) - значения логического нуля. В этом случае на N инверсных выходах 82₁-82_N (выходах

) шифратора приоритетов 8 будет сформирован двоичный код в инверсном представлении, соответствующий значению первого номера входа

с установленным значением логического нуля, т.е. код соответствующий числу k - номеру интервала, которому принадлежит значение a _k. Полученный код после инвертирования в элементах 9₁-9_N поступает на N-разрядный информационный вход 101 второго регистра 10, здесь регистрируется как код предыдущего шага, затем поступает на N-разрядный вход 111 блока проверки значений вероятностей переходов 11.Thus (see Fig. 1), under the condition b _k-1 < a _k <b _k , at the inputs 81 ₁ -81 _K (the inputs of the registers

) priority encoder 8 will be set to logical units, and at inputs 81 _k-1 -81 _K (inputs of registers

) are logical zero values. In this case, at N inverse outputs 82 ₁ -82 _N (outputs

) Priority encoder 8, a binary code will be generated in the inverse representation corresponding to the value of the first input number

with a set value of logical zero, i.e. the code corresponding to the number k is the number of the interval to which the value of a _k belongs. The resulting code after inverting in elements 9 ₁ -9 _{N is} supplied to the N-bit information input 101 of the second register 10, here it is registered as the code of the previous step, then it goes to the N-bit input 111 of the block for checking the values of transition probabilities 11.

The code values of the previous step from the bits of the N-bit output 104 of the second register 10 are supplied to the corresponding bits of the N-bit input 111 of the block for checking the probabilities of transitions 11. In this case, the code containing the logical zero values in all bits is fed to the N-bit input of the value selector of transition probabilities 11.1 and to the N-bit input (D ₁ -D _K ) of the transition probability value converter 11.2 (see Fig. 2), which provides transit conversion (rewriting) of code values in the transition probability value selector 1 1.1 in the converter of transition probability values 11.2 and setting the logical zero values on all bits of the N-bit output of the transition probability values selector 11.1 and on the corresponding bits of the N-bit direct output 112 of the transition probability checking unit 11, as well as on all bits of the N-bit output Y (Y ₁ -Y _N ) converter of the values of the probabilities of transitions 11.2 and on the corresponding bits of the N-bit correction output 113 of the block for checking the values of the probabilities of transitions 11.

The receipt of logical zero values from the bits of the N-bit correction output 113 of the block of checking the probabilities of transitions 11 to the N-bit correction input 121 of the block of correction of the values of the probabilities of transitions 12 and to the corresponding bits of the N-bit input I (I ₁ -I _N ) of the programmable calculator 12.1 occur according to the corresponding permissive (unlocking) command received from the output of the TxD transmission of the converter of values of transition probabilities 11.2 through the control output 114 of the block for checking the values of probabilities of transitions rows 11 to a control input 123 of probability values correction unit 12 and transitions to the input output enable A (OE _I) 12.1 programmable calculator (see. FIG. 3) that ensures the establishment of a logical zero at all values N (A ₁ -A _N) outputs 12.1-1 ₁ - 12.1-1 _{N of} programmable calculator 12.1 and, as a result, after writing to memory cells, setting logical zero values on all bits of the N-bit output of the storage element 12.2 and on the corresponding bits of the N-bit direct output 122 of the value correction block transition probabilities 12.

) оперативного запоминающего устройства 5 подают значение логического нуля, а по первому входу «Чтение/запись» 02 генератора на вход 54 (вход

) оперативного запоминающего устройства 5 подают значение логической единицы, что соответствует операции чтения данных. Таким образом, в соответствии со случайными адресами, формируемыми источником случайных чисел, происходит чтение начальных (для первого шага работы генератора) значений элементов А={а ₁, а ₂, …, a _K} заданного набора данных из оперативного запоминающего устройства 5, которые через выход 55 поступают на М-разрядный выход «Результат» 013 генератора.Logical zero values from the bits of N-bit direct outputs 112 and 122 of the block of probabilities of transitions 11 and the block of correction of values of transition probabilities 12, respectively, are supplied to the corresponding bits of the second N-bit information input 0012 (input for bits B ₁ -B _N ) of the first selector-multiplexer 1 and the second N-bit information input 22 (input for bits B ₁ -B _N ) of the second selector-multiplexer 2. Then from the second N-bit information input 0012 (input for bits B ₁ -B _N ) of the first selector- mu of the multiplexer 1, the received and inverted code is fed to the N-bit address input 52 (input for bits A ₁ -A _N ) of the random access memory 5. In this case, the first input “Choice of crystal” 04 of the generator to input 51 (input

) random access memory 5 serves the value of logical zero, and on the first input "Read / write" 02 of the generator to input 54 (input

) random access memory 5 serves the value of a logical unit, which corresponds to the operation of reading data. Thus, in accordance with random addresses generated by the source of random numbers, the initial values (for the first step of the generator) of the elements A = { a ₁ , a ₂ , ..., a _K } of a given data set from random access memory 5 are read, which through the output 55 go to the M-bit output "Result" 013 generator.

At the second and subsequent steps of generating values of a discrete random process, the device operates taking into account not only the probabilistic, but also the ambiguous (incomplete and contradictory) relationship between the states of the random process (between the generated values of a given data set) as follows.

After registering the values of the previous (for the last step) quantitatively and ambiguously (incompletely and inconsistently) given upper boundaries of the intervals (the value of which dynamically changes according to the methods of Markov chains, depends on the probability of the transition of a random process from state to state and corresponds to the values of the probabilities required at the last step observations of the corresponding elements of a given data set) from the output 104 of the second register 10 are fed to the N-bit input 111 of the block for checking the values of transition probabilities 11 (see Fig. 2).

A preliminary analysis of the data in the interests of determining (verifying) the true values of the code characterizing the probabilities of a random process transitioning from state to state and defining new (for each subsequent step) upper bounds on the intervals, as well as revealing (selection) of ambiguous (incomplete and contradictory) identifiable values of this code is carried out in the unit for checking the values of transition probabilities 11 as follows. From the N-bit input 111 of the block for checking the values of transition probabilities 11, which require additional verification of the code characterizing the probabilities of the transition of a random process from state to state and new upper bounds for the intervals, they go to the corresponding bits of the N-bit input of the selector of values of transition probabilities 11.1 and to the corresponding bits of the N-bit input (D ₁ -D _N ) of the converter of transition probability values 11.2 (see Fig. 2).

The procedure for identifying (selecting) data on the true values of this code and deciding on the mathematical nature of this data is carried out in the selector of transition probability values 11.1 as follows. A code characterizing the probabilities of a random process transitioning from state to state and defining new (for each subsequent step) upper bounds for the intervals is fed to the N-bit input of the selector of transition probabilities 11.1, which is designed to store one binary number in each cell (bit) ( bits) of incoming information - this is quite enough to store the uniquely (fully and consistently) specified values of this code. If the number of binary numbers characterizing any of the N digits of this code exceeds one, that means, from the point of view of mathematics, this code sequence contains redundancy, which determines the ambiguity (incompleteness and inconsistency) of the data characterizing the probabilities of a random process from state to state and determining new (for each subsequent step) the upper bounds of the intervals.

селектора значений вероятностей переходов 11.1 поступает в двоичном коде команда, инициирующая запрет трансляции информации с N-разрядного выхода селектора значений вероятностей переходов 11.1 на соответствующие разряды N-разрядного прямого выхода 112 блока проверки значений вероятностей переходов 11. Последовательный код, характеризующий вероятности перехода случайного процесса из состояния в состояние и определяющий новые (для каждого последующего шага) верхние границы интервалов, который неоднозначно (неполно и противоречиво) идентифицирован, с N-разрядного выхода Y (Y₁-Y_N) преобразователя значений вероятностей переходов 11.2 через N-разрядный корректировочный выход 113 блока проверки значений вероятностей переходов И поступает на N-разрядный корректировочный вход 121 блока коррекции значений вероятностей переходов 12. С выхода передачи TxD преобразователя значений вероятностей переходов 11.2 через контрольный выход 114 блока проверки значений вероятностей переходов 11 на контрольный вход 123 блока коррекции значений вероятностей переходов 12 поступает команда, инициирующая начало процедуры верификации кода, характеризующего значения вероятностей перехода случайного процесса из состояния в состояние и определяющего новые (для каждого последующего шага) верхние границы интервалов.In this case (see Fig. 2), the command initiating the start of recording data characterizing the probabilities of a random process transitioning from state to state and determining new (for each subsequent step) upper bounds of intervals and the beginning of the conversion of this data from parallel to serial code. The converter of transition probability values 11.2 registers the data received through its N-bit input (D ₁ -D _N ), which is recognized by the selector of transition probability values 11.1 as ambiguous (incomplete and inconsistent) and converts them from parallel to serial code. In this case, from the enable output of the DSR converter of the values of the probabilities of transitions 11.2 to the inverse enable input

the transition probability value selector 11.1 receives in binary code a command initiating the prohibition of transmitting information from the N-bit output of the transition probability value 11.1 selector to the corresponding bits of the N-bit direct output 112 of the transition probability value checking unit 11. A serial code characterizing the transition probabilities of a random process from state to state and determining new (for each subsequent step) upper bounds on intervals that are ambiguously (incomplete and contradictory) identifiable It is cited from the N-bit output Y (Y ₁ -Y _N ) of the transition probability value converter 11.2 through the N-bit correction output 113 of the transition probability value checking block And is fed to the N-bit correction input 121 of the transition probability value correction block 121. From the output transmitting the TxD converter of transition probability values 11.2 through the control output 114 of the transition probabilities value verification unit 11 to the control input 123 of the transition probabilities value correction block 12, a command initiating The procedure for verifying the code characterizing the probabilities of the transition of a random process from state to state and defining new (for each subsequent step) upper bounds of intervals was introduced.

If from the N-bit input 111 of the block for checking the probabilities of transitions 11, one binary number characterizing any of N is received at the N-bit input of the selector of probabilities of transitions 11.1 and the N-bit input (D ₁ -D _N ) of the converter of values of transition probabilities 11.2 discharges of values of transition probabilities, that means this code does not need to be verified, reliably, unambiguously (fully and consistently) characterizes the probabilities of the transition of a random process from state to state and reliably determines new ones (for each n next step) the upper boundaries of the intervals. In this case, without receiving the appropriate command to its inhibiting input DST, the transition probability value converter 11.2 locks its N-bit output Y (Y ₁ -Y _N ) and the TxD transmission output, and the transition probability value selector 11.1 translates the parallel code, unambiguously ( fully and consistent) characterizing the probabilities of the transition of a random process from state to state, from its N-bit output through the corresponding bits of the N-bit direct output 112 of the block for checking the probabilities of transitions 11 to correspond Suitable bits of the second N-bit input information 0012 (input to bits B ₁ -B _N) of the first multiplexer selector 1 and the second N-bit data input 22 (for input bits B ₁ -B _N) of the second selector-multiplexer 2.

The data characterizing the probabilities of a random process transitioning from state to state and new (for each subsequent step) upper bounds on the intervals defined (recognized) in the block for checking the probabilities of transitions 11 as ambiguous (incomplete and contradictory) and requiring neural network verification come from N -bit correction output 113 of the unit for checking the values of the probabilities of transitions 11 to the N-bit correction input 121 of the unit for correcting the values of the probabilities of transitions 12, which performs Recording, storing the code analysis results, characterizing the transition probability of the random process from state to state and new (for each subsequent step), the upper boundaries of the intervals and mathematically correct values of the neural network verification code. The conversion of these specific (recognized) data is ambiguous (incomplete and inconsistent) to a form suitable for unambiguous adoption of a reliable decision about the probability values of the transition of a random process from state to state and new (for each subsequent step) upper bounds of intervals, carried out in a programmable calculator 12.1 block correction values of the probabilities of transitions 12 as follows.

The programmable calculator 12.1 of the block of correction of the values of transition probabilities 12 (see Fig. 3) is technically implemented on the basis of the programmable (from the point of view of the matrix of weights - causal cognitive opinions on the values of the transition probabilities formulated by experts) microprocessor section that plays the role of a programmable parallel ALU, implements a computational neural network algorithm (ENS) described in [5]. If there is no information at the N-bit correction input 121 of the transition probability correction block 12 of the transitions 12 and at the N-bit input I (I ₁ -I _N ) of the programmable calculator 12.1, accordingly, a command is not received initiating the verification procedure to the control input 123 of the value correction block transition probabilities 12 and to the input enable outputs A (OE _I ) of the programmable calculator 12.1. In this case, the N outputs A (A ₁ -A _N ) of the programmable calculator 12.1, and hence the N-bit output of the memory element 12.2 are blocked. Otherwise, there is a signal at the output enable input A (OE _I ) of the programmable calculator 12.1 and ambiguously (incompletely and inconsistently) certain initial data characterizing the probabilities of the transition of a random process from state to state and new (for each subsequent step) upper bounds of intervals to the N-bit input I (I ₁ -I _N ) of the programmable computer 12.1, which implements the functions of a programmable parallel ALU.

The programmable calculator 12.1, which implements the functions of a programmable parallel ALU, relying on the programmed values of the elements of the weight matrix — analytically described cause-effect cognitive opinions on the values of transition probabilities formulated by experts, performs the calculation (extrapolation) procedure in accordance with the computational neural network algorithm described in detail in [5]. In this case, the input bits (cells) I ₁ -I _{N of the} N-bit input I correspond to the bit (1, ..., N) of the serial code received at the N-bit input I of programmable calculator 12.1 and are equal to N inputs (N _in ) of the calculators ( neurons) of the input layer U _a ENS, to which the values of N bits of the code are supplied, which have a physical meaning ambiguously (incomplete and contradictory) of a certain value of the transition probabilities. The set of direct and feedback N _input with N _output ENS, programmatically implemented within the framework of programmable calculator 12.1, allows one to take into account the weight coefficients of transition probability values formulated by experts and obtain extrapolated values of N at the N outputs A (A ₁ -A _N ) of programmable calculator 12.1 bits of a parallel code having the physical meaning of a verified (mathematically correctly verified) value of transition probabilities, determined on the basis of verified (reliable, complete) source data. In this case, the supply to the nth, where n = 1, 2, ..., N, input (I _n ) of the N-bit input I of the programmable calculator 12.1 is the discharge of a code characterizing ambiguously (incompletely and contradictory) certain probabilities of a random process transitioning from a state to the state and new (for each subsequent step) upper bounds of the intervals, initiates the issuance from the corresponding nth output (A _n ) of programmable calculator 12.1 (output of the nth neuron of the output layer U _b ) programmed according to the computational neural network algorithm described in [ 5], meaning a mathematically correctly transformed, relatively reliable discharge code that characterizes the true values of the probabilities of the transition of a random process from state to state and defines new (for each subsequent step) upper bounds on the intervals.

As a result, at the N outputs A (A ₁ -A _N ) of the programmable calculator 12.1, at the corresponding bits of the N-bit output of the memory element 12.2 and at the corresponding bits of the N-bit direct output 122 of the block of correction of the values of transition probabilities 12, we obtain information characterizing (on based on the analysis of the integrated expert opinion obtained within the framework of the ENS), the true probabilities of the transition of a random process from state to state, which determines new (for each subsequent step) upper bounds of intervals and azovannuyu (a verified) in order to improve the reliability of the generated implementation sequence.

The storage element 12.2 records, stores and issues from the corresponding bits of its N-bit output through the corresponding bits of the N-bit direct output 122 of the correction block of the probability values of transitions 12 to the corresponding bits of the second N-bit information input 0012 (input for bits B ₁ -B _N ) of the first selector-multiplexer 1 and the corresponding bits of the second N-bit data input 22 (for input bits B ₁ -B _N) of the second selector-multiplexer 2, the code containing the verified results of the analysis of Achen transition probabilities - code that uniquely (full and consistent) determines the transition probabilities generated by a random process from state to state and new (for each subsequent step), the upper boundaries of the intervals.

From the N-bit output 24 of the second selector-multiplexer 2, the previous (from the last step), verified, uniquely (fully and consistent) certain values of the upper boundaries of the intervals are fed to the N-bit information input 31 (input of the registers D ₁ -D _N ) of the first register 3.

Thus, at the N-bit information input 31 (the input of the registers D ₁ -D _N ) of the first register 3, which is responsible for recording and storing the values of the new upper boundaries of the intervals, we have uniquely determined in accordance with the Markov model verified by the neural network algorithm (fully and consistent) defined values of the upper bounds of the intervals for a particular step.

This ensures the generation of values of a given data set, taking into account both quantitatively (probabilistically) and qualitatively (ambiguously, incompletely, and contradictory) the pronounced relationship between the states of a random process. The current (changed from the initial) and verified, unambiguously (fully and consistent) defined values of the upper bounds of the intervals for a particular step from the N-bit output 34 of the first register 3 are supplied to the N-bit address inputs 62 ₁ -62 _K K blocks of storage boundaries intervals 6 ₁ -6 _K and further to the P-bit inputs "Upper boundary" 72 ₁ -72 _K blocks of comparison 7 ₁ -7 _K (see Fig. 4). The random number P 1-bit inputs of 71 ₁ -71 _K comparison blocks 7 ₁ -7 _K still receive a P-bit random address value from a random number source 4, again, but for this particular step, a random address value is compared with the current verified, unambiguously (fully and consistent) defined values of the upper boundaries of the given intervals obtained taking into account both the quantitative (probabilistic) and qualitative (ambiguous, incomplete and contradictory) relationships between the states of a random process a. The cycle repeats, and the values of the previous address coming from the output 104 of the second register 10 through the block checking the values of the probabilities of transitions 11 and the block correcting the values of the probabilities of transitions 12 to the second N-bit information input 0012 (input for bits B ₁ -B _N ) of the first selector multiplexer 1, then N-bit address input 52 (for input bits a ₁ -A _N) random access memory 5, are the initial data for the next element values from a given set of data according to both quantitative (Vero nostnoy) and qualitative (ambiguous, conflicting and incomplete) bond each successive previous values.

As a result, in accordance with random addresses generated by a random number source and in accordance with current corrected at each step, verified using a neural network algorithm, unambiguously (fully and consistent) defined values of the upper boundaries of the intervals, the current probabilistic-time values of elements A are read = { a ₁ , a ₂ , ..., a _K } of a given set of data from random access memory 5, which through output 55 go to the M-bit output "Result" 013 of the generator.

) оперативного запоминающего устройства 5 подают значение логической единицы.The generator stops working when a logical zero value is supplied to its control input 07, which corresponds to the termination of the formation of random numbers by the source of random addresses, or when the generator 51 is input to the first input “Crystal Selection” 04 of the generator (input

) random access memory 5 serves the value of a logical unit.

Thus, the proposed random sequence generator provides an increase in the reliability of generating a sequence of values from a given set of values by taking into account not only the probabilistic, but also the ambiguous (incomplete, contradictory) relationship of each successive value with the previous one. The realization of the possibility of generating a random sequence, taking into account the presence of not only probabilistic, but also ambiguous (incomplete, contradictory) connection of each successive value with the previous one, occurs due to the identifiable (incomplete, contradictory) identifiable values realized in the verification unit of transition probabilities 11 of preliminary detection (selection) of transition probabilities and making decisions about their mathematical nature and implemented in the block of correction of values of transition probabilities 12, mathematically correct computational transformation (recognition) of these values using neuromathematical methods to a form suitable for unambiguous (consistent) adoption of a reliable decision on the probability values of the transition of a random process from state to state and new (for each subsequent step) upper bounds of intervals in the interest of implementing the parametric procedure modeling (generating) random processes. This result is caused, as a result, by obtaining on the M-bit output “Result” 013 a generator of the current probabilistic-temporal values of the elements of a given data set, taking into account the presence of probabilistic (quantitative) and ambiguous (incomplete, contradictory) given probabilities of transitions of a random process from state to state .

Analysis of the principle of operation of the claimed random sequence generator shows the evidence of the fact that, along with the capabilities for generating the sequence of a given data set saved and described in the prototype, taking into account the probabilistic relationships between the states of this process, the random sequence generator is capable of generating high values of the elements of a random process characterizing the real behavior of a complex computing system - when the relationship parameters of a random process, the relationships of each successive sequence of generated values with the previous value have both quantitative (probabilistic) and qualitatively (ambiguous, incomplete, contradictory) expressed physical meaning.

This random sequence generator provides an increase in the level of reliability of modeling (generation) of random processes that occur in real systems, where both Markov models and poorly formalized models with ambiguously (incompletely, contradictory) given (observed) parameters are widely used, which extends the functionality of universal generating devices in modern computer technology, where the claimed random sequence generator will be used.

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Claims (3)

1. A random sequence generator containing K comparison blocks (7 ₁ -7 _K ), where K≥2 is the maximum possible power of a given set of generated values, the first selector-multiplexer (1), the second selector-multiplexer (2), the first register ( 3), random access memory (5), K interval storage blocks of intervals (6 ₁ -6 _K ), priority encoder (8), N inverters (9 ₁ -9 _N ), where N = [log ₂ K] is the number of binary bits sufficient to address the elements of a given set of generated values, second register (10), source of random numbers (4), R-p one-dimensional, where P> N, the output of "Random number" (42) which is connected to the P-bit inputs "Random number" (71 ₁ -71 _K ) K comparison units (7 ₁ -7 _K ), P-bit output (65 _k ) of the k-th block for storing the boundaries of the intervals (6 _k ), where k = 1, 2, ..., K, is connected to the P-bit input “Upper boundary” (72 _k ) of the k-th block of comparison (7 _k ), output The “comparison result” (73 _k ) of the k-th comparison block (7 _k ) is connected to the k-th inverse input (81 _k ) of the priority encoder (8), the nth inverse output (82 _n ) of which, where n = 1, 2, ..., N is connected to the input (91 _n ) of the nth inverter (9 _n ), the selection input (0013) of the first selector-multiplexer a (1) is connected to the control input (41) of the random number source (4), to the selection input (23) of the second selector-multiplexer (2) and is the control input (07) of the generator, the first N-bit information input (0011) of the first the selector-multiplexer (1) is the first N-bit address input (01) of the generator, the N-bit output (0014) of the first selector-multiplexer (1) is connected to the N-bit address input (52) of the random access memory (5), inverse the “Read / write” inputs (54) and “Chip selection” (51) which are respectively the first m Read / write input (02) and the first input “Crystal selection” (04) of the generator, and M-bit, where M≥2 is the number of bits sufficient to represent the maximum value from a given set of generated values, output (55) random access memory (5) is the M-bit output "Result" (013) of the generator, M-bit information input (53) of the random access memory (5) is the M-bit information input (03) of the generator, while the P-bit information input (63 _{k) k-th} boundaries of the storage unit ntervalov (6, _k) is the k-th F-bit data input (09 _k) of the generator, n-th bit of N-bit data input (101) of the second register (10) coupled to the inverted output (92 _{n) n-th} inverter ( 9 _n ), the first N-bit input (21) of the second selector-multiplexer (2) is the second N-bit address input (05) of the generator, and its N-bit output (24) is connected to the N-bit information input (31) the first register (3), the N-bit output (34) of which is connected to the N-bit address inputs (62 ₁ -62 _K ) of K blocks for storing the boundaries of the intervals (6 ₁ -6 _K ), respectively the inverse inputs “Crystal Select” (61 ₁ -61 _K ) and “Read / Write” (64 ₁ -64 _K ) which are interconnected and are respectively the second “Crystal Select” input (08) and the second Read / Write input »(010) of the generator, while the initialization inputs (33) and (103) of the first (3) and second (10) registers are respectively the first (06) and second (012) input“ Setup ”of the generator, and the reset inputs (32 ) and (102) of the first (3) and second (10) registers are combined and are the input “Zeroing” (011) of the generator, characterized in that an additional check unit is entered transition probabilities (11) and a correction block of transition probabilities (12), and the N-bit output (104) of the second register (10) is connected to the N-bit input (111) of the block of transition probabilities (11), N-bit the correction output (113) which is connected to the N-bit correction input (121) of the transition probability value correction block (12), the control input (123) of which is connected to the control output (114) of the transition probability value block (11), N-bit direct output (112) which is connected to an N-bit direct output (122) of the transition probability correction block (12) and is connected to the second N-bit information input (0012) of the first selector-multiplexer (1) and to the second N-bit information input (22) of the second selector-multiplexer (2) . 2. A random sequence generator according to claim 1, characterized in that the block of probabilities of transitions (11) consists of a selector of values of transition probabilities (11.1) and a converter of values of transition probabilities (11.2), the N-bit output of which is an N-bit correction the output (113) of the transition probability value verification unit (11), the TxD transmission output of the transition probability value converter (11.2) is the control output (114) of the transition probability value verification unit (11), allowing the DSR output to photoelectret values of the transition probabilities (11.2) is connected to the inverted enable input

the transition probability value selector (11.1), the N-bit output of which is an N-bit direct output (112) of the transition probability value checking unit (11), the inhibit input of the DST converter of the transition probability values (11.2) is connected to the inhibit output of the MT of the transition probability value selector (11.1), the N-bit input of which is connected to the N-bit input of the transition probability value converter (11.2) and is the N-bit input (111) of the transition probability value verification unit (11). 3. A random sequence generator according to claim 1, characterized in that the block of transition probability values correction (12) consists of a programmable computer (12.1) and a storage element (12.2), and the N-bit input I of programmable computer (12.1) is N- bit correcting input (121) of the block of values of transition probabilities (12), input OE _{I of the} resolution of outputs A of the programmable calculator (12.1) is a control input (123) of the block of correction of values of transition probabilities (12), N outputs A (A ₁ -A _N ) programmable numerator (12.1) are connected to respective inputs of N ₍₁ 12.2-1 - 12.2-1 _N) memory element (12.2), N-bit output of which is N-bit direct output (122) of the values of the transition probabilities correction unit (12).

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