RU2211481C2 - Random-number generator - Google Patents

Abstract

FIELD: computer engineering; static analyses in data processing systems. SUBSTANCE: device has random-number transducer, key block, threshold generation unit, OR gate, control unit incorporating shift register, OR gates, bit disconnection components, trigger component, and initial setting component. EFFECT: enhanced precision of random value simulation. 2 cl, 8 dwg

Description

 The invention relates to the field of computer technology and can be used in statistical research and in systems for processing information.

 A known random number sequence generator (see AS USSR 447706, class G 06 F 1/02, 1974), containing a uniformly distributed number sensor, switch, first and second clock generators, counter, registers, valves, delay element , converter, reset pulse shaper and key.

 The known generator generates an uncontrolled length sequence of random numbers, which limits its functionality.

 A known random number generator (see AS USSR 771654, class G 06 F 1/02, 1978), containing a source of uniformly distributed random signals, two memory blocks, an adder, a switch and a multiplier.

 The well-known generator allows you to get random numbers for functions with both continuous distributions and distributions having discontinuities of the first kind.

 However, this device provides limited accuracy of the approximation of the distribution function.

 The closest technical solution to the claimed invention is a random sequence generator of given values of a data set (see RF patent 2138074, class G 06 F 7/58, 1998), containing a random number source with a given distribution law, the output of which is connected to the second address input the multiplexer, and its first address input is the address input of the generator of a random sequence of set values of the data set, the resolution input of the multiplexer is the generator enable input. The multiplexer output is connected to the address inputs of the first and second memory blocks, the information input of the second memory block is connected to the information input of the first memory block and is the information input of the generator, the output of the first is connected to the input of the comparison unit, and the output of the second to the input of the block of elements "AND". The second control input of the block of elements "AND" is connected to the input of the selection of the multiplexer, and the third input of the block of elements "AND" is connected to the output of the comparison unit. The output of the block of elements "AND" is the output of the device.

 This prototype, in comparison with analogues, allows you to generate random variables with a dynamic change in their distribution function during the simulation of random processes.

при любом возможном Θ будет равно Θ (см., например, книгу: Б. А. Севастьянов - Курс теории вероятности и математической статистики-М.: Наука, 1982, с.213-232)) случайных величин.The disadvantage of the prototype generator is the relatively low modeling accuracy (modeling accuracy (non-bias) refers to the condition where the mathematical expectation of an estimate of a random variable

for any possible Θ it will be equal to Θ (see, for example, the book: B. A. Sevastyanov - The course of probability theory and mathematical statistics-M .: Nauka, 1982, pp. 213-232)) random variables.

 The aim of the invention is to develop a random number generator that provides higher accuracy of modeling random variables, estimates of the moments of simulated random variables that describe the behavior of complex systems, by generating random numbers in a given range of variation of the probability measure (see, for example, the book: Reliability and Efficiency ( reference book) / Edited by B.V. Gnedenko, v.2, p.20) their presentation by controlling the length of a random sequence of generated numbers.

 This goal is achieved by the fact that N, where N≥2, key blocks, N threshold generation blocks and an N-input OR element, are additionally introduced into the well-known random number generator containing a random number sensor (DCH) and a control unit. The random number sensor has a k-bit output, where k≥2, which is connected to the k-bit information input of each key block.

 The control input of the i-th block of keys, where i = 1, 2, ... N is connected to the i-th output of the control unit, and its k-bit output is connected to the k-bit input of the i-th block of threshold generation.

 The control output of the threshold generation unit is connected to the i-th input of the N-input OR element. The information k-bit output of the Nth thresholding block is the output of a random number generator.

 The control unit consists of an input element, a synchronizing element, a start block, a block for disabling discharges, an initial setting block, and an N-bit shift register, including N cells. The forward output of the jth cell, where j = 1, 2, ..., N-1 of the N-bit register is connected to the information input of the (j + 1) th cell, and the forward output of the Nth cell is connected to the first input of the input item. The second input of the input element is connected to the first input of the synchronizing element and the output of the initial installation block. The output of the input element is connected to the information input of the first cell of the N-bit register. The synchronizing inputs of the register cells with numbers from the second to the Nth are combined and connected to the second input of the synchronizing element, which is the input of the control unit. The clock input of the first cell is connected to the output of the clock element. The allowing input of the i-th cell of the N-bit register is connected to the i-th output of the block for disabling discharges. Installation inputs of all N cells of the N-bit register are combined and connected to the output of the start block. The information outputs of all N cells of the N-bit register are the corresponding N outputs of the control unit.

 Thanks to a new set of essential features and due to the introduction of a control unit, threshold generation blocks, key blocks and the relationships between them, it is possible to generate a sequence of random numbers with the required (minimum and maximum) probability of their occurrence. This makes it possible to simulate random variables with higher accuracy.

The claimed device is illustrated by drawings:
figure 1 - functional diagram of the device;
figure 2 - diagram of the control unit;
figure 3 - cell diagram of the control unit;
4 is a diagram of a trigger element;
5 is a diagram of an element of the initial installation.

6 is a diagram of a block of keys;
Fig.7 is a block diagram of the formation of thresholds;
8 is a diagram of an N-input OR element.

 The random number generator shown in FIG. 1, consists of a random number sensor 1, control unit 5, N, where N≥2, key blocks 2, N blocks for generating thresholds 3 and N-input element OR 4.

The random number sensor 1 is designed to obtain a sequence of numbers subject to a given distribution law. A known sensor is described in the book: M.P. Bobnev "Generation of random signals", M.: Energy, 1971, p. 170, fig. 6-13. The sensor has a k-bit output, where k≥2, which is connected to the information input of the corresponding element "AND" 2.1 _l , ..., 2.1 _{k of} each key block 2.

The key block 2 is designed to switch a random number from the output of the frequency converter to the input of the corresponding block of threshold formation. The control inputs of the i-th block of keys, where i = 1, 2, ... N, are connected to the i-th output of the control block. The outputs of the "And" elements 2.1 _l , ... 2.1 _{k are} simultaneously connected to the first group of inputs of the first 3.3 and second 3.4 comparison blocks and the second inputs of the three-input elements 3.7 _l ... 3.7 _k "And" of the i-th block of threshold formation 3.

The threshold generation unit 3 is intended for selective sampling of random numbers generated by the DSL. The second group of inputs of the first 3.3 and second 3.4 comparison blocks are connected to the outputs of the first 3.1 and second 3.2 resistive matrices. The first and second outputs of the first 3.3 and the second and third outputs of the second 3.4 comparison blocks are connected respectively to the first 3.5 and second 3.6 two-input "OR" elements. The output of the first 3.5 OR element is connected to the first inputs of the three-input elements 3.7 _l , ..., 3.7 _k AND, and the output of the second 3.6 OR element is connected to the third inputs of the three-input elements 3.7 _l ,. . . , 3.7 _k "AND", the outputs of which are connected to the corresponding inputs of the k-input 3.8 element "OR". In addition, the output of elements 3.7 _l , ..., 3.7 _{k of the} Nth threshold block is at the same time an information output of the threshold block and the output of a random number generator.

 Resistive matrices 3.1, 3.2 and 5.3 are identical and can be implemented as described in the book: B.V. Tarabrin, L.F. Lunin, Yu.N. Smirnov et al .; Integrated circuits; Directory. - Second edition, corrected -M: Energoatomizdat, 1985. , p. 190. The comparison nodes 3.3 and 3.4 are identical and can be implemented by applying the known schemes of comparison nodes described in the book: V.V. Gusev, O.N. Lebedev, A.M. Sidorov. Fundamentals of pulsed and digital technology.- SPVVIUS, 1995, pp. 149-152.

The output of the k-input 3.8 element "OR" is the control output of the threshold generation unit, which is connected to the i-th input of the N-input element OR 4. In addition, the outputs of the elements 3.7 _l , .... 3.7 _k N-th block of the formation of thresholds are the output of a random number generator. The output of the N-input element OR 4 is simultaneously connected to the second input of the synchronizing element 5.2, which is the input of the control unit, and the synchronizing inputs of the cells of the shift register 5.1 ₂ ... 5.1 _N of the control unit 5.

The control unit 5 is designed to generate control signals of the key blocks and can be implemented, as shown in figure 2. The control unit 5 consists of an N-bit shift register 5.1, including N-cells (Fig. 3), a synchronizing element 5.2, a disabling element of discharges 5.3, a starting element 5.4 (Fig. 4), an initial setting element 5.5 (Fig. 4), and input element 5.6. The first input of the synchronizing element 5.2 is simultaneously connected to the output of the initial installation element 5.5 and the second input of the input element 5.6, and the output with the synchronizing input of the first cell 5.1 ₁ shift register 5.1. The forward output of the jth cell, where j = 1, 2, ... N-1, N-bit register is connected to the information input of the (j + 1) th cell, and the forward output of the Nth cell is connected to the first input of the input element whose output is connected to the information input of the first cell of the N-bit register. The permissive input of the i-th cell of the N-bit register is connected to the i-th output of the discharge disconnect element, and the installation inputs of all N cells of the N-bit register are combined and connected to the output of the trigger element 5.4. The information outputs of all N cells of the N-bit register are the corresponding N outputs of the control unit.

The cells of the shift register 5.1 _l ... 5.1 _N can be implemented, as shown in figure 3, and include a DV-trigger 5.1.3, the first 5.1.1 and second 5.1.5 inverters, two-input element "And" 5.1.2 and two-input element "OR" 5.1.4. Installation S input is simultaneously connected to the output of the discharge switch 5.3, enabling input V and the input of the first inverter 5.1.1, the output of which is connected to the second input of the two-input element "And" 5.1.2. Installation input R through the second inverter 5.1.5 is connected to the output of the trigger element 5.4. The clock input C of the 1st cell is connected to the clock element 5.2, the clock inputs C of the cells 5.1 ₂ ... 5.1 _{N are} simultaneously connected to the second input of the clock element 5.2 and the input of the control unit (Fig. 2). The information input D of the first cell is simultaneously connected to the output of the input element 5.6 and the first input of the two-input element "And" 5.1.2. The information inputs of cells 5.1 ₂ ... 5.1 _{N are} simultaneously connected to the first input of the two-input element "AND" 5.1.2 cells 5.1 ₂ ... 5.1 _N and the output of the two-input element "OR" 5.1.4 cells 5.1 _l ... 5.1 _{N- 1} , the first input of which is connected to the output of the two-input element AND 5.1.2, and the second with the direct output of the DV trigger, which is the output of the control unit. The output of the two-input element "OR" 5.1.4 cell 5.1 _{N is} connected to the first input of the input element 5.6 (Fig. 2).

 The trigger element 5.4 can be implemented, as shown in figure 4, and includes a power source E, an RC circuit and a switch, the output of the trigger element is simultaneously connected to the installation inputs of the i-cells of the shift register.

The initial setup element 5.5 may be implemented as shown in FIG. 5, and includes an E power supply, a quenching resistor, and a button. The output of the element is simultaneously connected to the first input of the synchronizing element 5.2 and to the second input of the input element 5.6, which is a two-input element "OR". The synchronizing element 5.2 is a two-input element "OR", the second input of which is simultaneously connected to the input of the control unit and to the synchronizing inputs 5.1 ₂ ... 5.1 _N cells of the shift register. The disabling element of discharges 5.3 is implemented on the basis of a resistive matrix identical to the first 3.1 and second 3.2 resistive matrix of the threshold generation unit, the i-th output of which is connected to the enable output of the i-th cell of the shift register.

 DV triggers can be implemented on integrated circuits described in the book: V. A. Batushev, V. N. Veniaminov, V.G. Kovaleva et al .; Chips and their application - M .: Energy, 1978, p. 164-168.

 Elements "AND", "OR", inverters can be implemented on integrated circuits described in the book: B.V. Tarabrin, L.F. Lunin, Yu.N. Smirnov and others; Integrated circuits; Directory. - Second edition, revised - M: Energoatomizdat, 1985.

 The generator operates as follows.

 The principle of operation of the generator is to generate a sample of random numbers with a given probability of their occurrence from a sequence of random numbers generated by a random number sensor due to a sequential selective selection of random numbers generated by a random number sensor.

The accuracy of the formation of simulated distribution functions is largely determined by the ability of random number generators (RNGs) to generate a sequence of numbers whose values in each step of its operation are a random variable defined in the interval from 0 to M ^N-1 , where N is the number of digits of the RNG random number sensor , M - the basis of the number system used (MP Bobnev "Generation of random signals. Ed. 2nd revised and additional - M.," Energy ", 1971, p. 132). Moreover, the N-bit generator allows receive n = M ^N (1) different numbers. In this In this case, the probability of occurrence of each of n numbers is determined by the number of bits of the differential frequency distribution, which is finite in the general case. This circumstance causes certain difficulties in obtaining random variables with a low probability. The area of generating random variables with a low probability can be expanded by applying sequential number generation using the selective sampling method (L.1, p.136).

 The meaning of this method is to filter out a set of numbers that do not satisfy the required rule. In this case, a region of numbers that are "true" is formed, and they participate in the formation of random numbers in the next step of the transformation. In this case, the probability of the required random number appearing at each step of the transformation obeys the hypergeometric distribution (V.S. Korolyuk, N.I. Portenko, A.V. Skorokhod, A.F. Turbin. A Handbook of Probability and Mathematical Statistics. Second edition , revised and supplemented. M .; "Science", 1985, p.112).

 Thus, realizing the above principle of obtaining random numbers, it is possible to form a stream of numbers with any arbitrarily small probability of their occurrence.

 The signal in the form of a binary k-bit number from the output of the random number sensor (DCH) (Fig. 1) is fed to the information inputs of the elements "And" of all key blocks (Fig.6). The control i-th input of the key blocks is connected to the corresponding i-th output of the control unit and, if there is a logical “1” signal on it, the number is written to the i-th threshold generation unit.

. Подача сигнала логической "1" на установочные входы S ячеек, участвующих в формировании выходного сигнала, осуществляется замыканием контактов соответствующих переключателей элемента отключения разрядов 5.3. Таким образом, ячейки разрядов регистра подготавливаются к работе по информационному входу D. Путем кратковременного замыкания кнопки элемента начальной установки 5.5 (фиг.5) сигнал логической "1" через входной элемент 5.6 и синхронизирующий элемент 5.2, поступая на информационный вход D и синхронизирующий вход С DV-триггера первой ячейки, обеспечивает запись в нее "1". При этом на выходе первого триггера будет "1", на выходе остальных "0". В случае, когда i-й триггер не используется в формировании выходного сигнала, на разрешающий вход ячейки регистра сдвига от элемента 5.3 подается логический "0", в этом случае сигнал логической "1" через элемент 5.1.2 и 5.1.4, минуя триггер ячейки сдвига, подается на информационный вход следующего триггера. При этом сигналом логического "0" на выходе триггера обеспечивается запрет записи числа с выхода ГСЧ через соответствующий блок ключей на блок формирования порогов.At each moment of time (cycle), a logical "1" signal is available only at one of the outputs of the control unit. This is due to the fact that the basis of the control unit (Fig. 2) is an annular shift register, which operates as follows. When the power is turned on (Fig. 3), when the contacts of the start element 5.4 switch are closed, the shift register cells based on the DV trigger are set to the “0” state. This is due to the short-term supply of a logical "0" signal to the input

. Logic "1" signal is supplied to the installation inputs S of cells participating in the formation of the output signal by closing the contacts of the corresponding switches of the discharge disconnect element 5.3. Thus, the cells of the register bits are prepared for work on the information input D. By short-circuiting the buttons of the initial setting element 5.5 (Fig. 5), the logic signal “1” through the input element 5.6 and the synchronizing element 5.2, arriving at the information input D and the synchronizing input C DV-trigger of the first cell, provides a record of "1" in it. In this case, the output of the first trigger will be "1", the output of the remaining "0". In the case when the ith trigger is not used in the formation of the output signal, a logical "0" is supplied to the resolving input of the shift register cell from element 5.3, in this case a logical "1" signal through element 5.1.2 and 5.1.4, bypassing the trigger cell shift, is fed to the information input of the next trigger. In this case, a logical “0” signal at the output of the trigger prohibits recording the number from the RNG output through the corresponding key block to the threshold generation block.

 Sequential movement along the bits of the shift register is carried out by applying to the synchronizing inputs C of the triggers a logical signal “1”, which is generated in the N-input element “OR” (Fig. 8) in the presence of “1” at the output of any i-th block of threshold formation. In this case, at the information outputs 1, 2, ..., i of the control unit, combinations 100. .. 00, 010 ... 00, 000 ... 01 are alternately formed, which, arriving at the control inputs of the "And" elements of the key blocks (Fig.6), allow the recording of the number from the output of the DCH to the input of the corresponding threshold generation unit.

 In the threshold generation unit using the comparison nodes 3.3 and 3.4 (Fig. 7), a comparison of the N-bit number coming from the output of the key block with the upper and lower thresholds, which are determined by the required probability of occurrence of the number, is performed. Thresholds are set using resistive matrices 3.1 and 3.2. If the conditions specified by the resistive matrices are satisfied, the signal "1" through block 3.8 is fed to the input of the N-input element "OR" 4.

As a result of sequential selective sampling of numbers, when the resulting signal appears at the output of elements 3.7 _l , ..., 3.7 _{k of the} Nth block of threshold formation, a random number will be generated that meets the requirements.

Claims (2)

 1. A random number generator containing a random number sensor and a control unit, characterized in that N is additionally introduced into it, where N≥2, key blocks, N threshold generation units and an N-input OR element, k-bit output of a random number sensor , where k≥2, is connected to the k-bit information inputs of each key block, the i-th output of the control unit, where i = 1, 2,. . . , N is connected to the control input of the i-th block of keys, the k-bit output of which is connected to the k-bit input of the i-th block of threshold generation, the control output of which is connected to the i-th input of the N-input element OR, the output of the N-input element OR connected to the input of the control unit, the information k-bit output of the N-th block of the formation of thresholds is the output of a random number generator.  2. The generator according to claim 1, characterized in that the control unit consists of an input element, which is a two-input OR element, a synchronizing element, a start block, a block for disabling discharges, an initial setting unit, and an N-bit shift register, including N cells, promoting jth cell output, where j = 1, 2,. . . , N-1, N-bit register is connected to the information input of the (j + 1) -th cell, and the advance output of the N-th cell is connected to the first input of the input element, the second input of which is connected to the first input of the synchronizing element and the output of the initial setting unit , the output of the input element is connected to the information input of the first cell of the N-bit register, the synchronizing inputs of the cells of the N-bit register with numbers from the second to the Nth are combined, connected to the second input of the synchronizing element, which is the input of the control unit, and the synchronizing input of the first cell is connected to the output of the synchronizing element, allowing the input of the i-th cell of the N-bit register is connected to the i-th output of the block disconnecting discharges, and the installation inputs of all N cells of the N-bit register are combined and connected to the output of the start block, information outputs all N cells of the N-bit register are the corresponding N outputs of the control unit.

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