CN110609672B - True random number generating device and generating method thereof - Google Patents
True random number generating device and generating method thereof Download PDFInfo
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- CN110609672B CN110609672B CN201810617931.4A CN201810617931A CN110609672B CN 110609672 B CN110609672 B CN 110609672B CN 201810617931 A CN201810617931 A CN 201810617931A CN 110609672 B CN110609672 B CN 110609672B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/588—Random number generators, i.e. based on natural stochastic processes
Abstract
The invention provides a true random number generating device and a generating method thereof. The true random number generating device includes a selection signal providing circuit and a linear feedback shift register. The selection signal providing circuit is used for providing a true random selection signal. The linear feedback shift register includes a multi-stage true random number generator. The N-th level true random number generator is used for receiving the clock signal and the N-1 bit true random number. The N-th stage true random number generator generates a plurality of N-th stage output logic values according to the clock signal and the N-1-th bit true random number, and selects one of the N-th stage output logic values as the N-th bit true random number according to the true random selection signal.
Description
Technical Field
The invention relates to a device and a method for generating a true random number capable of providing multiple bit numbers.
Background
The conventional random number generating devices can be classified into a pseudo random number generating device and a true random number generating device. The pseudo random number generating device is mainly realized by a linear feedback shift register. The pseudo-random number generating means may generate a distributed average and multi-bit pseudo-random number. However, the pseudo-random number generated by the pseudo-random number generating device is periodic, so that the generation rule of the pseudo-random number can be broken by using logic operation. Compared with the pseudo random number generating device, the true random number generating device has no periodicity, so the true random number generated by the true random number generating device has unpredictability. However, if a multi-bit true random number is to be generated, a plurality of true random number generating means are required. This makes the real random number generating device require a large layout space in design. In addition, the true random number generating device is mainly an analog circuit, and generates more power consumption in operation, so that the true random number generating device is not easy to generate the true random number with more bits.
Disclosure of Invention
The invention provides a true random number generating device and a true random number generating method, which are used for generating a true random number of unpredictable multi-bit numbers.
The true random number generating device comprises a selection signal providing circuit and a linear feedback shift register. The selection signal providing circuit is used for providing a true random selection signal. The linear feedback shift register is coupled to the selection signal providing circuit. The linear feedback shift register is used for generating a plurality of real random numbers. The linear feedback shift register includes a multi-stage true random number generator. The multi-stage true random number generator is coupled in series. An N-th stage true random number generator among the plurality of true random number generators is configured to receive the clock signal, the N-1-th bit true random number, and the true random selection signal. The N-th stage true random number generator generates a plurality of N-th stage output logic values according to the clock signal and the N-1-th bit true random number, and selects one of the N-th stage output logic values as the N-th bit true random number according to the true random selection signal. N is a natural number greater than or equal to 2.
The method for generating the true random number is applicable to generating the true random number with a plurality of bits. The true random number generation method comprises the following steps: providing a true random selection signal; receiving the clock signal and the N-1 bit true random number, and generating a plurality of N-th output logic values according to the clock signal and the N-1 bit true random number; and selecting one of the plurality of N-th output logic values as an N-th bit true random number according to the true random selection signal. N is a natural number greater than or equal to 2.
Based on the above, the present invention generates a plurality of output logic values according to the clock signal and the previous-stage bit true random number, and selects one of the plurality of output logic values as the true random number according to the true random selection signal, thereby generating the multi-bit true random number with unpredictability.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic diagram of a true random number generating apparatus according to a first embodiment of the present invention.
Fig. 2 is a circuit diagram of a true random number generating device according to a second embodiment of the present invention.
Fig. 3 is a flowchart of a true random number generation method according to an embodiment of the present invention.
Fig. 4 is a circuit diagram of a true random number generating device according to a third embodiment of the present invention.
Description of the reference numerals
100. 200, 400: true random number generating device
110. 210, 410: selection signal providing circuit
120. 220, 420: linear feedback shift register
121 (1), 121 (2), 121 (N-1), 121 (N), 221 (1), 221 (2), 221 (3), 421 (1), 421 (2), 421 (3): true random number generator
122. 222, 422: logic operation circuit
2212 (1), 2212 (2), 2212 (3), 4212 (1), 4212 (2), 4212 (3): flip-flop
2214 (1), 2214 (2), 2214 (3): reverser
2216 (1), 2216 (2), 2216 (3), 4216 (1), 4216 (2), 4216 (3): selection circuit
BQ (1), BQ (2), BQ (3): data output terminal
BR1 (1), BR1 (2), BR1 (3), R2 (1), R2 (2), R2 (3): second logic value
CK (1), CK (2), CK (3): clock input terminal
CLK: clock signal
D (1), D (2), D (3): data input terminal
LR: logic operation result
Q (1), Q (3): data output terminal
R1 (1), R1 (2), R1 (3): first logic value
SS: true random select signal
TRN (1), TRN (2), TRN (3), TRN (N-1), TRN (N): true random number
S310, S320, S330: step (a)
XOR: exclusive OR gate
Detailed Description
Referring to fig. 1, fig. 1 is a schematic diagram of a true random number generating apparatus according to a first embodiment of the present invention. In the embodiment of fig. 1, the true random number generating device 100 includes a selection signal providing circuit 110 and a linear feedback shift register 120. The selection signal providing circuit 110 is used for providing a true random selection signal SS. The linear feedback shift register 120 is coupled to the selection signal providing circuit 110. In the present embodiment, the linear feedback shift register 120 is used to generate real random numbers TRN (1) to TRN (N) with multiple bit numbers. The linear feedback shift register 120 includes a plurality of stages of true random number generators 121 (1) through 121 (N). The true random number generators 121 (1) to 121 (N) are coupled to each other in series. In the present embodiment, the level 2 true random number generator 121 (2) receives the clock signal CLK and the 1 st bit true random number TRN (1). The level 2 true random number generator 121 (2) generates a plurality of level 2 output logic values according to the clock signal CLK and the 1 st bit true random number TRN (1), and selects one of the plurality of level 2 output logic values as the 2 nd bit true random number TRN (2) according to the true random selection signal SS. A 3 rd stage true random number generator (not shown) receives the clock signal CLK and the 2 nd bit true random number TRN (2). The 3 rd level true random number generator generates a plurality of 3 rd level output logic values according to the clock signal CLK and the 2 nd bit true random number TRN (2), and selects one of the plurality of 3 rd level output logic values as the 3 rd bit true random number TRN (3) according to the true random selection signal SS, and so on.
In the present embodiment, the linear feedback shift register 120 further includes a logic operation circuit 122. The logic operation circuit 122 is coupled to at least two of the true random number generators 121 (1) to 121 (N). The logic operation circuit 122 is configured to receive at least two of the true random numbers and perform logic operation to generate a logic operation result LR. For example, the logic operation circuit 122 is coupled to the true random number generators 121 (1), 121 (N). The logic operation circuit 122 is configured to receive the 1 st bit true random number TRN (1) provided by the true random number generator 121 (1) and the N-th bit true random number TRN (N) provided by the true random number generator 121 (N), and perform logic operation on the 1 st bit true random number TRN (1) and the N-th bit true random number TRN (N) to generate a logic operation result LR. After generating the logical operation result LR, the logical operation circuit 122 supplies the logical operation result LR to the 1 st stage true random number generator 121 (1). The level 1 true random number generator 121 (1) is configured to receive the clock signal CLK and the logic operation result LR, and generate a plurality of level 1 output logic values according to the clock signal CLK and the logic operation result LR. And the level 1 true random number generator 121 (1) selects one of the plurality of level 1 output logic values as the 1 st bit true random number TRN (1) according to the true random selection signal SS.
The logic circuits of the present invention may be one or more and are not limited in any way.
Next, the level 1 true random number generator 121 (1) supplies the 1 st bit true random number TRN (1) to the level 2 true random number generator 121 (2), and so on. The true random number generators 121 (1) to 121 (N) may respectively and continuously generate unexpected true random numbers TRN (1) to TRN (N). The linear feedback shift register 120 organizes the multiple-bit true random numbers TRN (1) -TRN (N) to generate a set of binary form multiple-bit true random numbers. In the present invention, the number of true random logic value generators is greater than or equal to 2, and the number of true random numbers generated is also greater than or equal to 2. The true random number generating device can configure the number of the true random logic value generators according to the bit number requirement of the true random number.
In this embodiment, the selection signal providing circuit 110 may be a circuit conforming to the algorithm of the chaotic algorithm (Chaotic Algorithm) for providing the true random selection signal SS in the form of a single bit.
It should be noted that, in the present embodiment, the true random selection signal SS is an unpredictable true random value, so in each of the true random number generators 121 (1) to 121 (N), one of the plurality of output logic values of each of the true random number generators 121 (1) to 121 (N) is randomly selected by the true random selection signal SS to generate multi-bit true random numbers TRN (1) to TRN (N). In addition, the true random selection signal SS may be a true random number in the form of a single bit. Therefore, the selection signal providing circuit 110 may occupy less layout space. The select signal providing circuit 110 for providing a true random value of a single bit may have lower power consumption than a select signal providing circuit providing a true random value of multiple bits.
For further explanation, please refer to fig. 2, fig. 2 is a circuit diagram of a true random number generating device according to a second embodiment of the present invention. In the embodiment of fig. 2, for convenience of explanation, the linear feedback shift register 220 includes three true random number generators 221 (1) to 221 (3). The true random number generator 221 (1) includes a flip-flop 2212 (1), an inverter 2214 (1), and a selection circuit 2216 (1). The true random number generator 221 (2) includes a flip-flop 2212 (2), an inverter 2214 (2), and a selection circuit 2216 (2). The true random number generator 221 (3) includes a flip-flop 2212 (3), an inverter 2214 (3) and a selection circuit 2216 (3).
In the present embodiment, the flip-flop 2212 (1) has a data input D (1), a clock input CK (1) and a data output Q (1), wherein the data input D (1) is configured to receive the logic operation result LR, and the clock input CK (1) is configured to receive the clock signal CLK. The flip-flop 2212 (1) generates a first logic value R1 (1) according to the logic operation result LR and the clock signal CLK, and outputs the first logic value R1 (1) through the data output terminal Q (1). The input of the inverter 2214 (1) is coupled to the data output Q (1) of the flip-flop 2212 (1). The inverter 2214 (1) is configured to receive the first logic value R1 (1) and generate a second logic value R2 (1) after the inverting operation. That is, in the present embodiment, the plurality of 1 st stage output logic values includes a first logic value R1 (1) and a second logic value R2 (1). The selection circuit 2216 (1) is coupled to the data output terminal Q (1) of the flip-flop 2212 (1), the output terminal of the inverter 2214 (1), and the selection signal providing circuit 210. The selection circuit 2216 (1) is controlled by a true random selection signal SS in the form of a single bit, and selects one of the first logic value R1 (1) and the second logic value R2 (1) as the 1 st bit true random number TRN (1) according to the true random selection signal SS.
For example, when the logic value of the true random selection signal SS is "0", the selection circuit 2216 (1) selects the first logic value R1 (1) as the first bit true random number TRN (1). Conversely, when the logic value of the true random selection signal SS is "1", the selection circuit 2216 (1) selects the second logic value R2 (1) as the first bit true random number TRN (1).
In this embodiment, the selection circuit 2216 (1) can be implemented by a two-to-1 Multiplexer (2-to-1 Multiplexer). The selection circuit 2216 (1) has a first input terminal, a second input terminal, a control terminal and an output terminal, and the first input terminal of the selection circuit 2216 (1) is coupled to the data output terminal Q (1) for receiving the first logic value R1 (1). A second input terminal of the selection circuit 2216 (1) is coupled to the output terminal of the inverter 2214 (1) for receiving the second logic value R2 (1). The control terminal of the selection circuit 2216 (1) is coupled to the selection signal providing circuit 210 for receiving the true random selection signal SS, and the output terminal of the selection circuit 2216 (1) is for providing the 1 st bit true random number TRN (1). In other embodiments, the selection circuit 2216 (1) may be implemented by a transmission gate (Transmission Gate).
The flip-flop 2212 (2) has a data input D (2), a clock input CK (2) and a data output Q (2), wherein the data input D (2) is configured to receive the 1 st bit true random number TRN (1), and the clock input CK (2) is configured to receive the clock signal CLK. The flip-flop 2212 (2) generates a first logic value R1 (2) according to the 1 st bit true random number TRN (1) and the clock signal CLK, and outputs the first logic value R1 (2) through the data output terminal Q (2). That is, in the present embodiment, the plurality of 2 nd stage output logic values includes a first logic value R1 (2) and a second logic value R2 (2). The input of the inverter 2214 (2) is coupled to the data output Q (2) of the flip-flop 2212 (2). The inverter 2214 (2) is configured to receive the first logic value R1 (2) and perform an inverse operation on the first logic value R1 (2) to generate a second logic value R2 (2). The selection circuit 2216 (2) is coupled to the data output terminal Q (2) of the flip-flop 2212 (2), the output terminal of the inverter 2214 (2), and the selection signal providing circuit 210. The selection circuit 2216 (2) is controlled by the true random selection signal SS for receiving the first logic value R1 (2) and the second logic value R2 (2). The selection circuit 2216 (2) selects one of the first logic value R1 (2) and the second logic value R2 (2) as the 2 nd bit true random number TRN (2) according to the true random selection signal SS.
The flip-flop 2212 (3) has a data input D (3), a clock input CK (3) and a data output Q (3), wherein the data input D (3) is configured to receive the 2 nd bit true random number TRN (2), and the clock input CK (3) is configured to receive the clock signal CLK. The flip-flop 2212 (3) generates a first logic value R1 (3) according to the 2 nd bit true random number TRN (2) and the clock signal CLK, and outputs the first logic value R1 (3) through the data output terminal Q (3). The input of the inverter 2214 (3) is coupled to the data output Q (3) of the flip-flop 2212 (3). The inverter 2214 (3) is configured to receive the first logic value R1 (3) and perform an inverse operation on the first logic value R1 (3) to generate a second logic value R2 (3). That is, in the present embodiment, the plurality of 3 rd stage output logic values includes a first logic value R1 (3) and a second logic value R2 (3). The selection circuit 2216 (3) is coupled to the data output terminal Q (3) of the flip-flop 2212 (3), the output terminal of the inverter 2214 (3), and the selection signal providing circuit 210. The selection circuit 2216 (3) is controlled by the true random selection signal SS for receiving the first logic value R1 (3) and the second logic value R2 (3). The selection circuit 2216 (3) selects one of the first logic value R1 (3) and the second logic value R2 (3) as the 3 rd bit true random number TRN (3) according to the true random selection signal SS.
In this embodiment, the logic operation circuit 222 includes exclusive or gates XOR. The exclusive-OR gate XOR has two inputs coupled to the true random number generators 221 (1) and 221 (3), respectively, for receiving the 1 st bit true random number TRN (1) and the 3 rd bit true random number TRN (3). The exclusive or gate XOR performs a logical operation on the 1 st bit true random number TRN (1) and the 3 rd bit true random number TRN (3) to generate a logical operation result LR. In the present embodiment, the logical operation circuit 222 may provide the logical operation result LR with a logical value of "0" when the 1 st bit true random number TRN (1) and the 3 rd bit true random number TRN (3) are the same. In contrast, the logic operation circuit 222 provides the logic operation result LR with a logic value of "1".
Referring to fig. 2 and 3, fig. 3 is a flowchart of a method for generating a true random number according to an embodiment of the invention. In step S310, a true random selection signal SS is provided. In step S320, a clock signal and an N-1 th bit true random number are received, and a plurality of N-th output logic values are generated according to the clock signal and the N-1 th bit true random number. Taking the true random number generator 221 (2) as an example, the true random number generator 221 (2) receives the clock signal CLK and the 1 st bit true random number TRN (1), and generates the first logic value R1 (2) and the second logic value R2 (2) of the 2 nd level output logic value according to the 1 st bit true random number TRN (1). Next, in step S330, one of the N-th output logic values is selected as the N-th bit true random number according to the true random selection signal SS. As an example, the true random number generator 221 (2) selects one of the first logic value R1 (2) and the second logic value R2 (2) as the 2 nd bit true random number TRN (2) according to the true random selection signal SS.
Referring to fig. 4, fig. 4 is a circuit diagram of a true random number generating device according to a third embodiment of the present invention. Unlike fig. 2, in the level 1 true random number generator 421 (1) of the present embodiment, the flip-flop 4212 (1) can provide the first logic value R1 (1) through the data output terminal Q (1) and the second logic value BR1 (1) through the inverted data output terminal BQ (1). The flip-flop 4212 (1) of the present embodiment can provide the first logic value R1 (1) through the data output terminal Q (1), and provide the second logic value BR1 (1) through the inverted data output terminal BQ (1). The first input of the selection circuit 4216 (1) is coupled to the data output Q (1), the first input is configured to receive the first logic value R1 (1), the second input of the selection circuit 4216 (1) is coupled to the inverted data output BQ (1), and the second input is configured to receive the second logic value BR1 (1), so as to select one of the first logic value R1 (1) and the second logic value BR1 (1) as the 1 st bit true random number TRN (1) according to the true random selection signal SS.
In the level 2 true random number generator 421 (2), the flip-flop 4212 (2) can provide the first logic value R1 (2) through the data output terminal Q (2) and the second logic value BR1 (2) through the inverted data output terminal BQ (2). The first input of the selection circuit 4216 (2) is configured to receive the first logic value R1 (2), and the second input of the selection circuit 4216 (2) is configured to receive the second logic value BR1 (2), so as to select one of the first logic value R1 (2) and the second logic value BR1 (2) as the 2 nd bit true random number TRN (2) according to the true random selection signal SS. The level 3 true random number generator 421 (3) is also configured similarly to the level 2 true random number generator 421 (2), and thus will not be repeated.
In summary, the present invention generates a plurality of output logic values according to the clock signal and the bit true random number of the previous stage. The true random select signal is an unpredictable true random value, and thus one of the plurality of output logic values is randomly selected as the true random number by the true random select signal, such that the true random number is unpredictable. In addition, the true random selection signal may be in the form of a single bit to achieve the above-described effect. Therefore, the selection signal providing circuit can occupy less layout space and generate lower power consumption.
Although the invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather may be modified or altered somewhat by persons skilled in the art without departing from the spirit and scope of the invention.
Claims (8)
1. A true random number generating apparatus, characterized by comprising:
a selection signal providing circuit for providing a true random selection signal, wherein the true random selection signal is an unpredictable true random value in the form of a single bit;
a linear feedback shift register coupled to the selection signal providing circuit for generating a plurality of true random numbers, the linear feedback shift register comprising:
the N-th stage true random number generator in the true random number generators is used for receiving a clock signal, an N-1 bit true random number and the true random selection signal, generating a plurality of N-th stage output logic values according to the clock signal and the N-1 bit true random number, and selecting one of the N-th stage output logic values to be used as the N-th bit true random number according to the true random selection signal; and
the logic operation circuit is coupled with at least two of the plurality of real random number generators, is used for receiving at least two of the plurality of real random numbers and carries out logic operation on at least two of the plurality of real random numbers to generate a logic operation result;
wherein, in the plurality of true random number generators, the 1 st stage true random number generator is used for receiving the clock signal and the logic operation result, generating a plurality of 1 st stage output logic values according to the clock signal and the logic operation result, selecting one of the plurality of 1 st stage output logic values as a 1 st bit true random number according to the true random selection signal,
where N is a natural number greater than or equal to 2.
2. The true random number generating device according to claim 1, wherein the nth stage true random number generator includes:
the flip-flop is provided with a data input end, a clock input end and a data output end, wherein the data input end is used for receiving the N-1 bit true random number, the clock input end is used for receiving the clock signal, and the data output end is used for outputting first logic values of the N-th output logic values.
3. The true random number generating device according to claim 2, wherein the nth stage true random number generator includes:
an inverter, an input terminal of which is coupled to the data output terminal and is used for receiving the first logic value and performing an inverse operation on the first logic value to generate a second logic value of the plurality of N-th output logic values; and
the selection circuit is coupled among the data output end of the flip-flop, the output end of the inverter and the selection signal providing circuit, and is used for receiving the first logic value and the second logic value, and selecting one of the first logic value and the second logic value as an Nth bit true random number according to the true random selection signal.
4. The true random number generating device of claim 3, wherein the selection circuit is a one-out-of-two multiplexer.
5. The true random number generating device of claim 3, wherein the selection circuit has a first input coupled to the data output for receiving the first logic value, a second input coupled to the output of the inverter for receiving the second logic value, a control coupled to the selection signal providing circuit for receiving the true random selection signal, and an output for providing the nth bit true random number.
6. The true random number generating device according to claim 1, wherein the nth stage true random number generator includes:
the flip-flop is provided with a data input end, a clock pulse input end, a data output end and a reverse data output end, wherein the data input end is used for receiving the N-1 bit true random number, the clock pulse input end is used for receiving the clock pulse signal, the data output end is used for providing a first logic value of the N-th output logic values, and the reverse data output end is used for providing a second logic value of the N-th output logic values; and
the selection circuit is coupled to the data output end of the flip-flop and the selection signal providing circuit, and is provided with a first input end, a second input end, a control end and an output end, wherein the first input end is used for receiving the first logic value, the second input end is used for receiving the second logic value, the control end is used for receiving the true random selection signal, and the output end is used for providing the Nth bit true random number, so that one of the first logic value and the second logic value is used as the Nth bit true random number according to the true random selection signal.
7. A method of generating a true random number, the method comprising:
providing a true random selection signal, wherein the true random selection signal is an unpredictable true random value in the form of a single bit;
receiving a clock signal and an N-1 bit true random number, and generating a plurality of N-th output logic values according to the clock signal and the N-1 bit true random number;
selecting one of the plurality of nth stage output logic values as an nth bit true random number according to the true random selection signal;
performing logic operation on at least two of the plurality of real random numbers to generate a logic operation result; and
receiving the clock signal and the logic operation result, generating a plurality of 1 st output logic values according to the clock signal and the logic operation result, selecting one of the 1 st output logic values according to the true random selection signal to be used as a 1 st bit true random number,
where N is a natural number greater than or equal to 2.
8. The true random number generating method of claim 7, wherein selecting one of the plurality of nth stage output logic values as the nth bit true random number according to the true random selection signal comprises:
generating a first logic value and a second logic value of the plurality of nth stage output logic values; and
and selecting one of the first logic value and the second logic value as an Nth bit true random number according to the true random selection signal.
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