CN115220694A

CN115220694A - Random data generation circuit and read-write training circuit

Info

Publication number: CN115220694A
Application number: CN202210711780.5A
Authority: CN
Inventors: 陆天辰
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-06-22
Filing date: 2022-06-22
Publication date: 2022-10-21

Abstract

The embodiment of the application provides a random data generation circuit and a read-write training circuit, which comprise: the shift register comprises m triggers, the trigger input ends of the triggers are used for receiving clock signals, the data input end of each trigger is connected to the output end of a data processing circuit or the output end of one of the triggers, the data processing circuit is used for carrying out logic processing on the output data of at least one trigger, and the output ends of n triggers are respectively used as n output ends Q1 to Qn; and the parallel-to-serial circuit is coupled with the shift register and is used for converting the parallel data output by the output ends Q1 to Qn in one clock period into serial data for output. The output ends of the plurality of flip-flops can be used as the output ends of the shift register, and the data output by the plurality of flip-flops in parallel is converted into serial data to be output through the parallel-serial circuit. In this way, when the clock signal is switched once, multi-bit data can be output in series, and the data generation speed can be effectively increased.

Description

Random data generation circuit and read-write training circuit

Technical Field

The embodiment of the application relates to the technical field of semiconductors, in particular to a random data generation circuit and a read-write training circuit.

Background

In the field of semiconductor technology, data writing and data reading are common data processing procedures, both of which are procedures for using a data storage circuit. When data writing is performed, data can be written into the data storage circuit. In data reading, data can be read from the data storage circuit. In order to ensure that the data writing function and the data reading function of the data storage circuit are normal, the data storage circuit can be subjected to read-write training through a clock signal CLK1 and training data.

Conventionally, training data may be generated by an LFSR (linear feedback shift register) to perform read/write training on an internal memory, for example, a DDR (double data rate SDRAM) or an SDRAM (synchronous dynamic random access memory). The LFSR circuit includes a plurality of DFFs (D type flip-flops). Each DFF switches in the clock signal CLK2 so that the data in one of the flip-flops is output as generated data upon each transition of CLK 2.

However, the LFSR circuit described above generates training data at a low speed.

Disclosure of Invention

The embodiment of the application provides a random data generation circuit and a read-write training circuit, so that the speed of generating training data is improved.

In one aspect, an embodiment of the present application provides a random data generating circuit, including:

the shift register comprises n output ends Q1 to Qn, and each output end outputs 1 bit of data in one clock period of a clock signal; wherein the shift register includes:

m flip-flops, trigger input ends of the flip-flops are used for receiving the clock signal, a data input end of each flip-flop is connected to an output end of a data processing circuit or an output end of one of the flip-flops, the data processing circuit is used for performing logic processing on output data of at least one flip-flop, and output ends of n flip-flops are respectively used as n output ends Q1 to Qn;

the parallel-to-serial circuit is coupled with the shift register and is used for converting the parallel data output by the output ends Q1 to Qn in one clock period into serial data to be output;

the n is a positive integer, and the m is a positive integer larger than or equal to the n.

Alternatively, n is 4 and m is 8.

Optionally, the 8 flip-flops are sequentially marked as a 1 st flip-flop to an 8 th flip-flop, and data input ends of the 1 st flip-flop to the 6 th flip-flop are respectively connected to the 6 data processing circuits: the data processing circuit comprises a 1 st data processing circuit to a 6 th data processing circuit, wherein a data input end of a 7 th trigger is connected to an output end of a 3 rd trigger, a data input end of an 8 th trigger is connected to an output end of a 4 th trigger, and output ends of the 1 st trigger to the 4 th trigger are sequentially output ends Q1 to Q4.

Optionally, the 1 st data processing circuit has 2 input terminals, and is respectively connected to the output terminal of the 5 th flip-flop and the output terminal of the 1 st flip-flop, and is configured to perform exclusive or processing on input data received by the 2 input terminals.

Optionally, the 2 nd data processing circuit has 3 input terminals, and the 3 input terminals are respectively connected to the output terminal of the 6 th flip-flop, the output terminal of the 1 st flip-flop, and the output terminal of the 2 nd flip-flop, and are configured to perform xor processing on input data received by the 3 input terminals.

Optionally, the 3 rd data processing circuit has 4 input terminals, and is respectively connected to the output terminals of the 1 st flip-flop to the 3 rd flip-flop and the output terminal of the 7 th flip-flop, and is configured to perform xor processing on input data received by the 4 input terminals.

Optionally, the 4 th data processing circuit has 4 input terminals, and is respectively connected to the output terminals of the 2 nd flip-flop to the 4 th flip-flop and the output terminal of the 8 th flip-flop, and is configured to perform xor processing on input data received by the 4 input terminals.

Optionally, the 5 th data processing circuit has 3 input terminals, and is respectively connected to the output terminal of the 1 st flip-flop, the output terminal of the 3 rd flip-flop, and the output terminal of the 4 th flip-flop, and is configured to perform xor processing on input data received by the 3 input terminals.

Optionally, the 6 th data processing circuit has 2 input terminals, and is respectively connected to the output terminal of the 2 nd flip-flop and the output terminal of the 4 th flip-flop, and is configured to perform xor processing on input data received by the 2 input terminals.

Optionally, the output data is divided into 2 ^m The bits are repeated in units.

On the other hand, an embodiment of the present application further provides a read-write training circuit, which includes a data memory and the random data generation circuit, where a parallel-to-serial circuit in the random data generation circuit is connected to the data memory, and is used to input data generated by the random data generation circuit into the data memory for read-write training.

Optionally, the data memory is a DDR5 internal memory.

The random data generation circuit and the read-write training circuit provided by the embodiment of the application can take the output ends of the plurality of triggers as the output ends of the shift register, and convert the data output by the plurality of triggers in parallel into serial data through the parallel-serial circuit for output. In this way, when the clock signal CLK2 is switched once, multi-bit data can be serially output, and the data generation speed can be effectively increased.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the embodiments of the application and, together with the description, serve to explain the principles of the embodiments of the application.

Fig. 1 is a schematic structural diagram of an LFSR circuit according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of data at the data input D of each flip-flop in the LFSR shown in FIG. 1 in 9 clock cycles according to an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a random data generating circuit according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of another random data generating circuit provided in an embodiment of the present application;

fig. 5 is a schematic structural diagram of a 1 st data processing circuit according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a 2 nd data processing circuit according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a 3 rd data processing circuit according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a 4 th data processing circuit according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of a 5 th data processing circuit according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of a 6 th data processing circuit according to an embodiment of the present application;

fig. 11 is a schematic diagram of data at the data input terminal D of each flip-flop in the random data generating circuit shown in fig. 4 in different clock cycles according to an embodiment of the present application.

Specific embodiments of the present application have been shown by way of example in the drawings and will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts of the present application in any way, but rather to illustrate the inventive concepts of the embodiments of the present application by those skilled in the art with reference to particular embodiments.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the examples of the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the embodiments of the application, as detailed in the appended claims.

Fig. 1 is a schematic structural diagram of an LFSR circuit according to an embodiment of the present disclosure. Referring to fig. 1, the LFSR circuit includes 8 DFFs: DFF _1 to DFF _8, and xor gates X1 to X3. Wherein each DFF has a data input D, a trigger input C and an output Q, the clock signal CLK2 being coupled into the trigger input C of each DFF. In addition, each DFF also corresponds to a reset input terminal for resetting data in the DFF, and since the embodiment of the present application does not relate to the operation of the reset input terminal, it is not shown in fig. 1.

Wherein, the output terminal Q of DFF _1 is connected with the data input terminal D of DFF _8 to shift the data of the data input terminal D of DFF _1 to the data input terminal D of DFF _8 at each switching of the clock signal CLK 2.

The output terminal Q of DFF _8 is connected to the data input terminal D of DFF _7 to shift-transfer the data of the data input terminal D of DFF _8 to the data input terminal D of DFF _7 at each switching of the clock signal CLK 2.

The output terminals Q and Q of DFF _7 and DFF _1 are connected to the input terminal of the exclusive or gate X1, and the output terminal of the exclusive or gate X1 is connected to the data input terminal D of DFF _6 to input an exclusive or result between data of the data input terminal D of DFF _7 and data of the data input terminal D of DFF _1 to the data input terminal D of DFF _6 at each switching of the clock signal CLK 2.

The output terminals Q and Q of DFF _6 and DFF _1 are connected to the input terminal of the exclusive or gate X2, and the output terminal of the exclusive or gate X2 is connected to the data input terminal D of DFF _5, so that the exclusive or result between the data of the data input terminal D of DFF _6 and the data of the data input terminal D of DFF _1 is input to the data input terminal D of DFF _5 at each switching of the clock signal CLK 2.

The output terminals Q and Q of DFF _5 and DFF _1 are connected to the input terminal of the xor gate X3, and the output terminal of the xor gate X3 is connected to the data input terminal D of DFF _4 to input an xor result between the data of the data input terminal D of DFF _5 and the data of the data input terminal D of DFF _1 to the data input terminal D of DFF _4 at each switching of the clock signal CLK 2.

The output terminal Q of DFF _4 is connected to the data input terminal D of DFF _3 to input data of the data input terminal D of DFF _4 to the data input terminal D of DFF _3 every switching of the clock signal CLK 2.

The output terminal Q of DFF _3 is connected to the data input terminal D of DFF _2 to input data of the data input terminal D of DFF _3 to the data input terminal D of DFF _2 every switching of the clock signal CLK 2.

The output terminal Q of DFF _2 is connected to the data input terminal D of DFF _1 to input data of the data input terminal D of DFF _2 to the data input terminal D of DFF _1 every time the clock signal CLK2 is switched.

In the initial state, each DFF input has a preset data value, which can be randomly set, so that the generated data is also random data. In generating the training data, the input data of each DFF is shifted once according to the above-described relationship when CLK2 switches once. The data output from the output terminal Q of DFF _1 is used as the data generated by the LFSR circuit.

As can be seen from the LFSR structure shown in fig. 1, in the current clock cycle, the data at the data input terminal D of DFF _8 is the data at the data input terminal D of DFF _1 in the previous clock cycle, the data at the data input terminal D of DFF _7 is the data at the data input terminal D of DFF _8 in the previous clock cycle, the data at the data input terminal D of DFF _6 is the exclusive-or result of the data at the data input terminals D of DFF _1 and DFF _7 in the previous clock cycle, the data at the data input terminal D of DFF _5 is the exclusive-or result of the data at the data input terminals D of DFF _1 and DFF _6 in the previous clock cycle, the data at the data input terminal D of DFF _4 in the previous clock cycle, the data at the data input terminal D of DFF _3 is the data at the data input terminal D of DFF _4 in the previous clock cycle, the data at the data input terminal D of DFF _2 in the previous clock cycle, and the data at the data input terminal D3 in the previous clock cycle, and the data input terminal D2 is the data at the data input terminal D2 in the previous clock cycle.

The data inputs of the flip-flops in the LFSR of FIG. 1 may be determined according to the above relationshipDData in any clock cycle. Fig. 2 is a schematic diagram of data at the data input D of each flip-flop in the LFSR shown in fig. 1 in 9 clock cycles according to an embodiment of the present application.

Referring to fig. 2, C0 may be in an initial state. In the initial state C0, data of the data input terminals D of the 1 st to 8 th flip-flops DFF _1 to DFF _8 may be denoted as D1 to D8, respectively. FIG. 2 shows the relationship between the data at the data input D of the flip-flop and the data D1 through D8 in the initial state for the remaining clock cycles C1 through C8. The data of the data input end D of each flip-flop in each clock cycle is determined by the data of the data input end D of each flip-flop in the previous clock cycle. For example, for DFF _8 in C1, the data at data input D is the same as the data at data input D of DFF _1 in the previous clock cycle C0, and for DFF _6 in C1, the data at data input D is the exclusive or result of the data at data inputs D of DFF _7 and DFF _1 in C0. In this way, the data at the data input terminal D of each flip-flop in the following C1 to C8 can be obtained according to the relationship between the data at the data input terminal D of each flip-flop in the adjacent clock cycles indicated by the arrows in fig. 2.

In the next clock cycle C1, the data at the data input terminal D of the 1 st flip-flop DFF _1 to the 8 th flip-flop DFF _8 are D2, D3, D4, D1^ D5, D1^ D6, D1^ D7, D8 and D1 respectively. Wherein ^ is an exclusive OR operation.

In the next clock cycle C2, the data at the data input D of the 1 st to 8 th flip-flops DFF _1 to DFF _8 are D3, D4, D1^ D5, D1^ D6^ D2, D1^ D7^ D2, D2^ D8, D1 and D2, respectively.

In the next clock cycle C3, the data at the data input D of the 1 st to 8 th flip-flops DFF _1 to DFF _8 are D4, D1^ D5, D1^ D6^ D2, D1^ D7^ D2^ D3, D2^ D8^ D3, D1^ D3, D2, and D3, respectively.

During the next clock cycle C4, the data at the data input D of the 1 st to 8 th flip-flops DFF _1 to DFF _8 are D1^ D5, D1^ D6^ D2, D1^ D7^ D2^ D3, D2^ D8^ D3^ D4, D1^ D3^ D4, D2^ D4, D3 and D4, respectively.

During the next clock cycle C5, the data at the data input D of the 1 st to 8 th flip-flops DFF _1 to DFF _8 are D1^ D6^ D2, D1^ D7^ D2^ D3, D2^ D8^ D3^ D4, D3^ D4^ D5, D2^ D4^ D1^ D5, D3^ D1^ D5, D4 and D1^ D5, respectively.

During the next clock cycle C6, the data at the data input D of the 1 st to 8 th flip-flops DFF _1 to DFF _8 are D1^ D7^ D2^ D3, D2^ D8^ D3^ D4, D3^ D4^ D5, D4^ D5^ D6, D3^ D5^ D6^ D2, D4^ D1^ D6^ D2, D1^ D5 and D1^ D6^ D2, respectively.

During the next clock cycle C7, the data at the data input D of the 1 st to 8 th flip-flops DFF _1 to DFF _8 are D2^ D8^ D3^ D4, D3^ D4^ D5, D4^ D5^ D6, D1^ D5^ D6^ D7, D4^ D6^ D7^ D3, D5^ D7^ D2^ D3, D1^ D6^ D2, and D1^ D7^ D2^ D3, respectively.

The data at the data input D of the 1 st to 8 th flip-flops DFF _1 to DFF _8 in the next clock cycle C8 are D3^ D4^ D5, D4^ D5^ D6, D1^ D5^ D6^ D7, D7^ D8^ D2^ D6, D5^ D7^ D8^ D4, D1^ D6^ D3^ D4^ D8, D1^ D7^ D2^ D3 and D2^ D8^ D3^ D4, respectively.

Accordingly, the data at the data input terminal D of DFF _1 is sequentially output according to 9 clock cycles C0 to C8 shown in fig. 2, resulting in 9-bit output data: d1, D2, D3, D4, D1^ D5, D1^ D6^ D2, D1^ D7^ D2^ D3, D2^ D8^ D3^ D4 and D3^ D4^ D5.

It can be seen that the LFSR circuit of fig. 1 has only one output terminal to output data, so that the speed of generating data is consistent with the frequency of the clock signal CLK2, and one bit of data is output when the clock signal CLK2 switches once, which is slow.

In order to solve the above problem, the embodiments of the present application output data through the output terminals of the plurality of flip-flops so that the clock signal CLK2 outputs multi-bit data every time it is switched. However, the multi-bit data is output in parallel with one switching of the clock signal CLK2, and cannot be directly output as the generated data. Therefore, the embodiment of the application converts the data output by the plurality of triggers in parallel into the serial data through the parallel-serial circuit and outputs the serial data.

The following describes in detail the technical solutions of the embodiments of the present application and how to solve the above technical problems with specific embodiments. These several specific embodiments may be combined with each other below, and details of the same or similar concepts or processes may not be repeated in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.

Fig. 3 is a schematic structural diagram of a random data generation circuit according to an embodiment of the present disclosure. Referring to fig. 3, the random data generating circuit 100 includes: a shift register 101 and a parallel-to-serial circuit 102, wherein the parallel-to-serial circuit 102 is coupled to the shift register 101. The shift register 101 has n output terminals Q1 to Qn to output parallel data generated by the shift register 101 in one clock cycle to the parallel-to-serial circuit 102, so that the parallel-to-serial circuit 102 converts the parallel data output from the output terminals Q1 to Qn into serial data, which is output as data generated by the random data generation circuit 100.

The shift register 101 may include m flip-flops 1011, denoted as DFF _1 to DFF _ m. n is a positive integer, and m is a positive integer greater than or equal to n. Accordingly, the output terminals Q of any n flip-flops DFF _1 to DFF _ n of the m flip-flops 1011 serve as the n output terminals Q1 to Qn, respectively, to output data according to the clock signal CLK 2. In outputting data, each of the output terminals Q1 to Qn outputs 1-bit data in one clock cycle of the clock signal CLK 2.

The flip-flop input C of each flip-flop 1011 of the m flip-flops 1011 is configured to receive the clock signal CLK2, so as to update the data at the data input D of the flip-flop 1011 according to the clock signal CLK 2. Since the updated data at the data input terminal D of each flip-flop 1011 is the data acquired by the flip-flop 1011 from the output terminal connected thereto, the updated data at the flip-flop 1011 is determined by the connection relationship between the data input terminal D of the flip-flop 1011 and the remaining flip-flops 1011.

The data input terminal D of each flip-flop is connected to the output terminal Q of one of the data processing circuits 1012 or one of the flip-flops 1011, so as to update the data of the data input terminal D according to the data of the output terminal according to the switching of the clock signal CLK 2.

For example, referring to fig. 3, the data input terminal D of DFF _1 is connected to the output terminal Q of another flip-flop 1011, so that the updated data at the data input terminal D of DFF _1 is the data at the data input terminal D of the other flip-flop 1011, i.e. shifting the data from the data input terminal D of the other flip-flop 1011 to the data input terminal D of DFF _1 is realized. Similarly, the data input terminal D of DFF _ m is also shifted by the data at the data input terminal D of another flip-flop 1011. Note that the data input terminal D of DFF _1 may be connected to the output terminal Q of any flip-flop 1011, so that the flip-flop 1011 to which the output terminal Q connected thereto belongs is not shown in fig. 3.

For another example, as shown in fig. 3, the data input terminal D of DFF _ n is connected to the data processing circuit 1012, and the data updated at the data input terminal D of DFF _ n is the output data of the data processing circuit 1012. Similarly, the updated data at the data input terminal D of DFF _ n +1 is also the output data of another data processing circuit 1012.

The data processing circuit 1012 is configured to perform logic processing on the output data of at least one flip-flop 1011, and an input terminal of the data processing circuit 1012 may be connected to an output terminal Q of any one or more flip-flops 1011. The logical processing here may be any logical processing, and the relationship between the output data and the input data of the data processing circuit 1012 may be flexible so that the output data of the data processing circuit 1012 is different from, but correlated with, the input data of the data processing circuit 1012. In this way, the diversity of the output data of the data processing circuit 1012 and the diversity of the data generated by the random data generating circuit 100 can be improved.

In order to make the data processing circuit 1012 implement the above logic processing, the data processing circuit 1012 can be connected by any logic gate in any manner. Thus, data processing circuit 1012 may include, but is not limited to, at least one of the following logic gates: an exclusive or gate, an and gate, an exclusive or gate, an or gate, and the like, and different logic gates or different connection manners of the data processing circuit 1012 can all realize different logic processing functions. For example, when the data processing circuit 1012 is obtained by cascade-connecting exclusive or gates, the data processing circuit 1012 may be configured to determine whether the output data of the flip-flop 1011 are the same, and if the output data are the same, may output a high level signal. If not the same, a low level signal may be generated.

It is understood that the more logic gates included in the data processing circuit 1012, the more complex the connection relationship, and the more diverse the output data of the data processing circuit 1012. However, the more the logic gates, the more complicated the connection relationship, which may result in higher operation complexity of the data processing circuit 1012, longer processing time, lower processing efficiency, and lower speed of generating data. Therefore, in order to balance the operation complexity and the diversity, the data processing circuit 1012 can be obtained by the cascade of the exclusive or gates, which not only ensures that the operation complexity is relatively small, but also can appropriately improve the data diversity.

In addition, when the data processing circuit 1012 in fig. 3 uses the cascade of exclusive or gates, the generated data can have the same characteristics as those generated by the LFSR shown in fig. 1, so that it is not necessary to adjust the read/write training logic for the data storage circuit, which helps to reduce the training cost.

Alternatively, the parallel-to-serial circuit 102 may be provided with n input terminals, and the n input terminals are connected to n output terminals Q1 to Qn in the shift register 101, respectively. In this manner, the parallel data output from the n output terminals Q1 to Qn of the shift register 101 can be input to the parallel-to-serial circuit 102 through the connection, so that the parallel-to-serial circuit 102 converts it into serial data output.

It is understood that the LFSR circuit shown in fig. 1 outputs one-bit data within one clock cycle of the clock signal CLK2, whereas the random data generation circuit 100 shown in fig. 3 may output n-bit data within one clock cycle of the clock signal CLK 2. That is, the random data generating circuit 100 shown in fig. 3 generates data at a speed n times that of the LFSR circuit shown in fig. 1.

In summary, in the process of generating data by the random data generating circuit 100, firstly, after each switching of the clock signal CLK2, each flip-flop 1011 in the shift register 101 receives input data from the output terminal connected to its own data input terminal D, and updates the input data to the data input terminal D of the flip-flop 1011, where the input data may be output data of the data processing circuit 1012 or output data of the remaining flip-flops 1011, and the n flip-flops 1011 output data thereof to the parallel-to-serial circuit 102 in parallel through the output terminals Q1 to Qn; then, the parallel-to-serial circuit 102 converts the received parallel data into serial data to be output.

It should be noted that n and m in the embodiment of the present application can be flexibly selected according to an actual application scenario. When n is different, the speed of generating data is different, so that the speed of generating data can be flexibly adjusted by adjusting n. When m is different, the size of the random data generating circuit 100 is different, so that the size of the random data generating circuit 100 can be flexibly adjusted by adjusting m.

Alternatively, n may be 4, m may be 8. That is, the random data generating circuit 100 shown in fig. 3 may be configured by 8 flip-flops 1011, and the outputs of the 4 flip-flops 1011 may be the output terminals of the shift register 101. In this way, when the same number of flip-flops 1011 are used as in fig. 1, 4-bit data can be output in one clock cycle of the clock signal CLK2, and the speed of generating data can be increased by 4 times.

Fig. 4 is a schematic structural diagram of another random data generating circuit 100 according to an embodiment of the present application. Referring to fig. 4, m is 8, and 8 flip-flops 1011 can be sequentially referred to as 1 st to 8 th flip-flops, that is, DFF _1 to DFF _8 in fig. 4. Referring to fig. 4, for the 1 st to 6 th flip-flops, i.e., DFF _1 to DFF _6 in fig. 4, the data input terminals D thereof are respectively connected to 6 data processing circuits 1012: the output data of the 1 st to 6 th data processing circuits are transmitted to the data input terminals D of DFF _1 to DFF _ 6. For example, the output data of the 2 nd data processing circuit is transferred to the data input terminal D of the 2 nd flip-flop DFF _ 2.

The data input terminal D of the 7 th flip-flop DFF _7 is connected to the output terminal Q of the 3 rd flip-flop DFF _3, and data of the data input terminal D of the 3 rd flip-flop DFF _3 is transferred to the data input terminal D of DFF _7 by shifting under the trigger of the clock signal CLK 2.

The data input terminal D of the 8 th flip-flop DFF _8 is connected to the output terminal Q of the 4 th flip-flop DFF _4, and data of the data input terminal D of the 4 th flip-flop DFF _4 is shifted and transferred to the data input terminal D of DFF _8 at the flip-flop of the clock signal CLK 2.

Further, the output terminals Q of the 1 st flip-flop DFF _1 to 4 th flip-flop DFF _4 are output terminals Q1 to D4 in order to take the output data of the 1 st flip-flop to 4 th flip-flop as the output data of the shift register 101, which are input in parallel to the parallel-serial circuit 102.

It can be seen that in the embodiment of the present application, data input to the data input terminals D of the 6 flip-flops can be logically processed by the 6 data processing circuits, so as to ensure diversity of data at the data input terminals D of the six flip-flops as much as possible. And the output data of 4 flip-flops can be used as the output of the shift register 101, so that the diversity of the output data of the shift register 101 is improved by the diversity of the data input end D of the flip-flop 1011.

Optionally, the 1 st data processing circuit in fig. 4 has 2 input terminals, and fig. 5 is a schematic structural diagram of the 1 st data processing circuit provided in the embodiment of the present application. Referring to fig. 5, the 1 st data processing circuit is respectively connected to the output terminal Q of the 5 th flip-flop DFF _5 and the output terminal Q of the 1 st flip-flop DFF _1, and performs an exclusive or process on input data received by the 2 input terminals. That is, the 1 st data processing circuit performs an exclusive-or process on the output data of the 5 th flip-flop DFF _5 and the output data of the 1 st flip-flop DFF _1 every time the clock signal CLK2 is switched, and the data obtained by the exclusive-or process is transmitted to the data input terminal D of the 1 st flip-flop DFF _ 1.

Referring to fig. 5, the 1 st data processing circuit is an exclusive or gate having 2 input terminals connected to the output terminal Q of the 5 th flip-flop DFF _5 and the output terminal Q of the 1 st flip-flop DFF _1, respectively.

In the embodiment of the present application, the xor result of the data at the data input terminals D of DFF _5 and DFF _1 may be updated to the data input terminal D of DFF _1 by the 1 st data processing circuit, so that the update of the data at the data input terminal D of DFF _1 in one clock cycle coincides with the update of the data at the data input terminal D of DFF _1 in the LFSR in fig. 1 in four clock cycles. That is, the data input terminal D of DFF _1 in fig. 5 can reach the state that the data input terminal D of DFF _1 in fig. 1 reaches in 4 clock cycles in one clock cycle, so that, when the shift register has four output terminals, the data output by DFF _1 is the data output by fig. 1 every 4 clock cycles, and the data output by three clock cycles in the middle interval is output by the other three output terminals.

Optionally, the 2 nd data processing circuit in fig. 4 includes two cascaded exclusive or gates, and fig. 6 is a schematic structural diagram of a 2 nd data processing circuit provided in an embodiment of the present application. Referring to fig. 6, the 2 nd data processing circuit has 3 input terminals connected to the output terminal Q of the 6 th flip-flop DFF _6, the output terminal Q of the 1 st flip-flop DFF _1, and the output terminal Q of the 2 nd flip-flop DFF _2, respectively, for performing an exclusive-or process on input data received by the 3 input terminals. That is, each time the clock signal CLK2 is switched, the output data of the 6 th flip-flop DFF _6, the output data of the 1 st flip-flop DFF _1, and the output data of the 2 nd flip-flop DFF _2 are exclusive-ored by the 2 nd data processing circuit, and the data obtained by the exclusive-or processing is transmitted to the data input terminal D of the 2 nd flip-flop DFF _ 2.

Referring to fig. 6, the output terminal Q of the 6 th flip-flop DFF _6 and the output terminal Q of the 1 st flip-flop DFF _1 are respectively connected to two input terminals of an exclusive or gate X1, the output terminal Q of the 2 nd flip-flop DFF _2 and the output terminal of the exclusive or gate X1 are respectively connected to an input terminal of an exclusive or gate X2, and the output terminal of the exclusive or gate X2 is connected to the data input terminal D of the 2 nd flip-flop DFF _ 2.

In the embodiment of the present application, the xor result of the data at the data input terminals D of DFF _6, DFF _2, and DFF _1 may be updated to the data input terminal D of DFF _2 by the 2 nd data processing circuit, so that the update of the data at the data input terminal D of DFF _2 in one clock cycle coincides with the update of the data at the data input terminal D of DFF _2 in the LFSR in fig. 1 in four clock cycles. That is, the data input terminal D of DFF _2 in fig. 6 can reach the state that the data input terminal D of DFF _2 in fig. 1 reaches in 4 clock cycles in one clock cycle, so that when the shift register has four output terminals, the data output by DFF _2 is the data output by fig. 1 in every 4 clock cycles, and the data output by three clock cycles in the middle interval is output by the other three output terminals.

Optionally, the 3 rd data processing circuit in fig. 4 has 4 input terminals, and fig. 7 is a schematic structural diagram of a 3 rd data processing circuit provided in an embodiment of the present application. Referring to fig. 7, the 3 rd data processing circuit is connected to the output terminals Q of the 1 st to 3 rd flip-flops DFF _1 to DFF _3 and the output terminal Q of the 7 th flip-flop DFF _7, respectively, and performs an exclusive or process on input data received at the 4 input terminals. That is, the 3 rd data processing circuit performs an exclusive-or process on the output data of the 1 st to 3 rd flip-flops DFF _1 to DFF _3 and the 7 th flip-flop DFF _7 every time the clock signal CLK2 is switched, and the data obtained by the exclusive-or process is transmitted to the data input terminal D of the 3 rd flip-flop DFF _ 3.

Referring to fig. 7, an output terminal Q of a 7 th flip-flop DFF _7 and an output terminal Q of a 1 st flip-flop DFF _1 are respectively connected to two input terminals of an exclusive or gate X1, an output terminal Q of a 2 nd flip-flop DFF _2 and an output terminal of the exclusive or gate X1 are respectively connected to an input terminal of an exclusive or gate X2, an output terminal Q of a 3 rd flip-flop and an output terminal of the exclusive or gate X2 are respectively connected to an input terminal of an exclusive or gate X3, and an output terminal of the exclusive or gate X3 is connected to a data input terminal D of the 3 rd flip-flop DFF _ 3.

In the embodiment of the present application, the 3 rd data processing circuit may update the xor result of the data at the data input terminals D of DFF _7, DFF _3, DFF _2, and DFF _1 to the data input terminal D of DFF _3, so that the update of the data at the data input terminal D of DFF _3 in one clock cycle coincides with the update of the data at the data input terminal D of DFF _3 in the LFSR in fig. 1 in four clock cycles. That is, the data input terminal D of DFF _3 in fig. 7 can reach the state that the data input terminal D of DFF _3 in fig. 1 reaches in 4 clock cycles in one clock cycle, so that when the shift register has four output terminals, the data output by DFF _3 is the data output by fig. 1 in every 4 clock cycles, and the data output by three clock cycles in the middle interval is output by the other three output terminals.

Optionally, the 4 th data processing circuit in fig. 4 has 4 input terminals, and fig. 8 is a schematic structural diagram of a 4 th data processing circuit provided in an embodiment of the present application. Referring to fig. 8, the 4 th data processing circuit is connected to the output terminals Q of the 2 nd to 4 th flip-flops DFF _2 to DFF _4 and the output terminal Q of the 8 th flip-flop DFF _8, respectively, for performing an exclusive or process on input data received at the 4 input terminals. That is, the 4 th data processing circuit performs the exclusive-or processing on the output data of the 2 nd to 4 th flip-flops DFF _2 to DFF _4 and the 8 th flip-flop DFF _8 every time the clock signal CLK2 is switched, and the data obtained by the exclusive-or processing is transmitted to the data input terminal D of the 4 th flip-flop DFF _ 4.

Referring to fig. 8, an output terminal Q of an 8 th flip-flop DFF _8 and an output terminal Q of a 2 nd flip-flop DFF _2 are respectively connected to two input terminals of an exclusive or gate X1, an output terminal Q of a 3 rd flip-flop DFF _3 and an output terminal of the exclusive or gate X1 are respectively connected to an input terminal of an exclusive or gate X2, an output terminal Q of a 4 th flip-flop and an output terminal of the exclusive or gate X2 are respectively connected to an input terminal of an exclusive or gate X3, and an output terminal of the exclusive or gate X3 is connected to a data input terminal D of the 4 th flip-flop DFF _ 4.

In the embodiment of the present application, the 4 th data processing circuit may update the xor result of the data at the data input terminals D of DFF _2, DFF _3, DFF _4, and DFF _8 to the data input terminal D of DFF _4, so that the update of the data at the data input terminal D of DFF _4 in one clock cycle is consistent with the update of the data at the data input terminal D of DFF _4 in the LFSR in fig. 1 in four clock cycles. That is, the data input terminal D of DFF _4 in fig. 8 can reach the state that the data input terminal D of DFF _4 in fig. 1 reaches in 4 clock cycles in one clock cycle, so that when the shift register has four output terminals, the data output by DFF _4 is the data output by fig. 1 every 4 clock cycles, and the data output by three clock cycles in the middle interval is output by the other three output terminals.

Optionally, the 5 th data processing circuit in fig. 4 has 3 input terminals, and fig. 9 is a schematic structural diagram of a 5 th data processing circuit provided in an embodiment of the present application. Referring to fig. 4, the 5 th data processing circuit is respectively connected to the output terminal of the 1 st flip-flop, the output terminal Q of the 3 rd flip-flop, and the output terminal of the 4 th flip-flop, and is configured to perform xor processing on input data received by the 3 input terminals. That is, the 5 th data processing circuit performs an exclusive-or process on the output data of the 1 st flip-flop DFF _1, the output data of the 3 rd flip-flop DFF _2, and the output data of the 4 th flip-flop DFF _4 every time the clock signal CLK2 is switched, and the data obtained by the exclusive-or process is transferred to the data input terminal D of the 5 th flip-flop DFF _ 5.

Referring to fig. 9, the output terminal Q of the 4 th flip-flop DFF _4 and the output terminal Q of the 1 st flip-flop DFF _1 are respectively connected to two input terminals of one xor gate X1, the output terminal Q of the 3 rd flip-flop DFF _3 and the output terminal of the xor gate X1 are respectively connected to an input terminal of an xor gate X2, and the output terminal of the xor gate X2 is connected to the data input terminal D of the 5 th flip-flop DFF _ 5.

In the embodiment of the present application, the 5 th data processing circuit may update the xor result of the data at the data input terminals D of DFF _1, DFF _3, and DFF _4 to the data input terminal D of DFF _5, so that the update of the data at the data input terminal D of DFF _5 in one clock cycle coincides with the update of the data at the data input terminal D of DFF _5 in the LFSR in fig. 1 in four clock cycles. That is, the data input terminal D of DFF _5 in fig. 9 can reach the state reached by the data input terminal D of DFF _5 in fig. 1 at 4 clock cycles at one clock cycle. Referring to fig. 2, DFF _5 in fig. 1 reaches a state of an exclusive or result of data of the data input terminals D of DFF _1, DFF _3, and DFF _4 at 4 clock cycles C4. In the embodiment of the present application, the data at the data input terminal D of DFF _5 shown in fig. 4 is not used as the output data of the shift register.

Optionally, the 6 th data processing circuit in fig. 4 has 2 input terminals, and fig. 10 is a schematic structural diagram of a 6 th data processing circuit provided in an embodiment of the present application. Referring to fig. 10, the 6 th data processing circuit is respectively connected to the output terminal of the 2 nd flip-flop and the output terminal of the 4 th flip-flop, and is configured to perform exclusive or processing on input data received by the 2 input terminals. That is, the 6 th data processing circuit performs the xor processing on the output data of the 4 th flip-flop DFF _4 and the output data of the 2 nd flip-flop DFF _2 every time the clock signal CLK2 is switched, and the data obtained by the xor processing is transmitted to the data input terminal D of the 6 th flip-flop DFF _ 6.

Referring to fig. 10, the 6 th data processing circuit is an exclusive or gate having 2 input terminals connected to the output terminal Q of the 4 th flip-flop DFF _4 and the output terminal Q of the 2 nd flip-flop DFF _2, respectively.

In the embodiment of the present application, the result of the exclusive-or of the data at the data input terminal D of DFF _4 and DFF _2 may be updated to the data input terminal D of DFF _6 by the 6 th data processing circuit, so that the update of the data at the data input terminal D of DFF _6 in one clock cycle coincides with the update of the data at the data input terminal D of DFF _6 in the LFSR in fig. 1 in four clock cycles. That is, the data input terminal D of DFF _6 in fig. 10 can reach the state reached by the data input terminal D of DFF _6 in fig. 1 in 4 clock cycles in one clock cycle. Referring to fig. 2, the state that the data input terminal D of DFF _6 in fig. 1 reaches at 4 clock cycles C4 is the exclusive or result of the data input terminals D of DFF _4 and DFF _ 2. In the embodiment of the present application, the data at the data input terminal D of DFF _6 shown in fig. 4 is not used as the output data of the shift register.

The data at the data input D of each flip-flop shown in fig. 4 in any clock cycle can be determined according to the connection relationship shown in fig. 4 to fig. 10. Fig. 11 is a schematic diagram of data at the data input terminal D of each flip-flop in the random data generating circuit 100 shown in fig. 4 in different clock cycles according to an embodiment of the present application.

Referring to fig. 11, C0 may be in an initial state. In the initial state C0, data of the data input terminals D of the 1 st to 8 th flip-flops DFF _1 to DFF _8 may be denoted as D1 to D8, respectively. Fig. 11 shows the relationship between the data at the data input terminal D of the flip-flop and the data D1 to D8 in the initial state in one clock cycle C1.

As can be seen from the connection relationship shown in fig. 5, in the current clock cycle, the data at the data input terminal D of DFF _1 is the exclusive or result between the data at the data input terminals D of DFF _1 and DFF _5 in the previous clock cycle. Thus, in the next clock cycle C1 shown in FIG. 11, the data at the data input terminal D of the 1 st flip-flop DFF _1 is D1^ D5.

As can be seen from the connection relationship shown in fig. 6, in the current clock cycle, the data at the data input terminal D of DFF _2 is the exclusive or result of the data at the data input terminals D of DFF _6, DFF _1 and DFF _2 in the previous clock cycle. Thus, in the next clock cycle C1 shown in FIG. 11, the data at the data input terminal D of the 2 nd flip-flop DFF _2 is D1^ D6^ D2.

As can be seen from the connection relationship shown in fig. 7, in the current clock cycle, the data at the data input terminal D of DFF _3 is the exclusive or result of the data at the data input terminals D of DFF _2, DFF _1, DFF _3, and DFF _7 in the previous clock cycle. Thus, in the next clock cycle C1 shown in FIG. 11, the data at the data input D of the 3 rd flip-flop DFF _3 is D1^ D7^ D2^ D3.

As can be seen from the connection relationship shown in fig. 8, in the current clock cycle, the data at the data input terminal D of DFF _4 is the exclusive or result of the data at the data input terminals D of DFF _3, DFF _8, DFF _4, and DFF _2 in the previous clock cycle. Thus, in the next clock cycle C1 shown in FIG. 11, the data at the data input D of the 4 th flip-flop DFF _4 is D2^ D8^ D3^ D4.

As can be seen from the connection relationship shown in fig. 9, in the current clock cycle, the data at the data input terminal D of DFF _5 is the exclusive or result of the data at the data input terminals D of DFF _1, DFF _3, and DFF _4 in the previous clock cycle. Thus, in the next clock cycle C1 shown in FIG. 11, the data at the data input D of the 5 th flip-flop DFF _5 is D1^ D3^ D4.

As can be seen from the connection relationship shown in fig. 10, in the current clock cycle, the data at the data input terminal D of DFF _6 is the exclusive or result of the data at the data input terminals D of DFF _4 and DFF _2 in the previous clock cycle. Accordingly, in the next clock cycle C1 shown in FIG. 11, the data at the data input terminal D of the 6 th flip-flop DFF _6 is D2^ D4.

As can be seen from the connection relationship shown in fig. 4, in the current clock cycle, the data at the data input terminal D of DFF _7 is the data at the data input terminal D of DFF _3 in the previous clock cycle. Accordingly, in the next clock cycle C1 shown in fig. 11, the data of the data input terminal D of the 7 th flip-flop DFF _7 is D3.

As can be seen from the connection relationship shown in fig. 4, in the current clock cycle, the data at the data input terminal D of DFF _8 is the data at the data input terminal D of DFF _4 in the previous clock cycle. Accordingly, in the next clock cycle C1 shown in fig. 11, the data of the data input terminal D of the 8 th flip-flop DFF _8 is D4.

Comparing the data at the data input D of each flip-flop shown in fig. 11 and fig. 2, the data at the data input D of each flip-flop in the clock cycle C1 shown in fig. 11 is identical to the data at the data input D of each flip-flop in the clock cycle C5 shown in fig. 2, that is, the random data generating circuit shown in fig. 4 to 10 can reach the state of the LFSR shown in fig. 1 in 4 clock cycles through one clock cycle. It can also be understood that the random data generating circuit 100 according to the embodiment of the present application can establish a relationship between the data at the data input terminal D of each flip-flop in C4 and the data at the data input terminal D of each flip-flop in C0 in fig. 2 through the data processing circuit, thereby realizing updating data and outputting data in advance.

Specifically, referring to fig. 2, through C0 to C3, the data output by the LFSR shown in fig. 1 sequentially is: d1, D2, D3 and D4, and then C4 to C7, the data outputted by the LFSR shown in FIG. 1 is D1^ D5, D1^ D6^ D2, D1^ D7^ D2^ D3 and D2^ D8^ D3^ D4 in sequence. Referring to FIG. 11, through C0, the data outputted from the random data generating circuit 100 shown in FIG. 4 are D1, D2, D3 and D4 in sequence, and through C1, the data outputted from the random data generating circuit 100 shown in FIG. 4 are D1^ D5, D1^ D6^ D2, D1^ D7^ D2^ D3 and D2^ D8^ D3^ D4 in sequence. It can be seen that the data sequence output by the two is the same.

In addition, the state of C1 in fig. 11 can be understood as a new initial state for updating in the next clock cycle. Since the state of C1 in fig. 11 is the same as the state of C4 in fig. 2, that is, the data stored by each flip-flop is the same, the state at the next clock cycle C2 in fig. 11 coincides with the state of C8 in fig. 2. The data can be continuously output according to the relation, and the data sequence output by the two is always the same.

As described above, the random data generating circuit 100 shown in fig. 4 to 10 can generate data having the same characteristics at a speed 4 times as high as that of the LFSR shown in fig. 2.

It should be noted that, since m flip-flops are used in the random data generating circuit 100 of the embodiment of the present application, each flip-flop stores one bit of data, the data at the data input terminal D of the m flip-flop may be up to 2 ^m And (4) respectively. Then, the data output from the shift register 101 is also 2 ^m The bits are repeated in units. That is, for a positive integer i greater than or equal to 1 and less than or equal to m, the ith bit data and the ith bit datai+j×2 ^m The bit data is the same, and j is a positive integer greater than or equal to 0.

Based on the random data generating circuit 100, an embodiment of the present application further provides a read-write training circuit, including: and the data memory and the random data generating circuit 100, wherein the parallel-to-serial circuit 102 in the random data generating circuit 100 is connected to the data memory and is used for inputting the data generated by the random data generating circuit 100 into the data memory for read-write training.

Optionally, the data memory is a DDR5 internal memory.

The random data generation circuit 100 provided by the embodiment of the application can improve the speed of generating training data, further improve the training speed and the training efficiency of the data storage circuit, and save time.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one of 8230, and" comprising 8230does not exclude the presence of additional like elements in a process, method, article, or apparatus comprising the element.

The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

The above description is only a preferred embodiment of the present application, and is not intended to limit the scope of the present application, and all equivalent structures or equivalent processes that are directly or indirectly applied to other related technical fields, which are made by using the contents of the specification and the drawings of the present application, are also included in the scope of the present application.

Claims

1. A random data generating circuit, comprising:

2. The random data generating circuit of claim 1, wherein n is 4 and m is 8.

3. The random data generating circuit of claim 2, wherein 8 flip-flops are sequentially denoted as 1 st flip-flop to 8 th flip-flop, and data input terminals of the 1 st flip-flop to the 6 th flip-flop are respectively connected to 6 data processing circuits: the data processing circuit comprises a 1 st data processing circuit to a 6 th data processing circuit, wherein a data input end of a 7 th trigger is connected to an output end of a 3 rd trigger, a data input end of an 8 th trigger is connected to an output end of a 4 th trigger, and output ends of the 1 st trigger to the 4 th trigger are sequentially output ends Q1 to Q4.

4. The random data generating circuit of claim 3, wherein the 1 st data processing circuit has 2 inputs respectively connected to the output of the 5 th flip-flop and the output of the 1 st flip-flop, and is configured to perform exclusive-or processing on the input data received by the 2 inputs.

5. The random data generating circuit of claim 3, wherein the 2 nd data processing circuit has 3 inputs respectively connected to the output of the 6 th flip-flop, the output of the 1 st flip-flop, and the output of the 2 nd flip-flop, for performing exclusive-or processing on the input data received by the 3 inputs.

6. The random data generating circuit of claim 3, wherein the 3 rd data processing circuit has 4 inputs respectively connected to the outputs of the 1 st to 3 rd flip-flops and the output of the 7 th flip-flop, and is configured to perform exclusive-or processing on the input data received by the 4 inputs.

7. The random data generating circuit of claim 3, wherein the 4 th data processing circuit has 4 inputs respectively connected to the outputs of the 2 nd flip-flop to the 4 th flip-flop and the output of the 8 th flip-flop, and is configured to perform exclusive-or processing on the input data received by the 4 inputs.

8. The random data generating circuit of claim 3, wherein the 5 th data processing circuit has 3 inputs respectively connected to the output of the 1 st flip-flop, the output of the 3 rd flip-flop, and the output of the 4 th flip-flop, and is configured to perform exclusive-or processing on the input data received by the 3 inputs.

9. The random data generating circuit of claim 3, wherein the 6 th data processing circuit has 2 inputs respectively connected to the output of the 2 nd flip-flop and the output of the 4 th flip-flop, and is configured to perform exclusive-or processing on the input data received by the 2 inputs.

10. Random data generation according to any of claims 1 to 9A circuit, wherein the data output from the shift register is divided into 2 ^m The bits are repeated in units.

11. A read-write training circuit, comprising a data memory and the random data generating circuit of any one of claims 1 to 10, wherein a parallel-to-serial circuit in the random data generating circuit is connected to the data memory, and is configured to input data generated by the random data generating circuit into the data memory for read-write training.

12. The read-write training circuit of claim 11, wherein the data memory is a DDR5 internal memory.