CN110609672A - True random number generating device and generating method thereof - Google Patents
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- CN110609672A CN110609672A CN201810617931.4A CN201810617931A CN110609672A CN 110609672 A CN110609672 A CN 110609672A CN 201810617931 A CN201810617931 A CN 201810617931A CN 110609672 A CN110609672 A CN 110609672A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/588—Random number generators, i.e. based on natural stochastic processes
Abstract
The invention provides a true random number generating device and a generating method thereof. The true random number generating apparatus includes a selection signal providing circuit and a linear feedback shift register. The selection signal providing circuit is used for providing a true random selection signal. The linear feedback shift register includes a plurality of stages of true random number generators. The Nth stage of the true random number generator is used for receiving the clock signal and the N-1 th bit of true random number. The Nth stage true random number generator generates a plurality of Nth stage output logic values according to the clock signal and the N-1 th bit true random number, and selects one of the plurality of Nth stage output logic values as the Nth bit true random number according to the true random selection signal.
Description
Technical Field
The invention relates to a true random number generating device and a generating method thereof, which can provide a plurality of bits.
Background
The random number generator can be divided into a pseudo random number generator and a true random number generator. The pseudo random number generating device is mainly realized by a linear feedback shift register. The pseudo random number generating device may generate a uniformly distributed and multi-bit pseudo random number. However, the pseudo random number generated by the pseudo random number generating device is periodic, so the generation rule of the pseudo random number can be broken by using logic operation. Compared with the pseudo random number generator, the real random number generator has no periodicity, so the real random number generated by the real random number generator is unpredictable. However, if a multi-bit true random number is to be generated, a plurality of true random number generation devices are required. This may cause the real random number generating apparatus to require a large layout space in design. In addition, the true random number generator is based on analog circuits, and generates a large amount of power consumption in operation, so that the true random number generator is not easy to generate true random numbers with a large number of bits.
Disclosure of Invention
The invention provides a true random number generating device and a true random number generating method, which are used for generating an unpredictable true random number with multiple bit numbers.
The true random number generating device of the present invention includes a selection signal providing circuit and a linear feedback shift register. The selection signal providing circuit is used for providing a true random selection signal. The linear feedback shift register is coupled to the selection signal providing circuit. The linear feedback shift register is used for generating a plurality of true random numbers. The linear feedback shift register includes a plurality of stages of true random number generators. The plural stages of true random number generators are coupled in series. The Nth stage of the plurality of true random number generators is configured to receive a clock signal, an N-1 th bit of true random number, and a true random select signal. The Nth stage true random number generator generates a plurality of Nth stage output logic values according to the clock signal and the N-1 th bit true random number, and selects one of the plurality of Nth stage output logic values as the Nth bit true random number according to the true random selection signal. N is a natural number greater than or equal to 2.
The true random number generation method of the present invention is suitable for generating a true random number of a plurality of bits. The true random number generation method includes: providing a true random selection signal; receiving a clock signal and an N-1 bit true random number, and generating a plurality of N-level output logic values according to the clock signal and the N-1 bit true random number; and selecting one of the plurality of Nth-stage output logic values as an Nth bit true random number according to the true random selection signal. N is a natural number greater than or equal to 2.
Based on the above, the present invention generates a plurality of output logic values according to the clock signal and the bit true random number of the previous stage, and selects one of the output logic values as the true random number according to the true random selection signal, thereby generating the unpredictable multi-bit true random number.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a diagram illustrating an apparatus for generating true random numbers according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram of an actual random number generator according to a second embodiment of the present invention.
FIG. 3 is a flowchart illustrating a method for generating true random numbers according to an embodiment of the invention.
FIG. 4 is a circuit diagram of an apparatus for generating a true random number according to a third embodiment of the present invention.
Description of the reference numerals
100. 200, 400: true random number generating device
110. 210, 410: selection signal providing circuit
120. 220, 420: linear feedback shift register
121(1), 121(2), 121(N-1), 121(N), 221(1), 221(2), 221(3), 421(1), 421(2), 421 (3): true random number generator
122. 222, 422: logic operation circuit
2212(1), 2212(2), 2212(3), 4212(1), 4212(2), 4212 (3): flip-flop
2214(1), 2214(2), 2214 (3): reverser
2216(1), 2216(2), 2216(3), 4216(1), 4216(2), 4216 (3): selection circuit
BQ (1), BQ (2), BQ (3): data output terminal
BR1(1), BR1(2), BR1(3), R2(1), R2(2), R2 (3): second logic value
CK (1), CK (2), CK (3): clock input terminal
CLK: clock signal
D (1), D (2), D (3): data input terminal
LR: logical operation result
Q (1), Q (3): data output terminal
R1(1), R1(2), R1 (3): first logic value
And SS: true random selection signal
TRN (1), TRN (2), TRN (3), TRN (N-1), TRN (N): true random number
S310, S320, S330: step (ii) of
XOR: XOR gate
Detailed Description
Referring to fig. 1, fig. 1 is a schematic diagram of an apparatus for generating true random numbers according to a first embodiment of the invention. In the embodiment of fig. 1, the apparatus 100 for generating an actual random number includes a selection signal providing circuit 110 and a linear feedback shift register 120. The selection signal providing circuit 110 is used to provide a true random selection signal SS. The linear feedback shift register 120 is coupled to the selection signal providing circuit 110. In the present embodiment, the linear feedback shift register 120 is used to generate true random numbers TRN (1) -TRN (n) with a plurality of bits. The linear feedback shift register 120 includes a plurality of stages 121(1) -121 (N). The true random number generators 121(1) -121 (N) are coupled in series with each other. In the present embodiment, the stage 2 true random number generator 121(2) receives the clock signal CLK and the 1 st bit true random number TRN (1). The level 2 true random number generator 121(2) generates a plurality of level 2 output logic values according to the clock signal CLK and the 1 st bit true random number TRN (1), and selects one of the plurality of level 2 output logic values as the 2 nd bit true random number TRN (2) according to the true random select signal SS. The 3 rd stage true random number generator (not shown) receives the clock signal CLK and the 2 nd bit true random number TRN (2). The 3 rd stage true random number generator generates a plurality of 3 rd stage output logic values according to the clock signal CLK and the 2 nd bit true random number TRN (2), and selects one of the plurality of 3 rd stage output logic values as the 3 rd bit true random number TRN (3) according to the true random selection signal SS, and so on.
In the present embodiment, the linear feedback shift register 120 further includes a logic operation circuit 122. The logic operation circuit 122 is coupled to at least two of the real random number generators 121(1) -121 (N). The logic operation circuit 122 is used for receiving at least two of the true random numbers and performing logic operation to generate a logic operation result LR. For example, the logic operation circuit 122 is coupled to the true random number generators 121(1), 121 (N). The logic operation circuit 122 is configured to receive the 1 st bit true random number TRN (1) provided by the true random number generator 121(1) and the nth bit true random number TRN (N) provided by the true random number generator 121(N), and perform a logic operation on the 1 st bit true random number TRN (1) and the nth bit true random number TRN (N) to generate a logic operation result LR. After generating the logical operation result LR, the logical operation circuit 122 provides the logical operation result LR to the level 1 true random number generator 121 (1). The level 1 true random number generator 121(1) is configured to receive the clock signal CLK and the logic operation result LR, and generate a plurality of level 1 output logic values according to the clock signal CLK and the logic operation result LR. And the level 1 true random number generator 121(1) selects one of the plurality of level 1 output logic values as the level 1 true random number TRN (1) according to the true random selection signal SS.
The logical operation circuit of the present invention may be one or more, and is not limited.
Next, the stage 1 true random number generator 121(1) provides the 1 st bit true random number TRN (1) to the stage 2 true random number generator 121(2), and so on. The true random number generators 121(1) -121 (N) may generate unpredictable true random numbers TRN (1) -TRN (N), respectively and continuously. The linear feedback shift register 120 organizes the plurality of bits of true random numbers TRN (1) -TRN (n) to generate a set of binary-type multi-bit true random numbers. In the present invention, the number of true random logic value generators is greater than or equal to 2, and the number of generated true random numbers is also greater than or equal to 2. The true random number generating device of the invention can configure the number of the true random logic value generators according to the requirement of the bit number of the true random number.
In the present embodiment, the selection signal providing circuit 110 may be a circuit conforming to the Algorithm rule of chaos Algorithm (Chaotic Algorithm) for providing the true random selection signal SS in the form of a single bit.
It should be noted that, in the present embodiment, the true random selection signal SS is an unpredictable true random value, so that in each of the stages of true random number generators 121(1) -121 (N), one of the output logic values of each of the stages of true random number generators 121(1) -121 (N) is randomly selected by the true random selection signal SS to generate the multi-bit true random numbers TRN (1) -TRN (N). Besides, the true random selection signal SS may be a true random number in the form of a single bit. Therefore, the selection signal supply circuit 110 can occupy less layout space. The selection signal providing circuit 110 for providing the true random value of a single bit may have lower power consumption than a selection signal providing circuit for providing the true random value of multiple bits.
To further explain, referring to fig. 2, fig. 2 is a circuit diagram of an actual random number generating device according to a second embodiment of the invention. In the embodiment of FIG. 2, for convenience of illustration, the linear feedback shift register 220 includes three true random number generators 221(1) -221 (3). The true random number generator 221(1) includes a flip-flop 2212(1), an inverter 2214(1), and a selection circuit 2216 (1). The true random number generator 221(2) includes a flip-flop 2212(2), an inverter 2214(2), and a selection circuit 2216 (2). The true random number generator 221(3) includes flip-flops 2212(3) and inverters 2214(3) and a selection circuit 2216 (3).
In the present embodiment, the flip-flop 2212(1) has a data input terminal D (1), a clock input terminal CK (1) and a data output terminal Q (1), the data input terminal D (1) is for receiving the logic operation result LR, and the clock input terminal CK (1) is for receiving the clock signal CLK. The flip-flop 2212(1) generates the first logic value R1(1) according to the logic operation result LR and the clock signal CLK, and outputs the first logic value R1(1) through the data output terminal Q (1). The input of the inverter 2214(1) is coupled to the data output Q (1) of the flip-flop 2212 (1). The inverter 2214(1) is configured to receive the first logic value R1(1) and generate the inverted second logic value R2 (1). That is, in the present embodiment, the plurality of 1 st-stage output logic values include a first logic value R1(1) and a second logic value R2 (1). The selection circuit 2216(1) is coupled to the data output Q (1) of the flip-flop 2212(1), the output of the inverter 2214(1), and the selection signal providing circuit 210. The selection circuit 2216(1) is controlled by a true random selection signal SS in the form of a single bit, and selects one of the first logic value R1(1) and the second logic value R2(1) as the 1 st bit true random number TRN (1) according to the true random selection signal SS.
For example, when the logic value of the true random select signal SS is "0", the selection circuit 2216(1) selects the first logic value R1(1) as the first bit true random number TRN (1). Conversely, when the logic value of the true random select signal SS is "1", the selection circuit 2216(1) selects the second logic value R2(1) as the first bit true random number TRN (1).
In this embodiment, the selection circuit 2216(1) can be implemented by a 2-to-1 Multiplexer. The selection circuit 2216(1) has a first input terminal, a second input terminal, a control terminal and an output terminal, and the first input terminal of the selection circuit 2216(1) is coupled to the data output terminal Q (1) for receiving the first logic value R1 (1). A second input terminal of the selection circuit 2216(1) is coupled to the output terminal of the inverter 2214(1) for receiving the second logic value R2 (1). The control terminal of the selection circuit 2216(1) is coupled to the selection signal providing circuit 210 for receiving the true random selection signal SS, and the output terminal of the selection circuit 2216(1) is used for providing the 1 st bit true random number TRN (1). In other embodiments, the selection circuit 2216(1) can be implemented by a Transmission Gate (Transmission Gate).
The flip-flop 2212(2) has a data input terminal D (2), a clock input terminal CK (2) and a data output terminal Q (2), the data input terminal D (2) is for receiving the 1 st bit true random number TRN (1), and the clock input terminal CK (2) is for receiving a clock signal CLK. The flip-flop 2212(2) generates the first logic value R1(2) according to the 1 st bit TRN (1) and the clock signal CLK, and outputs the first logic value R1(2) through the data output Q (2). That is, in the present embodiment, the plurality of 2 nd-stage output logic values include the first logic value R1(2) and the second logic value R2 (2). The input of the inverter 2214(2) is coupled to the data output Q (2) of the flip-flop 2212 (2). The inverter 2214(2) is configured to receive the first logic value R1(2) and invert the first logic value R1(2) to generate the second logic value R2 (2). The selection circuit 2216(2) is coupled to the data output Q (2) of the flip-flop 2212(2), the output of the inverter 2214(2), and the selection signal providing circuit 210. The selection circuit 2216(2) is controlled by the true random selection signal SS to receive the first logic value R1(2) and the second logic value R2 (2). The selection circuit 2216(2) selects one of the first logic value R1(2) and the second logic value R2(2) as the 2 nd bit true random number TRN (2) according to the true random selection signal SS.
The flip-flop 2212(3) has a data input terminal D (3), a clock input terminal CK (3) and a data output terminal Q (3), the data input terminal D (3) is for receiving the 2 nd bit TRN (2), the clock input terminal CK (3) is for receiving a clock signal CLK. The flip-flop 2212(3) generates the first logic value R1(3) according to the 2 nd bit TRN (2) and the clock signal CLK, and outputs the first logic value R1(3) through the data output Q (3). The input of the inverter 2214(3) is coupled to the data output Q (3) of the flip-flop 2212 (3). The inverter 2214(3) is configured to receive the first logic value R1(3) and invert the first logic value R1(3) to generate the second logic value R2 (3). That is, in the present embodiment, the plurality of 3 rd stage output logic values include the first logic value R1(3) and the second logic value R2 (3). The selection circuit 2216(3) is coupled to the data output Q (3) of the flip-flop 2212(3), the output of the inverter 2214(3), and the selection signal providing circuit 210. The selection circuit 2216(3) is controlled by the true random selection signal SS to receive the first logic value R1(3) and the second logic value R2 (3). The selection circuit 2216(3) selects one of the first logic value R1(3) and the second logic value R2(3) as the 3 rd bit true random number TRN (3) according to the true random selection signal SS.
In the present embodiment, the logic operation circuit 222 includes an exclusive or gate XOR. The XOR gate XOR has two input terminals coupled to the true random number generators 221(1) and 221(3) respectively for receiving the 1 st bit true random number TRN (1) and the 3 rd bit true random number TRN (3). The exclusive or gate XOR performs a logical operation on the 1 st bit true random number TRN (1) and the 3 rd bit true random number TRN (3) to generate a logical operation result LR. In the embodiment, the logic operation circuit 222 can provide the logic operation result LR with a logic value "0" in the case that the 1 st bit true random number TRN (1) and the 3 rd bit true random number TRN (3) are the same based on the exclusive or gate XOR. On the contrary, the logic operation circuit 222 provides the logic operation result LR with logic value "1".
Referring to fig. 2 and 3, fig. 3 is a flowchart illustrating a method for generating a true random number according to an embodiment of the invention. In step S310, a true random selection signal SS is provided. In step S320, a clock signal and an N-1 bit true random number are received, and a plurality of N-th stage output logic values are generated according to the clock signal and the N-1 bit true random number. Taking the true random number generator 221(2) as an example, the true random number generator 221(2) receives the clock signal CLK and the 1 st bit true random number TRN (1), and generates the first logic value R1(2) and the second logic value R2(2) of the 2 nd stage output logic value according to the 1 st bit true random number TRN (1). Next, in step S330, one of the nth output logic values is selected as an nth true random number according to the true random select signal SS. In the above example, the true random number generator 221(2) selects one of the first logic value R1(2) and the second logic value R2(2) as the 2 nd bit true random number TRN (2) according to the true random select signal SS.
Referring to fig. 4, fig. 4 is a circuit diagram of an actual random number generating device according to a third embodiment of the invention. Unlike fig. 2, in the level 1 true random number generator 421(1) of the present embodiment, the flip-flop 4212(1) provides the first logic value R1(1) through the data output Q (1) and provides the second logic value BR1(1) through the inverted data output BQ (1). The flip-flop 4212(1) of the present embodiment provides the first logic value R1(1) through the data output Q (1) and provides the second logic value BR1(1) through the inverted data output BQ (1). The first input terminal of the selection circuit 4216(1) is coupled to the data output terminal Q (1) for receiving the first logic value R1(1), and the second input terminal of the selection circuit 4216(1) is coupled to the inverted data output terminal BQ (1), and the second input terminal thereof is configured to receive the second logic value BR1(1), so as to select one of the first logic value R1(1) and the second logic value BR1(1) as the 1-bit true random number TRN (1) according to the true random selection signal SS.
In the stage 2 true random number generator 421(2), the flip-flop 4212(2) may provide the first logic value R1(2) through the data output Q (2) and provide the second logic value BR1(2) through the inverted data output BQ (2). The first input terminal of the selection circuit 4216(2) receives the first logic value R1(2), and the second input terminal of the selection circuit 4216(2) receives the second logic value BR1(2), so as to select one of the first logic value R1(2) and the second logic value BR1(2) as the 2-bit true random number TRN (2) according to the true random selection signal SS. The level 3 RTM 421(3) is also configured similarly to the level 2 RTM 421(2), and therefore cannot be repeated.
In summary, the present invention generates a plurality of output logic values according to the clock signal and the bit true random number of the previous stage. The true random select signal is an unpredictable true random value, and thus one of the plurality of output logic values is randomly selected by the true random select signal as a true random number, so that the true random number is unpredictable. In addition, the true random selection signal may be in the form of a single bit to achieve the above-described effect. Therefore, the selection signal providing circuit can occupy less layout space and produce lower power consumption.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited to the embodiments, and various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.
Claims (13)
1. A true random number generating apparatus, comprising:
a selection signal providing circuit for providing a true random selection signal;
a linear feedback shift register coupled to the selection signal providing circuit for generating a plurality of true random numbers, the linear feedback shift register comprising:
a plurality of real random number generators, coupled in series, an Nth-stage real random number generator of the plurality of real random number generators for receiving a clock signal, an N-1 th bit real random number, and the true random select signal, generating a plurality of Nth-stage output logic values according to the clock signal and the N-1 th-stage real random number, and selecting one of the plurality of Nth-stage output logic values as an Nth bit real random number according to the true random select signal,
wherein N is a natural number greater than or equal to 2.
2. The true random number generating device of claim 1, wherein the linear feedback shift register further comprises:
the logic operation circuit is coupled to at least two of the plurality of real random number generators, and is used for receiving at least two of the plurality of real random numbers and performing logic operation on at least two of the plurality of real random numbers to generate a logic operation result.
3. The apparatus of claim 2, wherein among the plurality of true random number generators, a level 1 true random number generator is configured to receive the clock signal and the logic operation result, generate a plurality of level 1 output logic values according to the clock signal and the logic operation result, and select one of the plurality of level 1 output logic values as a level 1 true random number according to the true random selection signal.
4. The real random number generating device of claim 1, wherein the nth stage real random number generator comprises:
the flip-flop is provided with a data input end, a clock pulse input end and a data output end, wherein the data input end is used for receiving the N-1 bit true random number, the clock pulse input end is used for receiving the clock pulse signal, and the data output end is used for outputting a first logic value of the N-th-stage output logic values.
5. The real random number generating device of claim 4, wherein the Nth stage real random number generator comprises:
an inverter having an input coupled to the data output for receiving the first logic value and inverting the first logic value to generate a second logic value of the plurality of nth stage output logic values; and
a selection circuit, coupled between the data output terminal of the flip-flop, the output terminal of the inverter, and the selection signal providing circuit, for receiving the first logic value and the second logic value, and selecting one of the first logic value and the second logic value as an nth bit true random number according to the true random selection signal.
6. The apparatus according to claim 5, wherein the selection circuit is an alternative multiplexer.
7. The apparatus of claim 5, wherein the selection circuit has a first input coupled to the data output for receiving the first logic value, a second input coupled to the output of the inverter for receiving the second logic value, a control terminal coupled to the selection signal providing circuit for receiving the true random selection signal, and an output for providing the N-bit true random number.
8. The true random number generating device of claim 1, wherein:
the selection signal providing circuit is a circuit complying with the algorithm rules of a chaotic algorithm for providing the true random selection signal in the form of a single bit.
9. The real random number generating device of claim 1, wherein the nth stage real random number generator comprises:
a flip-flop having a data input terminal, a clock input terminal, a data output terminal, and an inverted data output terminal, wherein the data input terminal is configured to receive the N-1 th bit true random number, the clock input terminal is configured to receive the clock signal, the data output terminal is configured to provide a first logic value of the plurality of nth stage output logic values, and the inverted data output terminal is configured to provide a second logic value of the plurality of nth stage output logic values; and
a selection circuit, coupled to the data output terminal of the flip-flop and the selection signal providing circuit, having a first input terminal for receiving the first logic value, a second input terminal for receiving the second logic value, a control terminal for receiving the true random selection signal, and an output terminal for providing the nth bit true random number, wherein one of the first logic value and the second logic value is selected as the nth bit true random number according to the true random selection signal.
10. A true random number generating method adapted to generate a true random number of a plurality of bits, the method comprising:
providing a true random selection signal;
receiving a clock signal and an N-1 bit true random number, and generating a plurality of N-level output logic values according to the clock signal and the N-1 bit true random number; and
selecting one of the plurality of Nth-stage output logic values as an Nth-bit true random number according to the true random selection signal,
wherein N is a natural number greater than or equal to 2.
11. The true random number generating method of claim 10, further comprising:
performing a logical operation on at least two of the plurality of true random numbers to generate a logical operation result; and
receiving the clock signal and the logic operation result, generating a plurality of 1 st-level output logic values according to the clock signal and the logic operation result, and selecting one of the plurality of 1 st-level output logic values as a 1 st bit true random number according to the true random selection signal.
12. The true random number generating method according to claim 10, wherein the step of selecting one of the plurality of nth-stage output logic values as the nth-bit true random number according to the true random select signal comprises:
generating a first logic value and a second logic value of the plurality of nth stage output logic values; and
and selecting one of the first logic value and the second logic value as an Nth bit true random number according to the true random selection signal.
13. The real random number generating method of claim 10, wherein said real random selection signal is a selection signal in the form of a single bit provided based on a calculus rule conforming to a chaos algorithm.
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| US20160179472A1 (en) * | 2014-12-19 | 2016-06-23 | Megachips Corporation | Random number generation device and method for generating random number |
| JP2016126518A (en) * | 2014-12-26 | 2016-07-11 | 株式会社メガチップス | Device and method for generating random numbers |
| US20180292857A1 (en) * | 2015-09-25 | 2018-10-11 | Gemalto Sa | Random clock generator |
| CN106293617A (en) * | 2016-08-12 | 2017-01-04 | 上海坚芯电子科技有限公司 | Real random number generator |
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