CN115694548A - Fast pseudo-random sequence generation method and system for 5G NR - Google Patents

Abstract

The invention provides a method and a system for generating a 5G NR fast pseudorandom sequence, which comprises the following steps: step S1: identifying valid starting position n for pseudorandom sequence application scenarios _START (ii) a Step S2: valid starting position n of pseudo-random sequence application scene based on identification _START Obtaining a state variable of an effective initial position of a preset application scene; and step S3: and generating a pseudo-random sequence by using the state variable of the effective initial position of the preset application scene. The invention can flexibly support various scenes and hardware speed requirements for HW circuit design by adopting a flexible pseudo-random bit generator.

Description

Fast pseudo-random sequence generation method and system for 5G NR

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a method and an apparatus for generating a fast pseudo-random sequence for 5G NR.

Background

As shown in fig. 1 for a typical 5G NR communication system, downlink information at a base station side is scrambled (Scrambling) by a pseudo random sequence and then sent out, and after receiving a signal, a user equipment needs to descramble (De-Scrambling) to recover the downlink information; the user equipment sends out the uplink information after scrambling, and the base station recovers the uplink information through descrambling after receiving the signals.

The 5G NR communication scene is complex, and the pseudo-random sequence content under different scenes is changed from an initial value x ₁ (i),i＝1,2,…,30，x ₂ (i) I =1,2, …,30 and length M _PN Determination of where x ₁ (i)＝0,i＝1,2,…,30，x ₂ (i) I =1,2, …,30 by C _init Determining, at a time of data processing C _init Is some certain known constant. For different channels, a certain segment or several segments of pseudo-random sequences are selected for scrambling/descrambling, for example, in the process of scrambling PBCH coded output data, the actually valid pseudo-random sequence is a certain segment in a continuous 8-segment sequence of c (i), i =1600,1601, … 1600+864 + 8-1, and the length of each segment is 864 bits. Assuming that the actual valid sequence is the last 1 segment of 864 bits, the first 7648 bits in the pseudo-random sequence generation process are invalid. The pseudo-random sequence required for generating the sequence of different reference signals may also be a certain segment of a long pseudo-random sequence, for example, the generation process of PDSCH DMRS sequence, and since the BWP coexistence scenario and the multicarrier aggregation scenario supporting different Numerology, the actually valid pseudo-random sequence may be c (i), i =1600,1601, … 1600+275 x 8-1, x =8 or 12 or 24, and a certain segment 275 x bit, therefore, the first 47800bit is invalid at most in the generation process of the pseudo-random sequence. In a general scenario, in order to avoid the situation that data in front of a sequence is not random enough, a protocol forces to stipulate that 1600 bits in front are invalid, namely N _C ＝1600。

A hardware system is usually based on a Linear Feedback Shift Register (or LFSR) structure, 1bit of pseudo random data is generated each time, and for a general scene, an effective starting position of a pseudo random sequence of the general scene is found through 1600 times of operation; for the scrambling/descrambling process of PBCH coded output data, 7648 operations are needed at most to find the effective starting position of the pseudorandom sequence; for the generation process of PDSCH DMRS sequence, 47800 operations are needed at most to find the effective starting position of the pseudo random sequence. The pseudo-random sequence obtained after the valid start positions can be used for related data scrambling/descrambling or signal generation, so that the operation process causes great delay and waste of power consumption in system processing.

The patent document US08793295B2 (application number US 13184646) discloses an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a pseudo-random sequence in response to a first m-sequence and a second m-sequence, wherein the first m-sequence is initialized with a pre-computed constant and the second m-sequence is initialized on a table of pre-defined initial sequences and pre-computed values indicating which components of the initial sequence participate in initializing the second m-sequence. The second circuit may be configured to store a table of pre-computed values. The patent only supports an LTE application scenario, and when the length N value of the sequence is large, a great storage cost is required.

Patent document CN109375897B (application number: 201710657524.1) discloses a method for generating a pseudo random sequence, which calculates N first data and N second data from N first initial data and N second initial data, respectively, and uses them as initial data of a first shift register and initial data of a second shift register, respectively. The first data in the pseudo random sequence may be generated by one clock cycle according to initial data of the first shift register and the second shift register, and one data in the pseudo random sequence is generated every clock cycle, and finally the pseudo random sequence is generated.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide a method and a system for generating a 5G NR fast pseudorandom sequence.

The invention provides a fast pseudo-random sequence generation method for 5G NR, which comprises the following steps:

step S1: identifying pseudo-random sequencesValid starting position n for column application scenarios _START ；

Step S2: valid starting position n of pseudo-random sequence application scene based on identification _START Obtaining a state variable X1 of a preset effective initial position of an application scene _START And X2 _START ；

And step S3: state variable X1 using preset application scene valid start position _START And X2 _START A pseudo-random sequence is generated.

Preferably, the pseudorandom sequence application scenario includes a PBCH encoded data scrambling/decoding process scenario, a PDSCH DMRS generation process scenario, and a preset general scenario;

effective starting position n of pseudo-random bit of PBCH coded data scrambling/decoding process scene _START ：

n _START ＝1600+864*SsbIdx,SsbIdx＝0,1,…,7；

The PDSCH DMRS generates a valid start position n of pseudorandom bits for a process scene _START ：

n _START ＝1600+X*275*i，i＝0，1，...，7，X＝8 or 12 or 24；

The effective starting position n of the pseudo random bit of the preset general scene _START Is a preset value.

Preferably, the step S2 employs:

step S2.1: obtaining a 1 st m sequence effective starting position n under a preset application scene _START The state variable after the secondary state conversion is stored;

step S2.2: the 1 st m-sequence precomputation value selector selects 1 data from the stored data to assign to the state variable X1 of the current effective initial position according to the condition of the current scene _START ；

Step S2.3: the 2 nd m-sequence state variable generator converts the initial state variable X2 _INIT Updating state variable X2 to effective starting position of current application scene _START 。

Preferably, said step S2.3 employs: n paths of m-sequence state variable generators based on current sceneThe special jump module selects 1 path special jump module to activate, and the initial state variable X2 _INIT Updating state variable X2 of effective starting position of current application scene by using activated special skip module _START (ii) a Or, the 2 nd m-sequence state variable generator converts the state variable X2 _INIT Completing P times of state conversion updating to X2 by an initial jump module _UPD Sharing the skip module and then dividing X2 _UPD Continuously iteratively processing L times to output and update state variable X2 of effective initial position of current application scene _START 。

Preferably, in the dedicated skip module, the first path dedicated skip module is used for inputting a state variable X2 _INIT Completing P times of state conversion, and inputting state variable X2 by the second path special skip module _INIT Completing (P + 864) or (P + 275X) state transition, …, the nth path special jump module inputs state variable X2 _INIT (P +864 (n-1)) or (P +275 (x (n-1)) state transitions are completed.

Preferably, in the initial skip module, the input data X2 _INIT The 3 bits of data in the code are subjected to XOR and assignment operation and then stored in reg1; input data X2 _INIT The remaining bit data except for the 3-bit data is stored in reg2 after being processed by 31 cycles; XOR processing reg1 and reg2 to obtain X2 _UPD ；

The 31cycle treatment adopts the following steps: the 28-bit processing is realized by configuring 1 54-bit register d, filling 0 with high 26 bits and filling X2 with low 28 bits _INIT (3：30)；

reg2＝d ₀ ^d ₄ ^d ₈ ^d ₁₁ ^d ₁₂ ^d ₁₅ ^d ₂₄ ^d ₂₇ ^d ₂₈ ^d ₃₅ ^d ₃₆ ^d ₄₂ ^d ₄₄ ^d ₄₇ ^d ₄₈ ^d ₅₁ ^d ₅₂

Register d is then shifted left by 1bit, and the lower bit is complemented by 0.

Preferably, in the initial jump module, F is defined as a state transition matrix of P operations, and the current state transition matrix has a dimension of 31 × 31, X2 _UPD ＝mod(F*X2 _INIT 2), wherein F X2 _INIT For Binary AND operationEach element of the F matrix takes 0 or 1.

Preferably, in the common skip module, the input data X2 _UPD The 3 bits of data in the code are subjected to XOR and assignment operation and then stored in reg1; input data X2 _UPD The remaining bit data except for the 3-bit data is stored in reg2 after being processed by 31 cycles; performing exclusive or processing on reg1 and reg2;

the 31cycle treatment adopts the following steps: the 28-bit processing is realized by configuring 1 54-bit register d, filling 0 with high 26 bits and filling X2 with low 28 bits _INIT (3：30)；

reg2＝d ₀ ^d ₄ ^d ₈ ^d ₁₁ ^d ₁₂ ^d ₁₅ ^d ₂₄ ^d ₂₇ ^d ₂₈ ^d ₃₅ ^d ₃₆ ^d ₄₂ ^d ₄₄ ^d ₄₇ ^d ₄₈ ^d ₅₁ ^d ₅₂

Then the register d is shifted to the left by 1bit, and the low bit is complemented by 0;

if the current L =0, the common jump module does not work, and the output X2 of the initial jump module _UPD For the final result X2 _START (ii) a If the current L =1, the result obtained by 1 working time of the shared skip module is X2 _START (ii) a If the current L =2, writing the result obtained by 1-time work of the common jump module into X2 _UPD Then, the result obtained by continuing to work for 1 time by the common jump module is X2 _START ；......。

Preferably, the step S5 employs: obtaining corresponding state transition matrix according to the requirement of HW circuit, and updating the state variable X1 _START Calculating to obtain y1 through an exclusive or combination circuit indicated in the state conversion matrix; updated state variable X2 _START And calculating to obtain y2 through an exclusive-or combination circuit indicated in the state transition matrix, and carrying out exclusive-or on y1 and y2 to obtain a pseudo-random bit.

According to the invention, the fast pseudo-random sequence generation system for the 5G NR is provided, which comprises:

a module M1: identifying valid starting position n for pseudorandom sequence application scenarios _START ；

A module M2: based on knowledgeValid starting position n for other pseudo-random sequence application scenarios _START Obtaining a state variable X1 of a preset effective initial position of an application scene _START And X2 _START ；

A module M3: state variable X1 using preset application scene valid start position _START And X2 _START A pseudo-random sequence is generated.

Compared with the prior art, the invention has the following beneficial effects:

1. the invention can save processing delay and power consumption by adopting the initial jump module;

2. the invention adopts 2 parts of independent processing method and device by adopting the shared jump module and the initial jump module, and is a device with low cost and low complexity for HW circuit design;

3. the invention adopts the special skip module structure of 1 from n, thereby saving the processing delay and the power consumption;

4. the invention can save processing delay and power consumption by adopting the initial jump module and the shared jump module, and is a device with low cost and low complexity;

5. by adopting the 1 st m-sequence pre-calculation value selector, the invention can save processing delay and power consumption;

6. the invention can flexibly support various scenes and hardware speed requirements for HW circuit design by adopting a flexible pseudo-random bit generator.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

fig. 1 is a schematic diagram of communication between a base station and user equipment.

FIG. 2 is a schematic diagram of a low-cost and fast pseudo-random sequence generator.

Fig. 3 is a schematic diagram of a 2 nd m-sequence state variable ultra-high speed generator device.

FIG. 4 is a diagram of a very low cost and high speed generator device for the 2 nd m-sequence state variable.

FIG. 5 is a diagram of a low cost system for an initial jump module.

FIG. 6 is a diagram of a low-cost apparatus sharing a skip module.

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will aid those skilled in the art in further understanding the present invention, but are not intended to limit the invention in any manner. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.

The present invention employs a low-complexity and low-cost method and apparatus for rapidly obtaining a state variable of an effective position of a pseudorandom sequence, and implementing scrambling and descrambling functions of reference signals or data in subsequent scheduling or processing, see fig. 2.

Example 1

The invention provides a fast pseudo-random sequence generation method for 5G NR, which comprises the following steps:

step S1: identifying valid starting position n for pseudorandom sequence application scenarios _START ；

For the NR communication system, the application scenario of the pseudorandom sequence is complex, and includes not only one specific number in the WCDMA, LTE, and LTE-a communication systems (in this embodiment, n is preferred) _START = 1600) but also implies more other scenarios such as PBCH encoded data scrambling/descrambling process, generation of pseudo random sequences used in PDSCH DMRS generation process;

specifically, the effective starting position of the pseudo-random bit related to the PBCH coded data scrambling/descrambling process is n _START ＝1600+864*SsbIdx，SsbIdx＝0，1，...，7；

The effective starting position of the pseudo-random bit related to the PDSCH DMRS generating process is n _START ＝1600+X*275*i，i＝0，1，...，7，X＝8 or 12 or 24；

The pseudo-random bit of the preset general scene isEffective starting position n _START In the present embodiment, n is preferably a predetermined number _START ＝1600。

Step S2: valid starting position n of pseudo-random sequence application scene based on identification _START Obtaining a state variable X1 of a preset effective initial position of an application scene _START And X2 _START ；

Specifically, the step S2 employs:

step S2.1: obtaining a 1 st m sequence effective starting position n under a preset application scene _START The state variable after the secondary state conversion is stored;

for example, for PBCH encoded data scrambling/descrambling process scenarios:

obtaining a state variable X1 after (1600 +864 +0) state transformation in advance _candidate0 ；

Obtaining a state variable X1 after (1600 +864 +1) state transformation in advance _candidate1 ；

Obtaining a state variable X1 after (1600 +864 +2) state transformation in advance _candidate2 ；

Obtaining a state variable X1 after (1600 +864 +3) state transformation in advance _candidate3 ；

Obtaining a state variable X1 after (1600 +864 +4) state transformation in advance _candidat□4 ；

Obtaining a state variable X1 after (1600 +864 +5) state transformation in advance _candidate5 ；

Obtaining a state variable X1 after (1600 +864 +6) state transformation in advance _candidate6 ；

Obtaining a state variable X1 after (1600 +864 +7) state transformation in advance _candidate7 ；

These 8 data are then stored.

For PDSCH DMRS the process scenario is generated:

obtaining a state variable X1 after the state transformation is carried out for (1600 +0) times in advance _candidate0 ，

Obtaining a state variable X1 after state transformation (1600 +, 275 + 8) times in advance _candidate1 (X＝8，Scsldx＝1)；

Obtaining a state variable X1 after (1600 +275 +2) state transformations in advance _candidate2 (X＝8，Scsldx＝2)；

Obtaining a state variable X1 after (1600 +275 +3) state transformations in advance _candidate3 (X＝8，Scsldx＝3)；

Obtaining a state variable X1 after (1600 +275 +4) state transformations in advance _candidate4 (X＝8，Scsldx＝4)；

Obtaining a state variable X1 after (1600 +275 + 8) state transformations in advance _candidate5 (X＝8，Scsldx＝5)；

Obtaining a state variable X1 after (1600 +275 +6) state transformations in advance _candidate6 (X＝8，Scsldx＝6)；

Obtaining a state variable X1 after (1600 +275 +7) state transformations in advance _candidate7 (X＝8，Scsldx＝7)；

Obtaining a state variable X1 after (1600 +275 + 12) state transformations in advance _candidate8 (X＝12，Scsldx＝1)；

Obtaining a state variable X1 after (1600 +275 + 12) state transformations in advance _candidate9 (X＝12，Scsldx＝2)；

Obtaining a state variable X1 after (1600 +275 +3) state transformations in advance _candidate10 (X＝12，Scsldx＝3)；

Obtaining a state variable X1 after state transformation (1600 +, 275 + 12 + 4) times in advance _candidate11 (X＝12，Scsldx＝4)；

Obtaining state variable X1 after (1600 +275 + 12) state transformations in advance _candidate12 (X＝12，Scsldx＝5)；

Obtaining state variable X1 after (1600 +275 + 12) state transformations in advance _candidate13 (X＝12，Scsldx＝6)；

Obtaining state variable X1 after (1600 +275 + 12) state transformations in advance _candidate14 (X＝12，Scsldx＝7)；

Obtaining a state variable X1 after (1600 +275 + 24) state transformations in advance _candidate15 (X＝24，Scsldx＝1)；

Obtaining a state variable X1 after (1600 +275 +2) state transformations in advance _candidate16 (X＝24，Scsldx＝2)；

Obtaining a state variable X1 after state transformation (1600 +, 275 + 24 + 3) times in advance _candidate17 (X＝24，Scsldx＝3)；

Obtaining a state variable X1 after (1600 +275 +4) state transformations in advance _candidate18 (X＝24，Scsldx＝4)；

Obtaining a state variable X1 after (1600 +275 +5) state transformations in advance _candidate19 (X＝24，Scsldx＝5)；

Obtaining a state variable X1 after (1600 +275 +6) state transformations in advance _candidate20 (X＝24，Scsldx＝6)；

Obtaining a state variable X1 after (1600 +275 +7) state transformations in advance _candidate21 (X＝24，Scsldx＝7)；

These 22 data are then stored.

Step S2.2: the 1 st m-sequence precomputation value selector selects 1 data from the stored data to assign to the state variable X1 of the current effective initial position according to the condition of the current scene _START ；

Scrambling/descrambling process scenarios for PBCH encoded data: select some 1 of the 8, namely: x1 _START ＝X1 _candidate4 (assume current scene SbsIdx = 4).

For PDSCH DMRS the process scene is generated: selecting according to the value combination of X and ScsIdx, if X =8 and ScsIdx =4, then X1 _START ＝X1 _candidate4 。

Step S2.3: the 2 nd m-sequence state variable generator converts the initial state variable X2 _INIT Updating state variable X2 to effective starting position of current application scene _START . Wherein the initial state variable X2 _INIT Is derived from the input value C of the system _init And (4) determining.

Wherein, the 2 nd m-sequence state variable generator can be realized by a plurality of schemes. FIG. 3 illustrates a very high speed generator method and apparatus, while FIG. 4 illustrates a very low cost and high speed generator method and apparatus;

FIG. 3 illustrates the input state variable X2 of the dedicated skip module 1 _INIT Completing P state transitions, the special skip module 2 pair inputs the state variable X2 _INIT Completing (P + 864) or (P + 275X) state transition, …, the special jump module 8 inputs the state variable X2 _INIT Completing (P +864 × 7) or (P +275 × X7) state transition, selecting 1 path to activate according to the current scene 8 paths, and outputting the updated state variable X2 _START ；

The initial jump module in FIG. 4 completes P state transitions, inputting the state variable X2 _INIT Updated to X2 _UPD Sharing the skip module and then dividing X2 _UPD Continuously iterating for L times, and outputting updated state variable X2 _START (ii) a For example, when the current scene is a PBCH coding data scrambling/decoding process and SsbIdx =5, we firstly obtain X2 through an initial jump module _UPD The 1 st run shared skip module takes the updated state variable as input, the 2 nd run shared skip module, … and the 5 th run shared skip module assign the result to X2 _START In the scene, the shared jump module completes 864 state transitions, and if the PDSCH DMRS generates a process scene, the shared jump module completes 275 × x state transitions.

The initial jump module can be realized by 2 methods and devices. FIG. 5 shows a low cost method and apparatus for dividing input data into 2 portions, the first portion being processed with simple logic and stored in reg1, the second portion being processed with 31 cycles and stored in reg2, and finally XORing reg1 and reg2 to obtain X2 _UPD Taking P =1569 as an example, the implementation process is described as follows:

input data X2 _INIT The first part of the 3-bit processing, namely some simple logic calculations, is as follows:

a＝mod(X2 _INIT (0)+X2 _INIT (1)+X2 _INIT (2)，2)；

reg1(0)＝0；

reg1(1)＝0；

reg1(2)＝a；

reg1(3)＝X2 _INIT (0)；

reg1(4)＝X2 _INIT (1)；

reg1(5)＝X2 _INIT (2)；

reg1(6)＝a；

reg1(7)＝X2 _INIT (0)；

reg1(8)＝X2 _INIT (1)；

reg1(9)＝X2 _INIr (2)；

reg1(10)＝a；

reg1(11)＝mod(X2 _INIT (1)+X2 _INIT (2)，2)；

reg1(12)＝mod(X2 _INIT (0)+X2 _INIT (1)，2)；

reg1(13)＝mod(X2 _INIT (1)+X2 _INIT (2)，2)；

reg1(14)＝X2 _INIT (2)；

reg1(15)＝0；

reg1(16)＝0；

reg1(17)＝0；

reg1(18)＝a；

reg1(19)＝X2 _INIT (0)；

reg1(20)＝X2 _INIT (1)；

reg1(21)＝X2 _INIT (2)；

reg1(22)＝0；

reg1(23)＝0；

reg1(24)＝0；

reg1(25)＝0；

reg1(26)＝a；

reg1(27)＝X2 _INIT (0)；

reg1(28)＝X2 _INIT (1)；

reg1(29)＝X2 _INIT (2)；

reg1(30)＝a；

here reg1 may be a register in the HW circuit or a variable in SW.

Input data X2 _INIT The second part 28bit processing, first configuring 1 54bit register d, high 26bit filling 0, low 28bit filling X2 _INIT (3：30) If the HW circuit design is considered, each Cycle takes the data at the fixed position in d to perform xor processing, such as:

reg2＝d ₀ ^d ₄ ^d ₈ ^d ₁₁ ^d ₁₂ ^d ₁₅ ^d ₂₄ ^d ₂₇ ^d ₂₈ ^d ₃₅ ^d ₃₆ ^d ₄₂ ^d ₄₄ ^d ₄₇ ^d ₄₈ ^d ₅₁ ^d ₅₂ ；

register d is then shifted left by 1bit, with the lower bit being 0.

Examples are described below, assuming

X2 _INIT (3) =0011111000000000000000000000, the contents in the 31cycle registers d are as follows:

cycle#1:000000000000000000000000000011111000000000000000000000

cycle#2:000000000000000000000000000111110000000000000000000000

cycle#3:000000000000000000000000001111100000000000000000000000

cycle#4:000000000000000000000000011111000000000000000000000000

cycle#5:000000000000000000000000111110000000000000000000000000

cycle#6:000000000000000000000001111100000000000000000000000000

cycle#7:000000000000000000000011111000000000000000000000000000

cycle#8:000000000000000000000111110000000000000000000000000000

cycle#9:000000000000000000001111100000000000000000000000000000

cycle#10:000000000000000000011111000000000000000000000000000000

cycle#11:000000000000000000111110000000000000000000000000000000

cycle#12:000000000000000001111100000000000000000000000000000000

cycle#13:000000000000000011111000000000000000000000000000000000

cycle#14:000000000000000111110000000000000000000000000000000000

cycle#15:000000000000001111100000000000000000000000000000000000

cycle#16:000000000000011111000000000000000000000000000000000000

cycle#17:000000000000111110000000000000000000000000000000000000

cycle#18:000000000001111100000000000000000000000000000000000000

cycle#19:000000000011111000000000000000000000000000000000000000

cycle#20:000000000111110000000000000000000000000000000000000000

cycle#21:000000001111100000000000000000000000000000000000000000

cycle#22:000000011111000000000000000000000000000000000000000000

cycle#23:000000111110000000000000000000000000000000000000000000

cycle#24:000001111100000000000000000000000000000000000000000000

cycle#25:000011111000000000000000000000000000000000000000000000

cycle#26:000111110000000000000000000000000000000000000000000000

cycle#27：001111100000000000000000000000000000000000000000000000

cycle#28：011111000000000000000000000000000000000000000000000000

cycle#29：111110000000000000000000000000000000000000000000000000

cycle#30：111100000000000000000000000000000000000000000000000000

cycle#31：111000000000000000000000000000000000000000000000000000

the reg1 and reg2 are subjected to XOR processing, and X2 is output _UPD

Another very high speed method and apparatus for the initial jump module is described below, defining F as the state transition matrix for P operations, which is 31X 31 dimensions, and thus X2 _UPD ＝mod(F*X2 _INIT 2), wherein F X2 _INIT For Binary AND operationHowever, each element of the F matrix takes 0 or 1, no storage is needed, and only some exclusive-or combination circuit 1 cycles are needed to obtain X2 when the HW circuit is implemented _UPD 。

The common skip module is similar to the initial skip module in realizing method and device, and input data X2 _UPD And 2 parts of processing are divided, the first part is stored in reg1 after being processed by simple logic, the second part is stored in reg2 after being processed by 31 cycles, and the result of XOR between reg1 and reg2 is the output of the module. If the current L =0, the common jump module does not work, and the output of the initial jump module is the final result X2 _START (ii) a If the current L =1, the result obtained by 1 working time of the shared skip module is X2 _START (ii) a If the current L =2, writing the result obtained by 1-time work of the common jump module into X2 _UPD Then the common jump module continues to work for 1 time, and the result is X2 _START 。

Fig. 6 illustrates an implementation of the scene common skip module by taking a PBCH encoded data scrambling/decoding process skip 864bit as an example.

Input data X2 _UPD The first part of the 3-bit processing, namely some simple logic calculations, is as follows:

a＝mod(X2 _UPD (0)+X2 _UPD (1)+X2 _UPD (2)，2)；

reg1(0)＝mod(X2 _UPD (0)+X2 _UPD (2)，2)；

reg1(1)＝mod(X2 _UPD (0)+X2 _UPD (2)，2)；

reg1(2)＝mod(X2 _UPD (0)+X2 _UPD (2)，2)；

reg1(3)＝mod(X2 _UPD (0)+X2 _UPD (2)，2)；

reg1(4)＝mod(X2 _UPD (0)+X2 _UPD (2)，2)；

reg1(5)＝X2 _UPD (1)；

reg1(6)＝X2 _UPD (2)；

reg1(7)＝a；

reg1(8)＝mod(X2 _UPD (1)+X2 _UPD (2)，2)；

reg1(9)＝mod(X2 _UPD (0)+X2 _UPD (1)，2)；

reg1(10)＝mod(X2 _UPD (1)+X2 _UPD (2)，2)；

reg1(11)＝X2 _UPD (2)；

reg1(12)＝0；

reg1(13)＝0；

reg1(14)＝0；

reg1(15)＝0；

reg1(16)＝0；

reg1(17)＝a；

reg1(18)＝mod(X2 _UPD (1)+X2 _UPD (2)，2)；

reg1(19)＝mod(X2 _UPD (0)+X2 _UPD (1)，2)；

reg1(20)＝mod(X2 _UPD (1)+X2 _UPD (2)，2)；

reg1(21)＝X2 _UPD (2)；

reg1(22)＝0；

reg1(23)＝a；

reg1(24)＝mod(X2 _UPD (1)+X2 _UPD (2)，2)；

reg1(25)＝mod(X2 _UPD (0)+X2 _UPD (1)，2)；

reg1(26)＝mod(X2 _UPD (1)+X2 _UPD (2)，2)；

reg1(27)＝X2 _UPD (2)；

reg1(28)＝0；

reg1(29)＝0；

reg1(30)＝0；

input data X2 _UPD The second part 28bit processing, first configuring 156 bit register d, high 28bit filling 0, low 28bit filling X2 _UPD (3:

reg2＝d ₀ ^d ₁ ^d ₄ ^d ₅ ^d ₆ ^d ₇ ^d ₁₀ ^d ₁₁ ^d ₁₆ ^d ₁₇ ^d ₂₀ ^d ₂₀ ^d ₂₃ ^d ₃₁ ^d ₃₃ ^d ₃₇ ^d ₃₉ ^d ₄₇ ^d ₄₉ ^d ₅₂ ^d ₅₃ ^d ₅₄ ^d ₅₅ register d is then shifted left by 1bit, with the lower bit being 0.

The reg1 and reg2 are subjected to XOR processing, and the result is output

The special skip module 1-the special skip module 8 realize the secondary input state variable X2 _INIT To the output state variable X2 _START The 1 step process of (1) is realized by a very high speed method similar to an initial jump module, namely a 1cycle exclusive or combinational circuit, by considering the design of the HW circuit; it can also be implemented by a low cost method like the initial skip module, i.e. a 31cycle circuit.

And step S3: state variable X1 using preset application scene valid start position _START And X2 _START Generating a pseudo-random sequence;

when obtaining X1 _START And X2 _START The pseudo-random sequence generator may be started. Considering HW circuit design, a pseudo-random sequence generator, can generate K pseudo-random bits in 1cycle, where K =2,4,6,8, 12, 24, etc. X1 _START Calculating by an exclusive or combination circuit to obtain y1 and X2 _START Y2 is obtained through calculation of an exclusive-OR combination circuit, finally, y1 and y2 are exclusive-ored to obtain output pseudorandom bits, and X1 is updated simultaneously _START ＝y1，X1 _START = y2, i.e., y1 and y2, as input at the time of the next calculation. The device can flexibly support various scenes and hardware speed requirements.

The input parameter of the pseudo-random sequence generator is X1 _START And X2 _START After 1 calculation, K pseudo-random bits can be output, and X1 is updated simultaneously _START And X2 _START Is used for the next calculation, which is an iterative process. The implementation example is as follows:

assuming that when K =2, it is,

in a first step, using the input parameter X1 _START And X2 _START Calculate y1 (i), i =0,1,.., 30 and y2 (i), i =0,1,.., 30, the calculation formula is as follows:

y1(0)＝X1 _START (2)，y2(0)＝X2 _START (2)；

y1(1)＝X1 _START (3)，y2(1)＝X2 _START (3)；

y1(2)＝X1 _START (4)，y2(2)＝X2 _START (4)；

y1(3)＝X1 _START (5)，y2(3)＝X2 _START (5)；

y1(4)＝X1 _START (6)，y2(4)＝X2 _START (6)；

y1(5)＝X1 _START (7)，y2(5)＝X2 _START (7)；

y1(6)＝X1 _START (8)，y2(6)＝X2 _START (8)；

y1(7)＝X1 _START (9)，y2(7)＝X2 _START (9)；

y1(8)＝X1 _START (10)，y2(8)＝X2 _START (10)；

y1(9)＝X1 _START (11)，y2(9)＝X2 _START (11)；

y1(10)＝X1 _START (12)，y2(10)＝X2 _START (12)；

y1(11)＝X1 _START (13)，y2(11)＝X2 _START (13)；

y1(12)＝X1 _START (14)，y2(12)＝X2 _START (14)；

y1(13)＝X1 _START (15)，y2(13)＝X2 _START (15)；

y1(14)＝X1 _START (16)，y2(14)＝X2 _START (16)；

y1(15)＝X1 _START (17)，y2(15)＝X2 _START (17)；

y1(16)＝X1 _START (18)，y2(16)＝X2 _START (18)；

y1(17)＝X1 _START (19)，y2(17)＝X2 _START (19)；

y1(18)＝X1 _START (20)，y2(18)＝X2 _START (20)；

y1(19)＝X1 _START (21)，y2(19)＝X2 _START (21)；

y1(20)＝X1 _START (22)，y2(20)＝X2 _START (22)；

y1(21)＝X1 _START (23)，y2(21)＝X2 _START (23)；

y1(22)＝X1 _START (24)，y2(22)＝X2 _START (24)；

y1(23)＝X1 _START (25)，y2(23)＝X2 _START (25)；

y1(24)＝X1 _START (26)，y2(24)＝X2 _START (26)；

y1(25)＝X1 _START (27)，y2(25)＝X2 _START (27)；

y1(26)＝X1 _START (28)，y2(26)＝X2 _START (28)；

y1(27)＝X1 _START (29)，y2(27)＝X2 _START (29)；

y1(28)＝X1 _START (30)，y2(28)＝X2 _START (30)；

y1(29)＝mod(X1 _START (0)+X1 _START (3)，2)；

y2(29)＝mod(X2 _START (0)+X2 _START (1)+X2 _START (2)+X2 _START (3)，2)；

y1(30)＝mod(X1 _START (1)+X1 _START (4)，2)；

y2(30)＝mod(X2 _START (1)+X2 _START (2)+X2 _START (3)+X2 _START (4)，2)；

second, pseudo-random bits s (0) and s (1) are output:

s(0)＝mod(y1(29)+y2(29)，2)，

s(1)＝mod(y1(30)+y2(30)，2)，

third, updating X1 _START And X2 _START For generation of the next set of 2 bits

X1 _START ＝y1；

X2 _START ＝y2。

The fast pseudo-random sequence generation system for 5G NR provided by the invention can be realized by the step flow in the fast pseudo-random sequence generation method for 5G NR provided by the invention. Those skilled in the art can understand the fast pseudo-random sequence generation method for 5G NR as a preferred example of the fast pseudo-random sequence generation system for 5G NR.

Those skilled in the art will appreciate that, in addition to implementing the systems, apparatus, and various modules thereof provided by the present invention in purely computer readable program code, the same procedures can be implemented entirely by logically programming method steps such that the systems, apparatus, and various modules thereof are provided in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system, the device and the modules thereof provided by the present invention can be considered as a hardware component, and the modules included in the system, the device and the modules thereof for implementing various programs can also be considered as structures in the hardware component; modules for performing various functions may also be considered to be both software programs for performing the methods and structures within hardware components.

The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.

Claims (10)

1. A fast pseudo-random sequence generation method for 5G NR, comprising:

step S1: identifying valid starting position n for pseudorandom sequence application scenarios _START ；

Step S2: valid starting position n of pseudo-random sequence application scene based on identification _START Obtaining a state variable X1 of a preset effective initial position of an application scene _START And X2 _START ；

And step S3: state variable X1 using preset application scene valid starting position _START And X2 _START A pseudo-random sequence is generated.

2. The fast pseudorandom sequence generation method for 5G NR of claim 1 wherein said pseudorandom sequence application scenarios comprise PBCH encoded data scrambling/decoding process scenarios, PDSCH DMRS generation process scenarios and preset general scenarios;

effective start position n of pseudo-random bit of PBCH coded data scrambling/decoding process scene _START ：

n _START ＝1600+864*SsbIdx，SsbIdx＝0，1，...，7；

The PDSCH DMRS generates a valid start position n of a pseudorandom bit of a process scene _START ：

n _START ＝1600+X*275*i，i＝0，1，...，7，X＝8 or 12 or 24；

The effective starting position n of the pseudo random bit of the preset general scene _START Is a preset value.

3. The fast pseudo-random sequence generation method for 5G NR according to claim 1, wherein said step S2 employs:

step S2.1: obtaining the 1 st m sequence effective initial position n in the preset application scene _START The state variable after the secondary state conversion is stored;

step S2.2: the 1 st m-sequence precomputation value selector selects 1 data from the stored data to assign to the state variable X1 of the current effective initial position according to the condition of the current scene _START ；

Step S2.3: the 2 nd m-sequence state variable generator converts the initial state variable X2 _INIT Updating the state variable X2 of the effective starting position of the current application scene _START 。

4. A fast pseudo-random sequence generation method for 5G NR according to claim 3, characterized in that said step S2.3 employs: the 2 nd m sequence state variable generator selects 1 path special skip module to activate based on the current scene n path special skip module, and the initial state variable X2 _INIT Updating the shape of the valid starting position of the current application scene by using the activated special skip moduleState variable X2 _START (ii) a Or, the 2 nd m-sequence state variable generator converts the state variable X2 _INIT Completing P times of state conversion updating to X2 by an initial jump module _UPD Sharing the skip module and then dividing X2 _UPD Continuously iteratively processing L times to output and update state variable X2 of effective initial position of current application scene _START 。

5. The method as claimed in claim 4, wherein the first path of dedicated skip module is input with state variable X2 _INIT Completing P times of state conversion, and inputting state variable X2 by the second path special skip module _INIT Completing (P +864 times) or (P + 275X) state transition, …, the nth path special jump module pair input state variable X2 _INIT (P +864 (n-1)) or (P +275 (x (n-1)) state transitions are completed.

6. The fast pseudo-random sequence generation method for 5G NR according to claim 4, characterized in that in the initial skip module, input data X2 _INIT The 3-bit data in the data are subjected to XOR and assignment operation and then stored in reg1; input data X2 _INIT The remaining bit data except for the 3-bit data is stored in reg2 after being processed by 31 cycles; XOR processing reg1 and reg2 to obtain X2 _UPD ；

The 31cycle treatment adopts the following steps: the 28-bit processing is realized by configuring 1 54-bit register d, filling 0 with high 26 bits and filling X2 with low 28 bits _INIT (3：30)；

reg2＝d ₀ ^d ₄ ^d ₈ ^d ₁₁ ^d ₁₂ ^d ₁₅ ^d ₂₄ ^d ₂₇ ^d ₂₈ ^d ₃₅ ^d ₃₆ ^d ₄₂ ^d ₄₄ ^d ₄₇ ^d ₄₈ ^d ₅₁ ^d ₅₂

Register d is then shifted left by 1bit, and the lower bit is complemented by 0.

7. The fast pseudo-random sequence generation method for 5G NR according to claim 4,wherein, in the initial jump module, F is defined as the state transition matrix of P times of operation, and the current state transition matrix is 31 × 31 dimensionality, X2 _UPD ＝mod(F*X2 _INIT 2), wherein F X2 _INIT For Binary AND operation, each element of the F matrix takes either 0 or 1.

8. The fast pseudo-random sequence generation method for 5G NR according to claim 4, characterized in that in the common skip module, input data X2 _UPD The 3 bits of data in the code are subjected to XOR and assignment operation and then stored in reg1; input data X2 _UPD The remaining bit data except for the 3-bit data is stored in reg2 after being processed by 31 cycles; carrying out XOR processing on regl and reg2;

the 31cycle treatment adopts the following steps: for 28-bit processing, 1 54-bit register d is firstly configured, high 26-bit is filled with 0, and low 28-bit is filled with X2 _INIT (3：30)；

reg2＝d ₀ ^d ₄ ^d ₈ ^d ₁₁ ^d ₁₂ ^d ₁₅ ^d ₂₄ ^d ₂₇ ^d ₂₈ ^d ₃₅ ^d ₃₆ ^d ₄₂ ^d ₄₄ ^d ₄₇ ^d ₄₈ ^d ₅₁ ^d ₅₂

Then the register d is shifted to the left by 1bit, and the low bit is complemented by 0;

if the current L =0, the common jump module does not work, and the output X2 of the initial jump module _UPD For the final result X2 _START (ii) a If the current L =1, the result obtained by 1 working time of the shared skip module is X2 _START (ii) a If the current L =2, writing the result obtained by 1-time work of the common jump module into X2 _UPD Then the common jump module continues to work for 1 time, and the result is X2 _START ；......。

9. The fast pseudo-random sequence generation method for 5G NR according to claim 1, wherein said step S3 employs: obtaining corresponding state transition matrix according to the requirement of HW circuit, and updating the state variable X1 _START By indication in state transition matrixThe XOR combination circuit calculates to obtain y1; updated state variable X2 _START And calculating to obtain y2 through an exclusive-or combination circuit indicated in the state transition matrix, and carrying out exclusive-or on y1 and y2 to obtain a pseudo-random bit.

10. A fast pseudo-random sequence generation system for 5G NR, comprising:

a module M1: identifying valid starting position n for pseudorandom sequence application scenarios _START ；

A module M2: valid starting position n of pseudo-random sequence application scene based on identification _START Obtaining a state variable X1 of a preset effective initial position of an application scene _START And X2 _START ；

A module M3: state variable X1 using preset application scene valid start position _START And X2 _START A pseudo-random sequence is generated.

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