CN111835474B - PBCH-based signal processing method and device - Google Patents

PBCH-based signal processing method and device Download PDF

Info

Publication number
CN111835474B
CN111835474B CN201910320105.8A CN201910320105A CN111835474B CN 111835474 B CN111835474 B CN 111835474B CN 201910320105 A CN201910320105 A CN 201910320105A CN 111835474 B CN111835474 B CN 111835474B
Authority
CN
China
Prior art keywords
matrix
preset
information
base station
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910320105.8A
Other languages
Chinese (zh)
Other versions
CN111835474A (en
Inventor
卢炳山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Datang Mobile Communications Equipment Co Ltd
Original Assignee
Datang Mobile Communications Equipment Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Datang Mobile Communications Equipment Co Ltd filed Critical Datang Mobile Communications Equipment Co Ltd
Priority to CN201910320105.8A priority Critical patent/CN111835474B/en
Publication of CN111835474A publication Critical patent/CN111835474A/en
Application granted granted Critical
Publication of CN111835474B publication Critical patent/CN111835474B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0053—Allocation of signaling, i.e. of overhead other than pilot signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving

Abstract

The present invention relates to the field of communications, and in particular, to a method and an apparatus for processing signals based on PBCH, so as to improve the efficiency of processing signals. The method comprises the following steps: based on the characteristics of the 5G NR protocol, a corresponding target matrix is generated in advance according to various information used in the PDCH signal processing process, so that the signal processing process is directly simplified into that the original signal is multiplied by the target matrix, the calculation result can be directly used as a signal processing result, the processes of adding CRC information, channel coding, rate matching and the like do not need to be executed step by step, compared with the signal processing process in the prior art, the signal processing time is greatly shortened, the signal processing efficiency is obviously improved, the purpose of rapidly outputting the signal processing result is achieved, meanwhile, the storage space required by the information processing process is reduced to a great extent, and the system load is reduced.

Description

PBCH-based signal processing method and device
Technical Field
The present invention relates to the field of communications, and in particular, to a method and an apparatus for processing a signal based on PBCH.
Background
In a New Radio (NR) system of 5G, a signal processing procedure of a Physical Broadcast Channel (PBCH) includes: generating a PBCH original signal, scrambling the original signal, adding 24-bit Cyclic Redundancy Check (CRC) information to the scrambled original signal, and then performing channel coding and rate matching, wherein the channel coding process comprises a channel interleaving process and a polar coding process.
Specifically, referring to fig. 1, in the prior art, the signal processing process of the 5G PBCH includes the following coding flow:
first, the original signal sent on PBCH is recorded as: a is0,a1,...,aA-1Wherein the first sequence length a is 32;
next, the original signal to which the CRC information is added is recorded as: c. C0,c1,...,cK-1Wherein, the length of the second sequence K is 56;
specifically, the CRC information with 24 bits can be generated by the following formula one, where D is a preset cyclic shift sequence.
gCRC24C(D)＝[D24+D23+D21+D20+D17+D15+D13+D12+D8+D4+D2+D+1]
Formula one
Again, the channel coded original signal is recorded as: d0,d1,...,dN-1Wherein the third sequence is longDegree N is 512;
specifically, the channel coding process includes channel interleaving and polar (polar) coding.
Finally, the original signal after rate matching is recorded as: e.g. of the type0,e1,...,eE-1Wherein the fourth sequence length E-864.
However, based on the existing 5G NR protocol, the existing PBCH signal processing procedure needs to sequentially perform operations of adding CRC information, channel coding, rate matching, and the like, which results in low signal processing efficiency due to slow computation speed, and at the same time, occupies a large amount of system resources, resulting in a serious system load.
Disclosure of Invention
The embodiment of the invention provides a PBCH-based signal processing method and a PBCH-based signal processing device. To improve the signal processing efficiency.
The embodiment of the invention provides the following specific technical scheme:
a signal processing method based on a Physical Broadcast Channel (PBCH) comprises the following steps:
a base station acquires an original signal to be transmitted on a PBCH;
the base station acquires a preset target matrix, wherein the target matrix is generated after cascading the following information: related information for generating Cyclic Redundancy Check (CRC) information, related information for channel coding and related information for rate matching;
and the base station multiplies the signal sequence of the original signal by the target matrix, and takes the calculation result as a corresponding signal processing result.
Optionally, before the base station multiplies the signal sequence of the original signal by the target matrix, the method further includes:
and the base station carries out scrambling processing on the original signal.
Optionally, after the base station multiplies the signal sequence of the original signal by the target matrix to obtain a corresponding signal processing result, the method further includes:
and the base station modulates the signal processing result to generate a broadcast signal sent on the PBCH.
Optionally, the base station presets the target matrix, including:
the base station generates a corresponding CRC information generating matrix according to a preset binary sequence;
the base station sets a corresponding channel interleaving matrix according to a preset channel interleaving pattern;
and the base station generates a corresponding information filling matrix according to the preset information bit indication information.
The base station generates a corresponding polar coding matrix according to a preset basic matrix;
the base station sets a corresponding subblock interleaving matrix according to a preset subblock interleaving pattern;
the base station sets a corresponding bit selection matrix according to a preset output sequence length;
and the base station performs cascade multiplication on the CRC information generation matrix, the channel interleaving matrix, the information filling matrix, the polar coding matrix, the subblock interleaving matrix and the bit selection matrix to obtain a corresponding target matrix.
Optionally, the base station presets the binary sequence, including:
and the base station adopts the set base number, sequentially calculates the binary value corresponding to each set power value of the base number, and fills each obtained binary value to the designated bit of the sequence to obtain the corresponding binary sequence.
Optionally, the setting, by the base station, a corresponding channel interleaving matrix according to a preset channel interleaving pattern includes:
the base station determines a first element exchange mode according to a preset channel interweaving pattern, and sets a corresponding channel interweaving matrix according to the first element exchange.
Optionally, the base station generates a corresponding information filling matrix according to the preset information bit indication information.
And the base station sets the element filling position to be 1 and sets the non-element filling position to be 0 according to the preset information bit indication information to generate a corresponding information filling matrix.
Optionally, the generating, by the base station, a corresponding polar coding matrix according to a preset basic matrix includes:
and the base station performs sub-Kronecker power on the basic array to generate a corresponding polar coding matrix.
Optionally, the base station sets a corresponding sub-block interleaving matrix according to a preset sub-block interleaving pattern, including:
and the base station determines a second element exchange mode according to a preset subblock interleaving pattern, and sets a corresponding channel interleaving matrix according to the second element exchange.
Optionally, the setting, by the base station, a corresponding bit selection matrix based on a preset output sequence length includes:
the base station takes the length of a preset output sequence as a set dimension, generates a corresponding diagonal matrix, and takes the diagonal matrix as a bit selection matrix.
A signal processing apparatus based on a physical broadcast channel PBCH, comprising:
at least comprising a processor and a memory, wherein,
the memory is used for storing a preset target matrix, and the target matrix is generated after cascading the following information: related information for generating Cyclic Redundancy Check (CRC) information, related information for channel coding and related information for rate matching;
the processor is configured to acquire an original signal to be transmitted on a PBCH, acquire the target matrix, multiply a signal sequence of the original signal by the target matrix, and use a calculation result as a corresponding signal processing result.
Optionally, before the processor multiplies the signal sequence of the original signal by the target matrix, the method further includes:
the processor performs scrambling processing on the original signal.
Optionally, after the processor multiplies the signal sequence of the original signal by the target matrix to obtain a corresponding signal processing result, the method further includes:
the processor modulates the signal processing result to generate a broadcast signal transmitted on the PBCH.
Optionally, the processor presets the target matrix, including:
the processor generates a corresponding CRC information generating matrix according to a preset binary sequence;
the processor sets a corresponding channel interleaving matrix according to a preset channel interleaving pattern;
and the processor generates a corresponding information filling matrix according to the preset information bit indication information.
The processor generates a corresponding polar coding matrix according to a preset basic matrix;
the processor sets a corresponding subblock interleaving matrix according to a preset subblock interleaving pattern;
the processor sets a corresponding bit selection matrix according to the length of a preset output sequence;
and the processor performs cascade multiplication on the CRC information generating matrix, the channel interleaving matrix, the information filling matrix, the polar coding matrix, the subblock interleaving matrix and the bit selection matrix to obtain a corresponding target matrix.
Optionally, the processor presets the binary sequence, including:
the processor adopts the set base number, sequentially calculates binary values corresponding to each set power value of the base number, and fills each obtained binary value to the appointed bits of the sequence to obtain a corresponding binary sequence.
Optionally, the processor sets a corresponding channel interleaving matrix according to a preset channel interleaving pattern, including:
the processor determines a first element exchange mode according to a preset channel interleaving pattern, and sets a corresponding channel interleaving matrix according to the first element exchange.
Optionally, the processor generates a corresponding information filling matrix according to preset information bit indication information.
And the processor sets the element filling position to be 1 and sets the non-element filling position to be 0 according to the preset information bit indication information to generate a corresponding information filling matrix.
Optionally, the processor generates a corresponding polar coding matrix according to a preset basic matrix, including:
the processor conducts the basic matrix to the sub-Kronecker power of the basic matrix to generate a corresponding polar coding matrix.
Optionally, the processor sets a corresponding sub-block interleaving matrix according to a preset sub-block interleaving pattern, including:
and the processor determines a second element exchange mode according to a preset sub-block interleaving pattern, and sets a corresponding channel interleaving matrix according to the second element exchange.
Optionally, the processor sets a corresponding bit selection matrix based on a preset output sequence length, including:
the processor takes the length of a preset output sequence as a set dimension, generates a corresponding diagonal matrix, and takes the diagonal matrix as a bit selection matrix.
A storage medium storing a program for implementing a signal processing method based on a physical broadcast channel PBCH, the program, when executed by a processor, performing the steps of:
acquiring an original signal to be transmitted on PBCH;
acquiring a preset target matrix, wherein the target matrix is generated after cascading the following information: related information for generating Cyclic Redundancy Check (CRC) information, related information for channel coding and related information for rate matching;
and multiplying the signal sequence of the original signal by the target matrix, and taking the calculation result as a corresponding signal processing result.
In the embodiment of the invention, the base station generates the corresponding target matrix in advance according to various information used in the PBCH signal processing process based on the characteristics of the 5G NR protocol, so that the signal processing process is directly simplified into the process of multiplying the original signal by the target matrix, the calculation result can be directly used as the signal processing result, the processes of adding CRC information, channel coding, rate matching and the like do not need to be executed step by step, compared with the signal processing process in the prior art, the signal processing time is greatly shortened, the signal processing efficiency is obviously improved, the aim of rapidly outputting the signal processing result is achieved, meanwhile, the storage space required by the information processing process is greatly reduced, and the system load is reduced.
Drawings
Fig. 1 is a schematic diagram illustrating a PBCH signal processing process in the prior art;
FIG. 2 is a schematic flow chart of a base station setting a target matrix according to an embodiment of the present invention;
FIG. 3 is a flow chart of signal processing performed by a base station according to an embodiment of the present invention;
fig. 4 is a functional structure diagram of a base station in an embodiment of the present invention.
Detailed Description
In order to improve the signal processing efficiency, in the embodiment of the present invention, the signal processing procedure for the PBCH supported by the release 15 standard is simplified, so as to achieve the purpose of outputting the signal processing result quickly.
Preferred embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
In the embodiment of the present invention, the base station may generate a comprehensive target matrix in advance to replace a system operation of adding CRC information, channel coding, rate matching, and the like in the prior art, and a setting principle and a setting process of the target matrix will be described in detail below.
Referring to fig. 2, in the embodiment of the present invention, a detailed flow of setting a comprehensive target matrix by a base station is as follows:
step 200: and the base station generates a corresponding CRC information generating matrix according to a preset binary sequence.
Specifically, in practical applications, the CRC information of 24 bits can be obtained by inputting an original signal a ═ a of 32 bits0,a1,...,aA-1]Thus obtaining the product.
For example, a predetermined CRC formula g may be employedCRC24C(D)＝[D24+D23+D21+D20+D17+D15+D13+D12+D8+D4+D2+D+1]A corresponding CRC generator matrix G _ CRC is generated with dimensions 32x 24.
Specifically, the polynomial and the binary number have a direct correspondence: when the binary sequence is set, a set base number can be adopted, a binary value corresponding to each set power value of the base number is sequentially calculated, and each obtained binary value is filled to a designated bit of the sequence to obtain a corresponding binary sequence;
for example, the highest power of the base D is set to correspond to the highest bit of the binary number, the following bits correspond to the powers of the polynomial, and any of the powers corresponds to 1 and any of the powers corresponds to 0. If the generator polynomial is gCRC24C(D) The information may be converted into binary codes 1101100101011000100010111, and the G _ CRC information generation matrix may be generated as follows:
step a: let G _ CRC be zeros (32, 24);
step b: let G _ CRC (32): 101100101011000100010111, i.e. the last 24 bits of the generated polynomial converted to 2-ary code;
step c: let k equal to 31;
step d: g _ CRC (k,: xor ([ G _ CRC (k +1,2:31),0 ];
G_CRC(k+1,1)*[101100101011000100010111))；
step e: and k is equal to k-1, if k is greater than 0, jumping to the step d, and otherwise, outputting G _ CRC information generation matrix.
Therefore, based on the G _ CRC information generation matrix, corresponding CRC information can be generated, and specifically, the CRC information can be expressed as check vector p ═ p0,p1,p2,p3,...,pL-1]And p is mod (a × G _ CRC,2), where L is 24, which indicates the length of the CRC information.
As can be seen from the above process, the process of adding CRC information to the original signal may also be usedGenerating a matrix, namely recording the original signal added with the CRC information as c ═ c0,c1,...,cK-1]， c＝mod(a*[eye(32)G_CRC]，2)。
Step 210: and the base station sets a corresponding channel interleaving matrix according to a preset channel interleaving pattern.
Specifically, the base station determines a first element exchange mode according to a preset channel interleaving pattern, and sets a corresponding channel interleaving matrix according to the first element exchange.
For example, in the channel interleaving process, assuming that the preset channel interleaving pattern is Π (k), the bit interleaving manner characterized by it can be expressed as: c'k＝cΠ(k)K-1, where K is the length of the original signal after CRC information is added, and K-56.
As can be seen from the above process, the channel interleaving process can be regarded as a column conversion process of one matrix, and therefore, a corresponding channel interleaving matrix G _ Π can be set based on Π (k), and G _ Π is used to indicate if c ═ c [ [ c ] ]0,c1,...,cK-1]E.g., G _ Π can be designed as a matrix of size KxK: if K is 0, Π (K) is 0, then G _ Π (0,0) is 1, if K is 1, and Π (K) is 2, then G _ Π (2,1) is 1, and so on, K is 0, 1.
Then, the original signal after channel interleaving may be recorded as a first interleaving vector c '═ c'0,c'1,c'2,c'3,...,c'K-1]，c′＝mod(c*G_Π，2)。
Step 220: and the base station generates a corresponding information filling matrix according to the preset information bit indication information.
Specifically, the base station may set the element filling position to 1 and the non-element filling position to 0 according to the preset information bit indication information, and generate the corresponding information filling matrix.
For example, in the prior art, the base station obtains a first interleaving vector c '═ c'0,c'1,c'2,c'3,...,c'K-1]Then, it is necessary to fill each element in the first interleaving vector into polar and the encoded input sequence u ═ u in sequence according to the set information bit indication information0u1u2...uN-1]Where N is the length of u, and N is 512, and in u, the frozen bits need to be filled except for the information bits filling each element in the first interleaved vector. Then, the padding process can also be regarded as multiplying an information padding matrix G _ U with a size KxN, such as element c 'of the first interleaving vector, on the basis of the first interleaving vector c'kCorresponding information bit is ikThen G _ U (k, i)k) When the first interleaving vector is multiplied by the information filling matrix, the coding input sequence u is obtained, and the ith sequence of the sequence u is obtainedkThe elements are the i-th of the interleaving vector c' and the matrix G _ UkColumn multiplication, i-th due to G _ UkColumns are only G _ U (k, i)k) 1, so the result u obtainedik＝c‘k。
Then, the original signal filled with information can be recorded as a filling vector so that the filling vector U is mod (c' × G _ U, 2).
Step 230: and the base station generates a corresponding polar coding matrix according to a preset basic matrix.
Specifically, the base station performs a sub-Kronecker (Kronecker) power on the basic array to generate a corresponding polar coding matrix.
Specifically, in the polar encoding process, it is assumed that the output polar encoded output sequence (i.e., the channel encoded output sequence) d is ═ d0d1d2...dN-1]Is obtained by d ═ uGNObtaining, wherein, the polar coding moment
Figure BDA0002034365710000091
Wherein G is2The method is used for the pre-set basic array, for example,
Figure BDA0002034365710000092
while
Figure BDA0002034365710000093
Represents G2X to the Kronecker power of (a).
The above steps 210-230 can also be referred to as a channel encoding process.
Step 240: and the base station sets a corresponding subblock interleaving matrix according to the preset subblock interleaving pattern.
Specifically, the base station determines a second element exchange mode according to a preset subblock interleaving pattern, and sets a corresponding channel interleaving matrix according to the second element exchange.
For example, the sub-block interleaving process may be regarded as a column transformation process of a matrix, and a corresponding sub-block interleaving matrix G _ J may be set based on a preset sub-block interleaving pattern J, where if a k-th element J (k) of the interleaving pattern J is i, the sub-block interleaving matrix G _ J (i, k) is 1, k is 0, 1.
Step 250: and the base station sets a corresponding bit selection matrix according to the preset output sequence length.
Specifically, the base station uses a preset output sequence length as a set dimension to generate a corresponding diagonal matrix, and uses the diagonal matrix as a bit selection matrix.
In the bit selection process, the second interleaving vector after sub-block interleaving is y ═ y0,y1,y2,...,yN-1And the length of the output signal sequence after the preset rate matching is E, that is, the original signal after the rate matching is recorded as: e.g. of the typekE-1, e.g., E ═ 0,1,20,e1,...,eE-1Since E ≧ N, the bit selection process multiplies y by a matrix G _ E (bit selection matrix) with dimension NxE, the diagonal values of the matrix are G _ E (i, i) 1, i 0, 1.
The steps 240-250 may also be referred to as a rate matching process.
The original signal after rate matching can be modulated and transmitted.
Step 260: and the base station performs cascade multiplication on the CRC information generation matrix, the channel interleaving matrix, the information filling matrix, the polar coding matrix, the subblock interleaving matrix and the bit selection matrix to obtain a corresponding target matrix.
From the above steps 200 to 260, it can be seen that the calculation process of the original signal recorded as e after rate matching is: e-mod (a [ eye (32) G _ CRC)]*G_Π*G_U*GN*G_J*G_E，2)；
The above process can be equivalent to:
e＝mod(a*mod([eye(32)G_CRC]*G_Π*G_U*GN*G_J*G_E,2)，2)；
then, it is assumed that the target matrix can be recorded as G _ PBCH;
G_PBCH＝mod([eye(32)G_CRC]*G_Π*G_U*GN*G_J*G_E，2)；
therefore, in the embodiment of the present invention, e ═ mod (a × G _ PBCH,2), the dimension of G _ PBCH is 32 × 864, so that the signal processing process of the PBCH channel is simplified to be a target matrix with the dimension of right-times 32 × 864 on the original signal, the content of the target matrix is as shown in table 1, the content stored in each row in table 1 is the element of one row in G _ PBCH, table 1 adopts 16-ary storage, for example, the first 16-ary element f in row 0 in table 1 is converted into binary bit 1111, the second element 4 is converted into 0100, the third element 8 is converted into binary bit 1000, and so on, the stored matrix can be converted into binary elements. According to the protocol, the base station can pre-generate and store the target matrix locally, and call the target matrix for use in the signal processing process.
TABLE 1
Figure BDA0002034365710000111
Figure BDA0002034365710000121
Figure BDA0002034365710000131
Therefore, based on the above embodiments, referring to fig. 3, in the embodiment of the present invention, the process of the base station performing signal processing on the PBCH is as follows:
step 300: the base station acquires an original signal for transmission on the PBCH, i.e. a ═ a0,a1,...,aA-1]。
Step 310: the base station acquires a preset target matrix, wherein the target matrix is generated by cascading the following information: information related to generating CRC information, information related to channel coding, and information related to rate matching.
For a specific generation process, refer to steps 200 to 260, which are not described herein again.
Step 320: and the base station multiplies the signal sequence of the original signal by the target matrix, and takes the calculation result as a corresponding signal processing result.
Specifically, the base station may perform scrambling processing on the original signal before multiplying the signal sequence of the original signal by the target matrix.
On the other hand, after obtaining the signal processing result, the base station may modulate the signal processing result, thereby finally generating a broadcast signal transmitted on the PBCH.
Based on the foregoing embodiments, referring to fig. 4, in an embodiment of the present invention, a PBCH-based signal processing apparatus (e.g., a base station) is provided, which at least includes a memory 40 and a processor 41, wherein,
the memory 40 is configured to store a preset target matrix, where the target matrix is generated by cascading the following information: related information for generating Cyclic Redundancy Check (CRC) information, related information for channel coding and related information for rate matching;
the processor 41 is configured to obtain an original signal to be transmitted on PBCH, obtain the target matrix, multiply the signal sequence of the original signal by the target matrix, and take the calculation result as a corresponding signal processing result.
Optionally, before the processor 41 multiplies the signal sequence of the original signal by the target matrix, the method further includes:
the processor 41 performs scrambling processing on the original signal.
Optionally, after the processor 41 multiplies the signal sequence of the original signal by the target matrix to obtain a corresponding signal processing result, the method further includes:
the processor 41 modulates the signal processing result to generate a broadcast signal transmitted on PBCH.
Optionally, the processor 41 presets the target matrix, including:
the processor 41 generates a corresponding CRC information generation matrix according to a preset binary sequence;
the processor 41 sets a corresponding channel interleaving matrix according to a preset channel interleaving pattern;
the processor 41 generates a corresponding information filling matrix according to the preset information bit indication information.
The processor 41 generates a corresponding polar coding matrix according to a preset basic matrix;
the processor 41 sets a corresponding sub-block interleaving matrix according to a preset sub-block interleaving pattern;
the processor 41 sets a corresponding bit selection matrix according to a preset output sequence length;
the processor 41 performs cascade multiplication on the CRC information generation matrix, the channel interleaving matrix, the information padding matrix, the polar coding matrix, the subblock interleaving matrix and the bit selection matrix to obtain a corresponding target matrix.
Optionally, the processor 41 presets the binary sequence, including:
the processor 41 uses the set base number to sequentially calculate the binary value corresponding to each set power value of the base number, and fills each obtained binary value into the designated bit of the sequence to obtain the corresponding binary sequence.
Optionally, the processor 41 sets a corresponding channel interleaving matrix according to a preset channel interleaving pattern, including:
the processor 41 determines a first element exchange mode according to a preset channel interleaving pattern, and sets a corresponding channel interleaving matrix according to the first element exchange.
Optionally, the processor 41 generates a corresponding information filling matrix according to preset information bit indication information.
The processor 41 sets the element filling position to 1 and sets the non-element filling position to 0 according to the preset information bit indication information, and generates a corresponding information filling matrix.
Optionally, the processor 41 generates a corresponding polar coding matrix according to a preset basic matrix, including:
the processor 41 performs a Kronecker power on the basic matrix to generate a corresponding polar coding matrix.
Optionally, the processor 41 sets a corresponding sub-block interleaving matrix according to a preset sub-block interleaving pattern, including:
the processor 41 determines a second element exchange mode according to a preset sub-block interleaving pattern, and sets a corresponding channel interleaving matrix according to the second element exchange.
Optionally, the processor 41 sets a corresponding bit selection matrix based on a preset output sequence length, including:
the processor 41 uses the preset length of the output sequence as a setting dimension to generate a corresponding diagonal matrix, and uses the diagonal matrix as a bit selection matrix.
A storage medium storing a program for implementing a signal processing method based on a physical broadcast channel PBCH, the program, when executed by a processor 41, performing the steps of:
acquiring an original signal to be transmitted on PBCH;
acquiring a preset target matrix, wherein the target matrix is generated after cascading the following information: related information for generating Cyclic Redundancy Check (CRC) information, related information for channel coding and related information for rate matching;
and multiplying the signal sequence of the original signal by the target matrix, and taking the calculation result as a corresponding signal processing result.
In summary, in the embodiment of the present invention, based on the characteristics of the 5G NR protocol, a corresponding target matrix is generated in advance according to various types of information used in the PBCH signal processing process, so that the signal processing process is directly simplified to right-multiply the original signal by one target matrix, and thus the calculation result can be directly used as the signal processing result without performing the processes of adding CRC information, channel coding, rate matching, and the like step by step.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made in the embodiments of the present invention without departing from the spirit or scope of the embodiments of the invention. Thus, if such modifications and variations of the embodiments of the present invention are within the scope of the claims of the present invention and their equivalents, the present invention is also intended to encompass such modifications and variations.

Claims (19)

1. A signal processing method based on a Physical Broadcast Channel (PBCH) is characterized by comprising the following steps:
a base station acquires an original signal to be transmitted on a PBCH;
the base station presets a target matrix, including:
the base station generates a corresponding CRC information generating matrix according to a preset binary sequence;
the base station sets a corresponding channel interleaving matrix according to a preset channel interleaving pattern;
the base station generates a corresponding information filling matrix according to preset information bit indication information;
the base station generates a corresponding polar coding matrix according to a preset basic matrix;
the base station sets a corresponding subblock interleaving matrix according to a preset subblock interleaving pattern;
the base station sets a corresponding bit selection matrix according to a preset output sequence length;
the base station carries out cascade multiplication on the CRC information generating matrix, the channel interleaving matrix, the information filling matrix, the polar coding matrix, the subblock interleaving matrix and the bit selection matrix to obtain a corresponding target matrix;
the base station acquires the preset target matrix, and the target matrix is generated after cascading the following information: related information for generating Cyclic Redundancy Check (CRC) information, related information for channel coding and related information for rate matching;
and the base station multiplies the signal sequence of the original signal by the target matrix, and takes the calculation result as a corresponding signal processing result.
2. The method of claim 1, wherein the base station, prior to multiplying the signal sequence of the original signal by the target matrix, further comprises:
and the base station carries out scrambling processing on the original signal.
3. The method of claim 1, wherein after the base station multiplies the signal sequence of the original signal by the target matrix to obtain the corresponding signal processing result, the method further comprises:
and the base station modulates the signal processing result to generate a broadcast signal sent on the PBCH.
4. The method of claim 3, wherein the base station presets the binary sequence, comprising:
and the base station adopts the set base number, sequentially calculates the binary value corresponding to each set power value of the base number, and fills each obtained binary value to the designated bit of the sequence to obtain the corresponding binary sequence.
5. The method of claim 3, wherein the base station sets a corresponding channel interleaving matrix according to a preset channel interleaving pattern, comprising:
the base station determines a first element exchange mode according to a preset channel interweaving pattern, and sets a corresponding channel interweaving matrix according to the first element exchange.
6. The method as claimed in claim 3, wherein the base station generates a corresponding information padding matrix according to the preset information bit indication information, including:
and the base station sets the element filling position to be 1 and sets the non-element filling position to be 0 according to the preset information bit indication information to generate a corresponding information filling matrix.
7. The method of claim 3, wherein the base station generates the corresponding polar coding matrix according to a preset basic matrix, comprising:
and the base station performs sub-Kronecker power on the basic array to generate a corresponding polar coding array.
8. The method of claim 3, wherein the base station sets a corresponding sub-block interleaving matrix according to a preset sub-block interleaving pattern, comprising:
and the base station determines a second element exchange mode according to a preset subblock interleaving pattern, and sets a corresponding channel interleaving matrix according to the second element exchange.
9. The method of claim 3, wherein the base station sets the corresponding bit selection matrix based on a preset output sequence length, comprising:
and the base station takes the length of a preset output sequence as a set dimension, generates a corresponding diagonal matrix and takes the diagonal matrix as a bit selection matrix.
10. A signal processing apparatus based on a physical broadcast channel PBCH, comprising:
at least comprising a processor and a memory, wherein,
the processor is used for presetting a target matrix, and comprises:
generating a corresponding CRC information generating matrix according to a preset binary sequence;
setting a corresponding channel interleaving matrix according to a preset channel interleaving pattern;
generating a corresponding information filling matrix according to preset information bit indication information;
generating a corresponding polar coding matrix according to a preset basic matrix;
setting a corresponding subblock interleaving matrix according to a preset subblock interleaving pattern;
setting a corresponding bit selection matrix according to the length of a preset output sequence;
performing cascade multiplication on the CRC information generation matrix, the channel interleaving matrix, the information filling matrix, the polar coding matrix, the subblock interleaving matrix and the bit selection matrix to obtain a corresponding target matrix;
the memory is configured to store a preset target matrix, where the target matrix is generated after cascading the following information: related information for generating Cyclic Redundancy Check (CRC) information, related information for channel coding and related information for rate matching;
the processor is further configured to acquire an original signal to be transmitted on PBCH, acquire the target matrix, multiply a signal sequence of the original signal by the target matrix, and use a calculation result as a corresponding signal processing result.
11. The apparatus of claim 10, wherein the processor, prior to multiplying the signal sequence of the original signal by the target matrix, further comprises:
the processor performs scrambling processing on the original signal.
12. The apparatus as claimed in claim 10, wherein the processor, after multiplying the signal sequence of the original signal by the target matrix to obtain the corresponding signal processing result, further comprises:
the processor modulates the signal processing result to generate a broadcast signal transmitted on the PBCH.
13. The apparatus of claim 12, wherein the processor presets the binary sequence, comprising:
the processor adopts the set base number, sequentially calculates the binary value corresponding to each set power value of the base number, and fills each obtained binary value to the designated bit of the sequence to obtain the corresponding binary sequence.
14. The apparatus as claimed in claim 12, wherein said processor sets the corresponding channel interleaving matrix according to a preset channel interleaving pattern, comprising:
the processor determines a first element exchange mode according to a preset channel interleaving pattern, and sets a corresponding channel interleaving matrix according to the first element exchange.
15. The apparatus of claim 12, wherein the processor generates the corresponding information filling matrix according to the preset information bit indication information, including:
and the processor sets the element filling position to be 1 and sets the non-element filling position to be 0 according to the preset information bit indication information to generate a corresponding information filling matrix.
16. The apparatus of claim 12, wherein the processor generates the corresponding polar coding matrix from a predetermined base matrix, comprising:
the processor conducts the basic matrix to the sub-Kronecker power of the basic matrix to generate a corresponding polar coding matrix.
17. The apparatus of claim 12, wherein the processor sets the corresponding sub-block interleaving matrix according to a preset sub-block interleaving pattern, comprising:
and the processor determines a second element exchange mode according to a preset sub-block interleaving pattern, and sets a corresponding channel interleaving matrix according to the second element exchange.
18. The apparatus of claim 12, wherein the processor sets the corresponding bit selection matrix based on a preset output sequence length, comprising:
the processor takes the length of a preset output sequence as a set dimension, generates a corresponding diagonal matrix, and takes the diagonal matrix as a bit selection matrix.
19. A storage medium storing a program for implementing a signal processing method based on a physical broadcast channel PBCH, the program, when executed by a processor, performing the steps of:
acquiring an original signal to be transmitted on PBCH;
presetting a target matrix, including:
generating a corresponding CRC information generating matrix according to a preset binary sequence;
setting a corresponding channel interleaving matrix according to a preset channel interleaving pattern;
generating a corresponding information filling matrix according to preset information bit indication information;
generating a corresponding polar coding matrix according to a preset basic matrix;
setting a corresponding subblock interleaving matrix according to a preset subblock interleaving pattern;
setting a corresponding bit selection matrix according to the length of a preset output sequence;
performing cascade multiplication on the CRC information generation matrix, the channel interleaving matrix, the information filling matrix, the polar coding matrix, the subblock interleaving matrix and the bit selection matrix to obtain a corresponding target matrix;
acquiring a preset target matrix, wherein the target matrix is generated after cascading the following information: related information for generating Cyclic Redundancy Check (CRC) information, related information for channel coding and related information for rate matching;
and multiplying the signal sequence of the original signal by the target matrix, and taking the calculation result as a corresponding signal processing result.
CN201910320105.8A 2019-04-19 2019-04-19 PBCH-based signal processing method and device Active CN111835474B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910320105.8A CN111835474B (en) 2019-04-19 2019-04-19 PBCH-based signal processing method and device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910320105.8A CN111835474B (en) 2019-04-19 2019-04-19 PBCH-based signal processing method and device

Publications (2)

Publication Number Publication Date
CN111835474A CN111835474A (en) 2020-10-27
CN111835474B true CN111835474B (en) 2021-07-23

Family

ID=72912112

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910320105.8A Active CN111835474B (en) 2019-04-19 2019-04-19 PBCH-based signal processing method and device

Country Status (1)

Country Link
CN (1) CN111835474B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1842974A (en) * 2004-06-25 2006-10-04 三菱电机株式会社 Method for processing RF signal in wireless MIMO communication systems
CN101207600A (en) * 2006-12-22 2008-06-25 华为技术有限公司 Method, system and apparatus for MIMO transmission of multi transmitting antennas
CN108429553A (en) * 2017-02-15 2018-08-21 中兴通讯股份有限公司 Coding method, code device and the equipment of polarization code
EP3371890A1 (en) * 2015-12-01 2018-09-12 Huawei Technologies Co., Ltd. Signature-enabled polar encoder and decoder
CN108809332A (en) * 2017-05-05 2018-11-13 华为技术有限公司 A kind of Polar decoding transmission methods and device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8509291B2 (en) * 2008-02-08 2013-08-13 Qualcomm Incorporated Open-loop transmit diversity schemes with four transmit antennas
CN101753186B (en) * 2008-12-19 2013-04-03 电信科学技术研究院 Channel quality information estimating method used for transmitting multi-flow beam forming data
EP3501109B1 (en) * 2017-04-01 2023-12-27 Huawei Technologies Co., Ltd. Polar code transmission method and apparatus
EP3504801B1 (en) * 2017-05-12 2021-04-07 Huawei Technologies Co., Ltd. Methods and apparatus for transmission and reception with polar codes

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1842974A (en) * 2004-06-25 2006-10-04 三菱电机株式会社 Method for processing RF signal in wireless MIMO communication systems
CN101207600A (en) * 2006-12-22 2008-06-25 华为技术有限公司 Method, system and apparatus for MIMO transmission of multi transmitting antennas
EP3371890A1 (en) * 2015-12-01 2018-09-12 Huawei Technologies Co., Ltd. Signature-enabled polar encoder and decoder
CN108429553A (en) * 2017-02-15 2018-08-21 中兴通讯股份有限公司 Coding method, code device and the equipment of polarization code
CN108809332A (en) * 2017-05-05 2018-11-13 华为技术有限公司 A kind of Polar decoding transmission methods and device

Also Published As

Publication number Publication date
CN111835474A (en) 2020-10-27

Similar Documents

Publication Publication Date Title
US11171741B2 (en) Polar code transmission method and apparatus
CN107239362B (en) Parallel CRC (Cyclic redundancy check) code calculation method and system
CA2559818A1 (en) Apparatus and method for coding/decoding block low density parity check code with variable block length
CN102096609A (en) Instruction-set architecture for programmable cyclic redundancy check (CRC) computations
JP7004008B2 (en) Error correction coding method and device using channel polarization, decoding method and device
JP2000156646A5 (en) Encoding device and method, decoding device and method, information processing device and method, and storage medium
JP2005535190A5 (en)
CN1567730A (en) Device and method for channel coding/decoding in communication system
CN108809332B (en) Polar code transmission method and device
CN105471545A (en) Data packet processing method and device
US6212662B1 (en) Method and devices for the transmission of data with transmission error checking
KR102244117B1 (en) Method and apparatus for processing rate matching of polar codes
CN108540259B (en) Method and device for encoding and decoding polarization code
CN101296053A (en) Method and system for calculating cyclic redundancy check code
EP1411643B1 (en) A method and apparatus for generating an interleaved address
EP1465351A2 (en) Soft decision decoding of error correcting block codes using the fast Hadamard transform
CN111835474B (en) PBCH-based signal processing method and device
CN107017962B (en) Coding method and coder-decoder for dynamic power consumption control
US8301962B2 (en) Apparatus and method for generating a linear code
WO2019047741A1 (en) Bit interleaving and de-interleaving method and device
EP3605904B1 (en) Interleaving method and device
US7760114B2 (en) System and a method for generating an interleaved output during a decoding of a data block
CN114303320A (en) Cyclic redundancy check, CRC, for decoding using an inverse CRC generator polynomial
CN114342265A (en) Partial parallel Cyclic Redundancy Check (CRC) computation using generator matrices stored in look-up tables (LUTs)
US8316070B2 (en) Method and system for advancing a linear feedback shift register

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant