SU847314A1 - Device for interfacing electronic computer with peripheral units - Google Patents

Description

one

The invention relates to computing and can be used as a multiplex channel.

The closest to the technical essence of the present invention is a selector channel containing the I / O command register, channel control word register, channel control word address register / security key register, address register, data register, arithmetic unit, channel state word register, a buffer register, an input register, an output register and a control unit, the inputs of the I / O command register are connected to the processor outputs, and the first outputs are connected to the first inputs of the control unit, second e inputs of which are connected to the first outputs of the channel state word register, third inputs with the outputs of the first group of triggers of the channel control word register, fourth inputs with the inputs of the second group of triggers of the channel command word register and the first inputs of the output register, fifth inputs with the outputs of the third group of triggers register command channel and

the first inputs of an arithmetic logic unit connected by their second exit with the outputs of the fourth group of register triggers

5 command words of the channel, third inputs - with the first output of the channel control word address register, and outputs - with the first inputs of the channel control word register and inputs

10 of the register of the address of the control word of the channel, the second outputs of which are connected to the inputs of the register of the address connected by their outputs with RAM, the third outputs of tS to the inputs of the register of protection keys connected with their outputs to the inputs of RAM, and to the first inputs of the data register connected with their first exits and second

2C inputs with RAM; third inputs — with the second outputs of the channel status word register; fourth inputs — with the first outputs of the buffer register, second outputs — with the second inputs of the channel control word register, and third outputs — with the first inputs of the buffer register, the second outputs of which are connected to the second

30 inputs of the output register connected by the third inputs to the second outputs of the register of the I / O command, and outputs to external devices, the second inputs of the buffer register are connected to the first outputs of the input register connected by their second outputs to the inputs of the channel status word register, and inputs with external devices 1 J However, in such I / O channels, the address of the external device is transmitted from the central processor (CPU) to the channel by the channel control command Start I / O. When accessing various external devices, the CPU interrupts the execution of the program, generates the address word of the channel (ACK) and issues the Start I / O command. This reduces the system speed and reduces the effective processor speed. This disadvantage is especially pronounced when the channels operate as part of a control digital computer connected with a large number of external devices and operating with unchanged programs in real time.

The purpose of the invention is to simplify and increase the speed of the device.

The goal is achieved by the fact that the device containing the first register, second register, third register, control unit, fourth register, fifth register and sixth register, whose inputs are connected to the processor outputs, and the outputs to the first inputs of the control unit,

connected with the second INPUTS1MI with YOU. The fourth register inputs, the third inputs - with the outputs of the fifth register and the first inputs of the third register connected by the first outputs with the inputs of external devices, - the second outputs - with the first inputs of the first register, the second inputs - with the outputs of external devices and the third inputs — with the outputs of the first register — the second inputs of which are connected to the outputs of the RAM unit and the inputs of the fourth and fifth registers; the first multiplexer, the second multiplexer, and the first counter (co channel mandal words) second counter (data addresses), third counter (number of bytes) and seventh register (addresses of external devices), the first multiplexer is connected to the outputs of the main memory unit, the first inputs - to the outputs of the second counter, the second inputs - with the first inputs of the second register and the outputs of the first channel counter, the inputs of which are connected to the outputs of the RAM unit, the second multiplexer is connected to the information inputs of the RAM unit, the first inputs from the output The first register, the second inputs with the outputs of the second register inputs of which are connected with the fourth inputs of the control unit and the outputs of the third counter, the outputs of the seventh register are connected to the fourth input of the third register.

The drawing shows a device for interfacing a computer with a device.

The device contains I / O 1 processor 2, memory block 3 and external devices 4, sixth register 5, first counter b, first register 7, third register 8, second register 9, first multiplexer 10; the second multiplexer 11, the control unit 12 is the fourth register 13, the fifth register 14, the second counter 15, the seventh register 16, the third counter 17.

The device works as follows.

An I / O operation starts with a special command from processor 2, which specifies the channel address in the device and the type of I / O command (for example, Start I / O, Stop I / O, etc.). The channel control command is recorded in the sixth register 5.

On the Start I / O command, the device selects the address word of the device channel from the RAM block 3 and writes it to the first counter 6.

Before the exchange begins, control unit 12 from registers 14 and 16 generates a control word in register 8. Channel 1 transmits a control word to external device 4. Control unit 12 analyzes the contents of registers 13 and 14 and counter 17 and, depending on the type of command being executed, data transmission cycle, generates the necessary control signals.

The data exchange between the RAM 3 and the external devices 4 takes place in two stages: the data exchange between the external devices 4 and channel 1, the data exchange between channel 1 and the RAM 3.

For data exchange between channel 1 and external devices 4, a third register 8 is used. When executing a read command, data from the first register 7 is written to the third register 8, the output of which is connected to external devices 4. When the Write command is executed, data from the external device 4 goes to the third Register 8. At the end of data reception, the contents of the third register 8 are overwritten into the first register 7.

Data transfer between the channel and the RAM unit 3 occurs as follows: when executing the read command, the RAM unit 3 transfers the data address from the second counter 15 via the first multiplexer 10, data is transferred from the RAM unit 3 to the first register 7, executing the command Write to the memory unit through the first multiplexer 10 transmits the data address from the second counter 15 and through the second multiplexer 11 the data from the first register 7.

One of the functions of the device is to manage the modification of the second counter 15 and the third counter. 17. In the last cycle of each data transfer cycle, control unit 12 generates control signals that provide a modification of Bloporo and the third data address and byte counter counters.

When engaged by data or by command, the control unit modifies the address of the KSK in the first counter-. ke 6 and there is a record of the new KSK in the register 7.

Upon completion of the I / O operation in channel 1, as well as on a command from the processor 2 Stop I / O, the contents of the first counter B and the third counter 17 are recorded in the second register 9.

The interface device 1 sets the interrupt request to the processor 2. The channel state word from the second register 9 is transmitted to the memory unit 3 via the second multiplexer 11.

. The device hardware cost reduction, in contrast to the known selector channel, is achieved by using multiplexers 10 and 11 and counters b, 15 and 17 to transfer the address and data to the RAM block. This allows modifying the CSK address, data addresses and the counter bytes without a part, arithmetic-logical device used in a known channel.

In the proposed device, in contrast to the known selector channel, the address of the external device is specified in the KSK. This allows the I / O channel 1, after terminating the exchange of information with one of the external devices 4, through the chain of commands, to proceed to exchange with another external

device, do not interrupt the processor.

Claims (1)

1. Anisimov B.V., Gornets N.N. Digital I / O systems of digital computers. M., Mechanical Engineering, 1977, p. 72-73 (prototype).