RU1797722C - Input-output processor - Google Patents

Abstract

The invention relates to computer technology and can be used in high performance multiprocessor computer systems with an extensive network of external devices. It is an object of the invention to increase processor performance and expand functionality by providing restarting failures. To do this, a processor containing an arithmetic logic device, local storage device, output register, receive register, input switch, first output demultiplexer, a group of exchange units and a control unit, a priority block, input register, two output registers, a delay element, an input a data and instruction demultiplexer, an instruction decoder, an instruction generator, a boundary indicator memory block, a first and second buffer memory block, and a second output demultiplexer. 3 C.p.F., 5 ill. ate with

Description

The invention relates to computer technology and can be used in the design of multiprocessor computer complexes of high performance with an extensive network of external devices.

A known input / output processor comprising a control unit, an arithmetic unit, a register unit, exchange units, registers, switches.

However, this device is characterized by insufficient flexibility and efficiency.

Closest to the proposed technical essence of the input-output processor containing the arithmetic-logical

device, local storage device, output and receive registers, input and output switches, exchange units, control unit, the outputs of which are connected to the corresponding control inputs of the output register, arithmetic logic device, local storage device and reception register, the first output of which is connected to the first information input of the local storage device, the first output of which is connected to the information input of the arithmetic-logic device, the first output of which is connected to the first command-information input of the issuance register, the second

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the command-information input of which is connected to the second output of the local storage device, the first and second outputs of the output register are connected corresponding to the first command-information input of the input switch and the command input of the exchange side commands, the first and second command inputs of the reception register are connected respectively to the third outputs of the blocks exchange and output switch, the second output of which is connected to the information input of the exchange units, the first output of which is connected to the second command-information the input of the input switch, the input-output of the units is the input-output of the device for connecting external devices.

A disadvantage of the known device is its limited performance, due to the fact that the rate of data transfer with RAM in the exchange mode with external devices is determined by the rate of exchange of external devices. Limited functionality prevents the I / O processor from expanding the number of processing modules without loss of performance.

It is an object of the invention to increase productivity and expand functionality by providing restart of exchange upon failure.

This goal is achieved by the fact that in the input-output processor containing an arithmetic logic device, a local storage device, reception and output registers, an input switch, an output demultiplexer, exchange units, a control unit, the first, second, third and fourth outputs of which are connected to the corresponding control inputs of the issuance register, arithmetic logic device, local storage device and reception register, the first output of which is connected to the first information input of the local memory device, the first output of which is connected to the information input of the arithmetic-logic device, the output of which is connected to the command-information input of the control unit, and the command-information input of the output register is connected to the second output of the local storage device, the first and second output registers are connected to - the responsibility of the first command-information input of the input switch and the input of the task of the commands of the exchange units, the first and second command

the inputs of the reception register are connected respectively to the third outputs of the exchange units and the output demultiplexer, the second output of which is connected to the information input of the exchange units, the first output of which is connected to the second command-information input of the input switch, the input-output of the exchange units is the input-output of the device for connecting external devices, a priority block, an input and two output registers, a delay line, an input data and command demultiplexer, a command decoder, a command generator, memory are introduced boundary indicators, the first and second buffer memories, an additional output demultiplexer, and the input of the priority block connected to the control output of the reception register, the output of the priority block connected to the address input of the control block, the fifth output of which is connected to the control input of the input register, information input which is connected to the third output of the output register, the output of the input register is connected to the first information inputs, the memory of the boundary indicators and the second buffer memory, the input of the command decoder, the first the output of which is connected to the first input of the first output register, the second output of the command decoder is connected to the control input of the input demultiplexers of data and commands, the command-information input of which is the input of the device from the central processor, the second input of the memory of the boundary indicators is connected to the first output of the driver commands, the second output of which through the second output register is connected to the third input of the input switch, the output of which is connected to the output of the first buffer memory, the output of which is connected n with the input of the output demultiplexer, the third output of which is connected to the input of the delay line, the first and second outputs of which are connected to the information input of the command generator and the first command and information input of the second buffer memory, the third input of which is connected to the output of the input demultiplexer of data and commands, the second the output of which is connected to the command inputs of the command generator and the memory of the boundary indicators, the first output of which is connected to the information input of the first output register, the command input of which of the second is connected to the first output of the second buffer memory, the second output of which is connected to the information input of the second output register, the output of the first output register

connected to the third input of the reception register, the second output of the memory of the boundary indicators is connected to the second information input of the command generator, the third output of the second buffer memory is connected to the input of the additional output demultiplexer, the output of which is the output of the device to the central processor.

The essence of the invention lies in the fact that an input / output processor includes a communication device with central processing units (SLE), including an input register, a delay line, an input data and command demultiplexer, an instruction decoder, an instruction generator, a memory of boundary indicators, buffer memory, output registers, an additional output demultiplexer, which made it possible to combine the transfer of data to the main memory parallel to the operation of the exchange unit and reduce the number of requests to the central memory Info for device management, as well as reduce the time of steering effects of external devices that significantly improved performance input-output processor; the buffer memory of the input / output processor was introduced, which made it possible to transfer control information (job card) to the input / output processor, which led to an expansion of the functionality; increasing independence, ensuring restart of exchanges during failures, optimization when accessing devices, improving the performance of the input-output processor by smoothing peak loads from external devices.

Figure 1 presents a block diagram of an input-output processor (I / O); figure 2 is a diagram of an arithmetic logic device; Fig. 3 is a diagram of a control unit; Fig. 4 is a diagram of a driver; figure 5 is the format of the command.

The input-output processor contains an arithmetic logic unit (ALU) 1, a local storage device (ROM) 2. priority unit 3, output registers 4 and 5 and prima, respectively, control unit 6, input switch 7, output demultiplexer 8, input register 9 , delay line 10, input demultiplexer 11 of data and commands, decoder 12 commands, shaper 13 commands, memory 14 border indicators, buffer memory 15, blocks 16 exchange, output registers 17 and 18, additional output demultiplexer 19. buffer memory 20 I / O processor w us 21-1, 21-2 issuing addresses and

data, control buses 22-1 to 22-5 for output register 4. ALU 1, LZU 2, reception register 5, input register 9, bus 23-1 -23-3 of the commands from the exchange units 16, output 5 of which are demultiplexers 8, output register 17, bus 24-1, 24-2 of the output of reception register 5, tires 25-1, 25-2 of outputting the results of operations from the LU 2. bus 26 of the results of operations of the ALU 1, data output bus 27-1

0 and addresses in the input switch 7, the bus 27-2 issuing commands to the exchange units 16, the bus 27 -3 issuing data and commands to the input register 9, the bus 28-1, 28-2 command decryption, bus 29-1, 29- 2 memory outputs 14

5 boundary indicators, buses 30-1 - 30-3 of the output of the input registers 9. 10 and the input demux 11 data and commands, buses

31-1 -31-3 data and command fetch, bus

32-1 sampling data, 32-2 sampling bus

0 teams, bus 33-1 / 33-2 of the issuance of addresses and data.

The arithmetic-logical device contains an adder 34, switches 35. 36, 37, shifter 38, the isolator floor (VDP)

5 39, encoder 40, input registers 41, 42, intermediate register 43 of the adder, output register 44 of the adder, register 45 of the encoder, convolution 46, 47 for parity, data transmission buses 48-1, 48-2, 49-1 0 49 -3 receiving data.

The control unit 6 comprises control memory 50, an address reception control unit 51, an address counter 52, a switch 53, a return address register 54, an output

5 register 55, control bus 56, return address bus 57, address counter control bus 58-1, switch control bus 58-2, return address register control bus 59-3.

0 Command shaper 13 contains priority block 59, input switch 60, constant buffer, register 62, decoder 63 section numbers, register 64, adder 65. address register 66. number register 67,

5 output switch 68.

The blocks included in the input / output processor (Fig. 1) have the following inputs and outputs; arithmetic logic device (ALU) 1 - control input (bus 22-2), information input (bus 25-1), output (bus 26), local storage device (L memory) 2 - control input (bus 22 -3), the first information input (width 24-1), the second information input (bus 26), the first output (bus 25-1), the second output (bus 25-2), priority block 3 - information input (bus 24 -2), output to control unit 6, output register 4 - control input (bus 22-1), command-information input (bus 25-2), three

output (bus 27-1 - 27-3), reception register 5 - three command inputs (bus 23-1 23-3), control input (bus 22-4), first output (bus 24-1), second output (tire

24-2), control unit 6 - address input from priority block 3, information input (bus 26), five outputs (buses 22-1 - 22-5), input switch 7 - three command-information inputs (buses 21- 1, 27-1 and the bus from the output register 13), the output to the buffer memory 20, the output demultiplexer 8 - information input from the buffer memory 20, the first output (bus 23-2), the second output (bus 33-1); third output (bus 33-2), input register 9 - information input (bus 27-3), control input (bus 22-5), output (bus 30-1), delay line 10-information input (bus 33- 1), the first output (bus 30-2), the second output to the shaper 13 commands, input demultiplexer 11 data and commands - command and information input from the central processor, control input (bus 28-2), the first output (bus 30-3), the second output to the memory 14 of the boundary indicators, decoder 12 commands - information input (bus 30-1), first output (bus 28-1), second output (bus 28-2), driver 13 commands - information input from the delay line 10, command input from the input demultighexer of data and commands, two outputs (bus 32-1, 32-2), memory 14 border indicators - information input (bus 30-1), command in one of the input demultiplexer of data and commands, information input (bus 32-1), two outputs (29-1, 29-2), buffer memory 15- information input (bus 30-1), the first command-information input (bus 30-2), the second command-information input (bus 30-3), three outputs (bus 31-1 - 31-3), exchange units 16 - information input (bus 33-2), command input (bus 27-2 ), command-information input-output with external devices (bus 21-2), output (bus 23-1), output (bus 21-1), output register 17 - the first command input (bus 28-1), information input (bus 29-1), second command input (bus 31-1), output (bus 23-3), output register 18 - command input (bus 32-2), information input (bus 31-2), output to the input switch 7, additional output demultiplexer 19 - command-information input (bus 31-3), output to the central processor, buffer memory 20 - command-information input from the input switch 7, output to the output demultiplexer 8.

The input demultiplexer 11 of data and commands is connected by a command-information input to the output of the central processor and a control input with

the corresponding output of the decoder 12 teams. The command output of the input demultiplexer 11 of data and commands is connected to the corresponding inputs of the memory 14 of the boundary indicators and the shaper 13 teams.

0 The output of the demultiplexer 11 is connected to the second command-information input of the buffer memory 15. The first command-information input of the buffer memory 15 is connected to the output of the input register 10.

5 The output of the input register 9 is connected to the information inputs of the memory 14 of the boundary indicators, the decoder 12 of the command and the buffer memory 15. The output of the buffer memory 15 is connected to the second command input.

0 of the output register 17. The information output of the buffer memory 15 is connected to the input of the output register 18. The command is informational, the output of the buffer memory 15 is connected to the input of the additional output demultiplexer 19. The output of the additional output demultiplexer 19 is connected to the command and information input of the central processor. The information input of the input regmstra 9 is connected to the output of the output register 4, the control input of the input register 9 is connected to the output of the control unit 6. The address input of the control unit 6 is connected to the output of the priority unit 3. The control 5 input of priority block 3 is connected to the output of reception register 5. The information output of the reception register 5 is connected to the input of the local storage device (LZU) 2. The control input of the register 5

0 of reception is connected to the output of control unit 6, the control input of LZU 2 is connected to the output of control unit 6. The information input Л ЗУ 2 is connected to the output of the arithmetic-logical device (ALU) 1.

5 Information output of LZU 2 is connected to the input of ALU 1. The control input of ALU 1 is connected to the output of control unit 6, the command-information input of output register 4 is connected to the output of LZU 2. The control input of output register 4 is connected to the output of block 6 management. The command-information input of the output register 4 is connected to the first corresponding input of the input switch 7. Command output

5 of register 4 is connected to the input of the exchange units 16. The information input of the input register 10 is connected to the output of the output demultiplexer 8. The information output of the input register 10 is connected to the first information input

Shaper 13 teams. The second information input of the command generator 13 is connected to the second output of the memory 14 of the boundary indicators. The command input of the output register 18 is connected to the output of the shaper 13 teams. The second information input of the memory 14 of the boundary indicators is connected to the output of the command generator 13. The first information output of the memory 14 of the boundary indicators is connected to the input of the output register 17. The command input of the output register 1.7 is connected to the output of the decoder 12 commands. The first command input of the reception register 5 is connected to the output of the exchange units 16. The second command input of the reception register 5 is connected to the output of the output demultiplexer 8. The command input of the reception register 5 is connected to the output of the output register 17. The second command-information input of the input switch 7 is connected to the output of the exchange units 16. The third command and information input of the input switch 7 is connected to the output of the output register 18. The command and information input of the buffer memory 20 is connected to the output of the input switch 7. The information input of the output demultiplexer 8 is connected to the buffer memory 20. The information input of the exchange units 16 is connected to the output output demultiplexer 8. The input-output of the exchange units 16 is connected to the input-output of external devices. The control input ALU 1 (Fig. 2) connected to the output of the control unit 6 is connected to the inputs of the switches 35-37, the shifter 38, the isolator 39, registers 41-45. The information input of ALU 1 connected to the output of the memory device 2 is connected to the inputs of the switches 36, 37. The information output of the switch 36 is connected to the input of the register 41. The information output of the register 41 is connected to the input of the encoder 40. the input of the shifter 38, the first information input of the adder 34. The information output of the switch 37 is connected to the input of the register 42. The output of the register 42 is connected to the second information input of the adder 34. The information output of the adder 34 is connected to the input of the register of the adder 43, the second information input of the switch 35. ormatsionny output register of the adder 43 is connected to the third input of the switch 35. The data output of shifter 38 is coupled to the input of discriminator 39. The information output of discriminator 39 is connected to a first data input of switch 35. The information output of the switch 35 is connected to the input of the parity convolution 47, entering the output register

44 adder, the input of the switch 36, the input of the switch 37. The information output of the convolution 47 in parity is connected to the input of the output register 44 of the adder. 5 The information output of the encoder 40 is connected to the input of the encoder register 45 and the parity input 46. The information output of the convolution 46 in parity is connected to the input of the register 45 of the encoder.

0 The information output of the encoder register 45 is connected to the output of the adder register 44, the input of the LZU 2, the input of the control unit 6, connected to the input of the address reception control unit 51, the input of the switch 53. The address output from the priority unit 3 is connected to the input of the 51, reception control the address and input of the switch 53. The first control output of the control unit 51 is connected to the counter input

0 52 addresses. The second control output of the control unit 51 is connected to the input of the switch 53. The third control output of the control unit 51 is connected to the input 54 of the return address. The information output of the switch 53 is connected to the input of the address counter 52. The address output of the address counter 52 is connected to the input of the control memory 50. The information output of the control memory 50 is connected to the input of the output register 55. The first control output of the register 55 is connected to the input of the control unit 51. The information output of the output register 55 is connected to the input of the register 54 of the return address. The third control output of the output register 55 is connected to the input of the register 4. The fourth control output of the register 55 is connected to the input of the ALU 1. The fifth control output of the register 55 is connected to the input of the LZU 2. The sixth control output of the register 55 is connected to the input of the register 5. The seventh control output of the register 55 is connected to the input of the register 9. The control output of the demultiplexer 11 of data and commands, sub.

5 connected to the former 13 (Fig. 4), connected to the priority block 59, the input switch 60, registers 62, 64, 66, 67, the adder 65, the output switch 68. The information output of the memory 14 indicated the boundaries connected to the input of the input switch 60, the information output of the input register 10 is connected to the input switch 60 of the buffer memory 20. The address output of the input switch 60 is 5 connected to the inputs of the registers 62, 64 and the decoder of the section number 63. The address output of the decoder 63 is connected to the input of the constant buffer 61. The information output of the constant buffer 61 is connected to the input of the register 64. Information output

register 64 is connected to the adder 65, the Information output of the register 62 is connected to the adder 65. The information output of the adder 65 is connected to the registers 66 and 67 of the address and quantity. The information output of the quantity register 67 is connected to the input of the output switch 68. The address output of the address register 66 is connected to the input of the output switch 68.

To execute I / O commands, the CPU builds a queue for the wok for an exchange containing one or more I / O requirements (I / O). The request for exchange indicates all the data necessary to start the exchange. Information exchange BVV consists of several words: the command BVV, descriptor exchange (TO), which describes the clipboard in the main memory of the CPU, the word exchange (CO), which determines the operating mode of the channel, the words of the peripheral device (SPU), which indicates the number of the device in the channel and the operation of the external device, the result descriptor (DR) and the specified result descriptor (DRU) are words that are filled after the end of the exchange. . :

All operative work with external devices takes place inside the IAP without the intervention of a central processor.

For the organization of an exchange of requests from the CPU and messages about the results of exchanges in the internal memory, -20 PVV is operational. the system generates a work map, the main elements of which are: arrays of air-conditioners received from the CPU (MBEI); queue BVV to an external device (OBVU); data buffers for exchanging with external devices (WUs); DR arrays for dispensing to a CPU (MDS); device and queue table (TUSO).

To each of the elements of the work map, the operating system allocates a fixed area in memory 20; boundaries in these areas are defined by indicators of the start and end boundaries.

Work with the elements of the work map is carried out through pointers, the pointers of BBB queues to an external device and data buffers for exchange in the slave are stored in the buffer memory 20 itself, in the table of devices and queues (TUSO); pointers to the remaining elements of the job map are in memory of 14 boundary pointers.

The memory 14 of the boundary indicators contains 4 independent areas: the memory of the boundaries of the BVVR; memory tables Zn / n; memory of the boundaries of the result descriptors; command memory.

The memory is based on a multiport register memory, which can be used as a multiport

register memory - WTL 1066 (Japan) or device of US patent No. 4817051, cl. G 11 C 8/00, 1987.

Buffer memory 20 is provided on a multi-port register memory.

Buffer memory 20 is implemented on elements 565RU7 with a capacity of 256 kbps. The total memory capacity is 96 MB. The memory management timing chart 20 is wired to a read-only memory located in the memory 20, which is read cyclically, issuing with each clock cycle the memory management strobes. When organizing the buffer memory 20, the principle of combining data bus and address, widely used in domestic computers (Electronics 60, 85, NTs-80-01, D), was used.

A synchronization system is adopted in the processor; synchronization circuits are not shown.

The operation of the PVV starts from the initial state via the CPU-PVV link. In the POS, it is possible to conditionally distinguish several stages of the execution of an application for exchange: loading registers and memory of the POS; device startup; end of exchange and transfer of the exchange descriptor to the main memory of the CPU.

The first step begins with an interruption.

from the central processor, after the next quantum of command information is formed in the RAM of the CPU.

On the received interrupt in block 11

a command is formed to read the LHC (base address of the command) and is transmitted to the CPU via the buffer memory 15 and the additional output demultiplexer 19. In the central processor, the interrupt is reset and together

a word read from the OP is transmitted from the FET to the FET, in which either a single-word instruction or a pointer instruction to an array of instruction words can be found. If the word that came is a separate command, then it

transferred to the memory 14 of the boundary indicators, and the presence of this command from the output register 17 is reported to the reception register 5; in the case when a pointer command arrives at the input data and command demultiplexer 11 to read an array of command words, a response command is formed to read input / output blocks (I / O). This command is transmitted through the buffer memory 15 and an additional output demultiplexer 19 to the CPU. Upon receipt of the command to read the BWA, the CPU will begin transferring the BWW to the memory 20 of the WSP, the cache address in the WSS will be calculated from the contents of the memory 14 of the boundary indicators. The transfer of data to the memory 20 will be carried out through the buffer memory 15, the output register 18, the input switch 7.

Access to the buffer memory 20 begins by issuing a request to the memory with a command indication. The format of the command is shown in Fig.5. The command gives a memory operation code, the size of the transmitted array, and the starting address of the memory.

In block 7, upon receipt of a command indication, the operation of the priority circuit is blocked, the memory operation trigger is set, and the code of the number of the interrogator that has passed the priority circuit is encrypted. On the leading edge of the operation trigger, size and address counters are set and a memory operation operation code is provided in the buffer memory 20. The requestor number through the buffer memory 20 is transported to block 8 for switching the output.

If a write operation has arrived, then in block 7 a PTV K-signal of command confirmation is generated, which through buffer memory 20, block 8 is transmitted to block 11 and then to block 13. After that, the array recording starts directly. Data is accompanied by a sign of DAN. Upon receipt of the data, the address and size are modified and a write strobe is formed, which are transferred to the buffer memory 20. After the size counter has been exhausted, the operation trigger is reset and the counters are reset. The operation of the priority scheme and the reception of new requests are allowed. Data and instructions to block 7 are transmitted on the same buses, but with different signs. Upon receipt of the read operation, PTWK is not issued, but the requestor number is generated and transmitted similarly to the write operation. Data read from memory 20 is also followed by completeness. The word format from block 8 is shown in FIG.

The adder of the amount of transmitted data is in the command shaper 13. An instruction for memory 20 consists of an operation code, a start address, and a word count. The order in which the memory is accessed is determined by priority block 59. The start address through the input switch 60 is forwarded to register 62 and to the decoder 63-section number. Depending on the section number, a constant is selected from buffer 61 and written to register 64. The constant buffer 61 is used to store address correction constants. The buffer is a read-only memory whose read address is determined by the strobe of the decoder 63 of the section number. The operands from registers 62 and 64 go to the adder 65, the new address through the address register 66 and the output switch is executed

into the cache register and a boundary memory for storing the current value. After pumping a predetermined number of words, the pointers to the free area of memory 20 5 are corrected and recorded in the memory of the boundary pointers 14. At this point, loading the BVV into the memory 20 is completed. One is set in the interrupt register, and from the output register 17 the interrupt is transmitted to the device

0 exchange control (UPR), consisting of ALU 1, LZU 2, priority block 3, issuing register 4, reception register 5, control block 6, to reception register 5 and then to priority block 3. Priority block 3 may

5 to be performed on elements K555IV1 or others that perform the functions of a priority encoder.

Interrupt from tKB if there are no interruptions of higher priority and the UPR is not

0 is busy working out any mode, arrives in the form of an address on the control unit 6, which generates control actions to work out this interrupt. On arithmetic logic unit 1, a command is generated to read the interrupt register of the hard currency, which stores 14 boundary pointers in memory. For this, the command is sent to the input register 9 of hard currency, then to the decoder 12 of the commands, and at the address indicated in the command, from the memory 14 of the boundary indicators to the output register 17, the interrupt register is read. Through the reception register, 5 interrupts are recorded in the local memory 2, and then on the ALU

5 1 processing begins.

On buses 25-1, the input data comes from the LZU 2 to the input registers 41, 42 through the switches 36, 37. For performing cyclic operations, there is a possibility. the ability to submit to the registers 41, 42 data from the switch 35. The adder 34 provides an arithmetic logic device that performs operations similar to those performed by the chip

5 100 IP 181.

Register 43 is provided for storing intermediate calculation results.

Register 44 is for receiving calculation results. On bus 26, the output data is sent to other nodes of the device. At the output of the encoder 40 is the binary number of the highest half-word unit found in register 41. To organize work according to the priority

5, the principle provides for the output of the encoder 40 to the control inputs of the isolator field 39.

The TAP 39 serves to mask a group of bits in a 32-bit field.

 When control: 0 - 4: - lower boundary floor;

exercise: 5-9: - vorhn border floor.

VDP 39 has 32 information inputs (from 38), 14 control inputs (22-2) and 2 information outputs.

The control inputs are divided into groups:

control: 0 - 4: - the first 5 inputs;

exercise: 5 -9: - the second 5 inputs;

control 10

upr 11 - formation management

output bits

control 12

control 13

The following symptoms may appear in the interrupt register:

1. The command for the UPR has been received in the hard currency.

2. The BVV array is loaded into memory 20.

If this command is for the UPR, the control unit b generates a sequence of control signals for requesting this command from the memory 14 of the SCR boundary pointers and, having received it, proceeds to execution.

The output of the VDP depends on the control signals. Arrays 10-13, as well as the mask, which is formed according to a certain law.

Depending on the value of the signal groups control: 0-4: and control: 5-9: two 32-bit words A and B are formed according to the formula:

if the bit number of the word A is less than the value of control; 0-4: that is, this bit is O, otherwise it is 1;

if the bit number of the word B is less than or equal to the value of control: 5-9: that is, this bit is 1, otherwise it is 0.

A 32-bit mask is formed from the words A and B by modulo 2 addition.

The VDP output is formed according to the following formula: output: mask x (control 13 + input x control 11) + masks (input x control 12 + control 10).

The control unit 6 contains a specialized memory for storing gates called control memory (50).

The control strobes are read out according to the instructions given to the address counter 52 via the input address switch 53. The control strobe word read from the memory is sent to the output register 55. This word indicates which control nodes should be opened, which operations should be performed in ALU 1, in LZU 2, and input-output registers.

Part of the control word field, which is occupied by the unconditional jump address, is supplied to the address switch upon returning from the subroutine — return address 54. The address prem control section 51 generates control signals for starting the address counter 52, controlling the switch 53 and the address return register 54.

The control unit 51 is started from the ALU and unit 3 or by signals from the strobe words of the control bus 56 and loads the address counter 52 (boot mode) and

setting the account mode (+1 mode). At the input of node 51, the results of counting (,, "0, etc.) and blocking from priority block 3 are received via bus 26 from ALU 1.

At the output of node 51, a weekend occurs

0 signals 58-1 (loading mode, when the result of the calculation on bus 56 is 1 or there are blocking strobes, otherwise -H mode), signals 58-2 (in the absence of blocking from block 3, part of strobe 560 is sent to 58-2, signals 5 58-3 1 if there is 1 on bus 56. The following single commands are used in the UIP: set the UIP to the initial state; set the channel to the initial state; stop the UIP, channel; write to the UIP registers; start the UIP, channel, device .

If in the interrupt register a sign is established that the BWV array is in the Cache, the UPR requests in the hard currency the pointers from the memory of 14 boundary pointers.

The pointers contain information about the BVV array in memory 20: start and end addresses; array size.

On ALU 1, a request is generated to read the BVV from the memory 20 in the exchange control access control memory 2.

The second stage is the launch of the device. To do this, in LZU 2, an element of the table of devices and queues is considered. From the BWV, the channel start commands and the UCS device (control word of the channel) and the control system (word of the peripheral device) are formed. The control unit 6, via the communication bus with the input / output channel, transmits the USC and the control system to the channel. If

Channel 0 is not busy with other activities, for example, drawing attention from the device; it starts the device for exchange.

The third stage is the end of the exchange and the transfer of DR to the CPU.

5 After completion of the exchange, a descriptor is formed in the channel, in which the result of the channel operation is indicated. The channel requests the descriptor to be transmitted and, if there is no work with a higher priority in the UPR, it is transmitted via the priority block 3 as an address to the control unit to start the timeline for completing the exchange.

The UPR, having received the exchange descriptor from the channel, analyzes it and, if there is a failure, repeats the device startup. If there was no malfunction, the DR is recorded in the BVV. In the memory of 14 boundary pointers, pointers to the arrays of the DR are stored in the 20 VVV memory. UPR and SLE work with these indicators, having considered these

pointers, in LZU 2, the UPR forms the address of the BVV record with the DR in memory 20 and then interrupts the SLE. Having received an interruption, an SCR establishes a connection with the CPU and transfers the array of the STBs with the DR to the CPU memory. Thus, the cycle ends from generating a request for data in the CPU memory to receiving the exchange result.

The introduction of new SCR nodes and buffer memory 20 made it possible to combine the operation of communication channels with data transmission to the CPU memory. Significantly decreased

requests for service information to the CPU memory, since the MAP operation card has been completely transferred to the memory 20. It has become possible to restart exchanges that failed with the intervention of the CPU.

Claims (4)

SUMMARY OF THE INVENTION 1. An input-output processor comprising an arithmetic logic device, a local storage device, an output register, a reception register, an input switch, a first output demultiplexer, a group of exchange units and a control unit, the first, second, third and fourth outputs of which are connected respectively to the input of the synchronization register of the output, the input of the operation of the arithmetic-logical device, the input mode of the logical storage device and the input of the synchronization of the reception register, the first output of which is connected connected to the first information input of the local storage device, the first output of which is connected to the information input of the arithmetic logic device, the output of which is connected to the operation input of the control unit, the information input of the output register is connected to the second output of the local storage device, the first and second outputs of the output register are connected respectively with the first information input of the input switch and the command input of the group exchange blocks, the first and second information inputs of the register receptions are connected respectively to the third outputs of the group exchange units and the first output of the first output demultiplexer, the second output of which is connected to the information inputs of the group exchange units, the third output of the first output demultiplexer is connected to the second information input of the input switch, the inputs and outputs of the group exchange units form an input - the output of the device for connecting to the input-output of external devices, characterized in that, in order to increase productivity and expand the functionality By providing a restart of the exchange during failures, a priority block, an input register, two output registers, a delay element, an input data and command demultiplexer, a command decoder, a command generator, a memory of boundary indicators, the first and second blocks are introduced into it buffer memory and a second output demultiplexer. moreover, the input of the priority block is connected to the second output of the reception register, the output of the priority block is connected to the address input of the control unit, the fifth output of which is connected to the synchronization input of the input register, the information input of which is connected to the third output of the output register, the output of the input register is connected to the first information inputs a boundary pointer memory block and a second buffer memory block and an instruction decoder input, the first output of which is connected to the first information input of the first output register , the second output of the command decoder is connected to the control input of the input data and command demultiplexer, the information input of which is the input of the device for connecting to the output of the central processor, the second information input of the boundary indicator memory unit is connected to the first output of the command generator, the second output of which the output register is connected to the third information input of the input switch, the output of which is connected to the input of the first block of buffer memory, the output of which is connected to the input the first output demultiplexer, the third output of which is connected to the input of the delay element, the first and second outputs of which are connected to the information input of the command generator and the first information input of the second block of buffer memory, the third input of which is connected to the output of the input demultiplexers of data and commands, the second output of which is connected with command inputs of a command generator and a memory block of boundary indicators, the first output of which is connected to the information input of the first output register, the command od coupled to a first output of the second buffer memory unit, the second output of which is connected to information input of the second output register, the output of the first output register is connected to the third information input of the reception register, the second output of the boundary pointer memory block is connected to the second information input of the command generator, the third output of the second buffer memory block is connected to the input of the second output demultiplexer, the output of which is output of the device for connecting to the input of the central processor. 2. The processor according to claim 1, with the fact that the arithmetic-logic device contains an adder, three switches, a shifter, a gender isolator, an encoder, two input registers, an intermediate adder register, an output adder register, encoder register, two adders modulo two, the first information inputs of the first and second switches connected to the information input of the device, the second information inputs of the first and second switches connected to the output of the third switch, the output of the first switch through the first input register is connected to the information inputs of the encoder, shifter and the first information input of the adder, the second information input of which is connected through the second input register to the output of the second switch, the output of the encoder is connected to the first information input and through the first adder modulo two with the second information input of the encoder register the output of which is connected to the output of the device, the output of the shifter through the isolator floor is connected to the first information input of the third switch, the second information whose input and the input of the intermediate register of the adder are connected to the output of the adder, the output of the intermediate register is connected to the third information input of the third switch, the output of which is connected to the first information input and through the second adder modulo two with the second information input of the output register of the adder, the output of which is connected to the output of the device, the control inputs of the first, second and third switches, the synchronization inputs of the first and second input registers, the control inputs of the adder, shift bodies, the clock input of encoder register control input extractor floor and clock inputs of the intermediate register and adder output register coupled to the adder input of the device operation. 3. The processor according to claim 1, with the exception that the control unit comprises control memory, an address reception synchronization unit, an address counter, a switch, a return address register, an output register, the first information the inputs of the synchronization node for receiving the address and the switch are connected to the address input of the block, the input of the operation of the block is connected to the second information inputs of the switch and the node for synchronizing the reception of the address, the control input of which is connected to the first group of outputs of the output register, the second group of outputs of which connected to the third information input and through the address register with the fourth information input of the switch, the first, second and third groups of outputs of the address reception synchronization unit are connected respectively to the clock input of the address counter, the control input of the switch and the synchronization input of the address register, the output of the switch through the address counter is connected with the information input of the control memory, the output of which is connected to the information input of the output register, the third, fourth, fifth, sixth and seventh groups of outputs you one register connected to first, second, third, fourth and fifth unit outputs, 4. The processor according to claim 1, wherein the command generator comprises a priority block, an input switch, a constant buffer, three address registers, an adder, a section number decoder, a quantity register, an output switch, and the first and second information inputs of the driver are connected. to the first and second information inputs of the input switch, the first control input of which is connected to the command input of the driver and is also connected to the synchronization inputs of the first, second and third address registers, equal to the adder input, the quantity register synchronization input, the control inputs of the output switch and the priority block, the output of which is connected to the second control input of the second switch, the output of which is connected to the information inputs of the first address register, the decoder of the section number and the first information input of the second address register , the second information input of which is connected through the constant buffer to the output of the section number decoder, the outputs of the first and second address registers are connected respectively with the first and second information inputs of the adder, whose output is connected to the data input of the register number and the first information input of the third address register, the second information input of which is connected to the command input of the shaper, the outputs of the third address register and the quantity register are connected respectively, with the first and second information inputs of the output switch, the first and second outputs of which are the first and second outputs of the driver, respectively. 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