SU842801A1

SU842801A1 - Digital converter of coordinates

Info

Publication number: SU842801A1
Application number: SU792752933A
Authority: SU
Inventors: Евгений Федорович Киселев
Original assignee: Предприятие П/Я В-8150
Priority date: 1979-04-16
Filing date: 1979-04-16
Publication date: 1981-06-30

Description

(54) ЦИФРОВОЙ ПРЕОБРАЗОВАТЕЛЬ КООРДИНАТ(54) DIGITAL COORDINATE CONVERTER

Изобретение относитс к вычислительной технике и предназначено дл воспроизведени по известным кодам пол рных координат и измер емой величины кодов ее пр моугольных координат и наоборот.The invention relates to computing and is intended to reproduce, using known codes, the polar coordinates and the measured value of the codes of its rectangular coordinates and vice versa.

Известно устройство 1, обладающее низкими функциональными возможност ми .A device 1 is known that has low functionality.

Наиболее ,близким по технической сущности к предлагаемому изобретению вл етс цифровой преобразователь координат, содержащий регистр угла, два сумматора, синусно-косинусный преобразователь, первый числоимпульсный умножитель, два регистра Н два счетчика, причем выходы разр дов первого и второго регистров подключены к разр дным .входам соответствующих счетчиков, выходы знаковых разр дов первого и второго регистров соединены с соответствующими входами первого сумматора, выход которого подключен к первому входу второго сумматора, входы первой группы синусно-косинусного преобразовател подключены к выходам разр дов регистра угла, входы первой и второй групп первого число-импульсного умножител соединены соответственно с выходами синуса и косинуса синуснокосинусного преобразовател 2}.The closest to the technical essence of the present invention is a digital coordinate converter containing an angle register, two adders, a sine-cosine converter, a first number-pulse multiplier, two registers H two counters, and the outputs of the bits of the first and second registers are connected to bits. the inputs of the respective counters, the outputs of the sign bits of the first and second registers are connected to the corresponding inputs of the first adder, the output of which is connected to the first input of the second adder , the inputs of the first sine-cosine converter group are connected to the outputs of the angle register bits, the inputs of the first and second groups of the first number-pulse multiplier are connected respectively to the sine and cosine sine-converter outputs 2}.

Недостаток известного устройстванизкое быстродействие.A disadvantage of the known device is a quick response.

Целью изобретени вл етс повышение быстродействи .The aim of the invention is to increase speed.

Поставленна цель достигаетс тем что в устройство, содержащее регистр угла, два сумматора, синусно-косинусный преобразователь, первый числоимпульсный умножитель, два регистра и два счетчика, причем выходы разр дов первого и второго регистров подключены к разр дным входам соответствующих счетчиков, выходы знаковых разр дов первого и второго регистров, соединены с соответствующими входами первого сумматора, выход которого подключен к первому входу второго сумматора, входы первой группы синусно-косинусного преобразовател подключены к выходам разр дов регистра угла, входы первой и второй групп п ервого число-импульсного умножител соединены соответственно с выходами синуса и косинуса синуснокосинусного преобразовател , дополнительно введены блок управлени .The goal is achieved by the fact that the device containing the angle register has two adders, a sine-cosine converter, a first pulse-multiplier, two registers and two counters, the outputs of the bits of the first and second registers are connected to the bit inputs of the corresponding counters, the outputs of sign bits the first and second registers are connected to the corresponding inputs of the first adder, the output of which is connected to the first input of the second adder, the inputs of the first group of sine-cosine converter connect us to discharge angle outputs of register rows, the inputs of the first and second groups ervogo n-number of pulse multipliers connected respectively to the outputs of the sine and cosine sinusnokosinusnogo transducer, the control unit is further introduced.

второй число-импульсный умножитель, коммутатор и функциональный преобразователь , причем входы второй групп синусно-косинусного преобразовател подключены к выходам функционального преобразовател , знаковому выходу первого регистра и выходу первого сумматора, второй вход второго сум|Матора подключен к выходу старшего разр да функционального преобразовател , входы первой и второй групп второго число-импульсного умножител подключены соответственно к выходам первого и второго регистров, выходы второго число-импульсного умножител соединены с первой группой импульсны входов коммутатора, втора группа импульсных входов которого соединена с выходами координат первого числоимпульсного умножител , выходы коммутатора подключены соответственно ко входам вычитани первого и второго счетчиков, входы блока управлени с первого по п тый соединены соответственно с выходами первого и второго сумматоров, первого и вторго счетчиков и выходом конца развертки первого .число-импульсного умножител , выходы блока управлени с первого по шестой соединены соответственно со входами установочным и тактовым первого число-импульсного преобразовател , запуска счетчиков, управлени коммутатора и синусно-косинусного преобразовател , входом коррекции и тактовым входом второго число-импульсного умножител , причем блок управлени содержит шесть триггеров , четыре элемента 2И-ИЛИ, шесть элементов И и три элемента ИЛИ, причем первый вход блока управлени соединен с первым и вторым входами первого элемента 2И-ИЛИ, третий и четвертый входы которого соединены с третьим и четвертым входами блока управлени , а его выход подключен к первому входу первого элемента И, второй вход которого соединен с пр мым выходом первого триггера, первым входом второго элемента И и тактовым входом второго триггера, инверсный выход которого соединен со входом третьего триггера, выход которого подключен к первому входу второго элемента 2И-2ИЛИ, второй вход которого подключен к первому входу третьего и четвертого элементов И и тактовому входу блока управлени , третий вход второго элемента 2И-ИЛК соединен с первым и вторым входами третьего элемента 2И-ИЛИ, пр мым выходом второго триггера и четве ртым выходом блока управлени , четвертый вход второго элемента 2ИИЛИ соединен с первым входом п того элемента И, тактовым входом четвертого триггера и п тым входом блока управлени , выход второго элементаthe second number-pulse multiplier, the switch and the functional converter, the inputs of the second sine-cosine converter groups are connected to the outputs of the functional converter, the sign output of the first register and the output of the first adder, the second input of the second sum | Matator is connected to the output of the higher bit of the functional converter, inputs the first and second groups of the second pulse number multiplier are connected respectively to the outputs of the first and second registers; the outputs of the second pulse number multiplier connected to the first group of pulse inputs of the switch, the second group of pulse inputs of which are connected to the coordinate outputs of the first pulse multiplier, the switch outputs are connected respectively to the subtracting inputs of the first and second counters, the inputs of the control unit from the first to the fifth are connected respectively to the outputs of the first and second totalizers, the first and second counters and the output of the sweep end of the first .pulse multiplier, the outputs of the control unit from the first to the sixth are connected respectively to inputs of the setup and clock of the first number-pulse converter, start of the counters, switch control and sine-cosine converter, correction input and clock input of the second number-pulse multiplier, the control unit contains six triggers, four 2I-OR elements, six AND elements and three element OR, the first input of the control unit is connected to the first and second inputs of the first element 2И-OR, the third and fourth inputs of which are connected to the third and fourth inputs of the control unit, and its output connected to the first input of the first element And, the second input of which is connected to the direct output of the first trigger, the first input of the second element And and the clock input of the second trigger, the inverse output of which is connected to the input of the third trigger, the output of which is connected to the first input of the second element 2I-2IL , the second input of which is connected to the first input of the third and fourth elements AND and the clock input of the control unit, the third input of the second element 2I-ILK is connected to the first and second inputs of the third element 2I-OR, the forward output second th trigger rtym quat and output control unit, fourth input 2IILI second member connected to the first input of the fifth AND gate, a clock input of a fourth flip-flop and a fifth input of the control unit, the output of the second member

2И-ИЛИ соединен с дес тым выходом блока управлени и тактовым входом п того триггера, вход которого соединен со входом запуска второго вычислени блока управлени , первыми входами первого три,ггера, первого элемента ИЛИ и первым и вторым входами четвертого элемента 2И-ЙЛИ, третий вход которого соединен с выходом первого элемента И и дев тым выходом блока управлени , четвертый вход четвертого элемента 2И-ИЛИ соединен с выходом шестого элемента И, вторым входом второго элемента И и п тым выходом блока управлени , выход четвертого элемента 2И-ИЛИ соединен с седьмым выходом блока управлени , третий выход которого соединен с выходом первого элемента ИЛИ, второй вход которого соединен с выходом четвертого элемента И и тактовым входом первого триггера, второй вход которого соединен с инверсным выходом п того триггера и входом второго триггера, третий и четвертый входы третьего элемента 2И-ИЛИ соединены со вторыми входом блока управлени , п тый и шестой входы третьего элемента 2И-ИЛИ подключены соответственно к первому и второму входам второго элемента ИЛИ, выходкоторого соединен с тактовым входом шестого триггера, первый вход которого соединен со входом запуска первого решени блока управлени , входом четвертого триггера и первым входом шестого элемента И, второй вход которого соединен со вторым входом п того элемента И и пр мым выходом п того трипера, третий вхо шестого триггера подключен к инверсному выходу первого триггера, выход тре;гьего элемента 2И-ИЛИ подключен к тактовому входу третьего триггера, пр мой выход четвертого триггера соединен со вторым входом четвертого элемента И, выход которого соединен со вторым выходом блока управлени , первый вход которого соединен с инверсным выходом четвертого триггера, выход шестого тригера соединен со вторым входом третего элемента И, выход которого соединен с шестым выходом блока управлени и первым входом третьего элемента ИЛИу второй вход которого соединен с выходом второго элемента И, выход третьего элемента ИЛИ соединен с восьмым выходом блока управлени , причем функциональный преобразователь содержит три счетчика, умножитель , блок пам ти и элемент задержки , причем выход переполнени умножител через первый счетчик и блок пам ти подключен к информационным входам умножител , установочные входы счетчиков и умножител подключены к первому входу функционального преобразовател , второй вход которого соединен с тактовым входом умножител , число-импульсный выход которого соединен с выходом суммировани второго и вычитани третьего счетчиков, выходы разр дов второго.счетчика подключены к входам разр дов третьего: счетчика, вход записи которого через элемент задержки подключен к третьему входу функционального преобразовател , выходы третьего счетчика вл ютс выходами функционального преобразовател . На фиг. 1 приведена блок-схема устройства; на фиг. 2 - то же; на фиг. 3 - схема функционального прео разовател . Устройство содержит регистр 1 угла, регистры 2 и 3, счетчики 4 и число-импульсные умножители 6 и 7, функциональный преобразователь 8, сумматоры 9 и 10, синусно-косинусны преобразователь 11, блок 12 управлени и коммутатор 13, входы 14 - 1 блока 12 управлени , выход 17 перво го сумматора 9, выход 18 второго сумматора 10, входы 19-21 блока управлени , выходы 22-30 блока 12 управлени , выходы 31-32 первого 2 5 второго 3 регистров, выходы 33 и 34 и входы 35 и 36 синусно-косинусного преЬбразовател 11, входы 37-40 и выходы 41 и 42 коммутатора 13, выходы 43 число-импульсного умножител 7, выходы 44 и .45 знаков синуснокосинусного преобразовател 11, выход 46 блока 12 управлени . Функциональный преобразователь 8 содержит число-импульсный умножител 47, счетчик 48, блок 49 пам ти, счетчики 50 и 51 элемент 52 задержк Блок 12 управлени содержит триг геры 53-58, элемент 2И-ИЛИ 59, элемент ИЛИ 60, элемент 2И-ИЛИ 61, эле менты 62-67 И, элементы 2И-ИЛИ 68 и 69 и элементы ИЛИ 70 и 71. Устройство может выполн ть как первое вычисление-преобразование по л рных координат Ф и r(t) и пр мо- угольные координаты Y(t) и X (t), так и второе вычисление-воспроизведение по пр моугольным координатам Y2 и Х2 пол рных координат S 2 и г2, Во времени работает устройство циклически так, что на каждый цикл его работы выполн етс цикл первого вычислени и первый такт второго вычислени , если он разрешен блоком 12 управлени . Каждый цикл второго вычислени осуществл етс за два такта , первый из которых выполн етс : одновременно с одним из циклов первого вычислени а в другом (последующем) цикле перво го вычислени выполн етс второй такт второго вычислени , т.е. второй такт второго вычислени выполн етс непосредственно с помощью одного из циклов первого вычислени . Причем, в первом такте второго вычислени определ етс код координаты Ф2, 9Овтором - код координаты г2. В каждом цикле работы устройства можно выделить два цикла периода TV и Т,, св занных между собой так,что в каждом периоде предыдущего цикла производитс подготовка устройства дл работы в течение периода Т, последующего цикла. В периоде Т по углу Ф предыдущ го цикла и по текущей координате r(t) устройство производит вычисление текущих координат Y(t) и X(t), а также выполн ет первый такт второго вычислени , если выполнение этого такта разрешено блоком 12 управлени . Запуск каждого цикла работы и запуск второго вычислени производитс с входов 14 и 15 соответственно по ийпульсам запуска цикла (ИЗЦ) 14, следующим с частотой К, и по импульсам запуска второго вычислени (ИЗВ) 15,. следующим с частотой Fj F, /2. Работа устройства синхронизируетс с входа 16 по тактовым импульсам (ТИ) 16, следующим с частотой F . . При этом ИЗЦ 14 и ТИ 16 синхронизированы между собой так, что ИЗЦ 14 приходит и длитс в промежутке времени , когда очередной ТИ 16 отсутствует . Устройство работает следующим образом . Начина с того момента времени перед поступлением очередного ИЗЦ 14, когда триггеры блока 12 управлени тогда триггер 53 наход тс в второго вычислени состо нием О непосредственно или через другие триггеры устанавливает фиксированно в О триггеры 55-58 и запрещает выработку блоком 12 управлени соответствующих сигналов вторичного вычислени (т.е. сигналов на выходах 24 - 30 и 46). Триггер 54 первого вычислени запрещает работу элемента 64, а также выдает на выход 22 блока 12 управлени логический сигнал П22 1, которым .фиксированно установлен в О умножитель 7. На первую и вторую группы входов умножител 7 с групп выходов 23 и 34 генератора функций поступаю.т п-разр дные коды функций и (п+2)-разр дного кода аргумен та (угла) такого, то 24(1-2) , причем п 10. Предположим, что в периоде Тфр предыдущего цикла П25 было также равно О. Следовательно, на входах умножител 7 содержитс информаци дл выполнени первого вычислени по углуЦ Ц . В это врем в других узлах устройства т.е. регистрах 2 и 3, счетчиках 4 и 5, умножителе 6, и функциональном преобразователе 8 содержитс информаци , обусловленна предыдущими циклами работы устройства . Цикл работы устройства начинаетс с приходом очередного ИЗЦ 14 на блок 12 управлени , в котором по ИЗЦ 14 триггер 54 переключаетс в , разрешает работу элемента 64 и вырабатывает на выходе 22 блока 12 управлени логический сигнал И22-0, который разрешает работу умножител 7.2I-OR is connected to the tenth output of the control unit and the clock input of the fifth trigger, the input of which is connected to the start input of the second calculation of the control unit, the first inputs of the first three, the second, the first element OR, and the first and second inputs of the fourth element 2I-YLI, the third the input of which is connected to the output of the first element AND and the ninth output of the control unit, the fourth input of the fourth element 2I-OR is connected to the output of the sixth element AND, the second input of the second element AND and the fifth output of the control unit, the output of the fourth element and 2I-OR is connected to the seventh output of the control unit, the third output of which is connected to the output of the first OR element, the second input of which is connected to the output of the fourth AND element and the clock input of the first trigger, the second input of which is connected to the inverse output of the fifth trigger , the third and fourth inputs of the third element 2I-OR are connected to the second input of the control unit, the fifth and sixth inputs of the third element 2I-OR are connected respectively to the first and second inputs of the second element OR, the output of which one with the clock input of the sixth trigger, the first input of which is connected to the start input of the first decision of the control unit, the input of the fourth trigger and the first input of the sixth element And, the second input of which is connected to the second input of the fifth element And the direct output of the fifth tripper, the third input the sixth flip-flop is connected to the inverse output of the first flip-flop, the output of the three; the giy element 2I-OR is connected to the clock input of the third flip-flop; the direct output of the fourth flip-flop is connected to the second input of the fourth element I, the output of which one with the second output of the control unit, the first input of which is connected to the inverse output of the fourth trigger, the output of the sixth trigger is connected to the second input of the third element I, the output of which is connected to the sixth output of the control unit and the first input of the third element ORI the second input of which is connected to the output of the second element And, the output of the third element OR is connected to the eighth output of the control unit, with the functional converter comprising three counters, a multiplier, a memory unit and a delay element, the output being The multiplier is connected via the first counter and the memory unit to the multiplier information inputs, the counters and multiplier setup inputs are connected to the first input of the function converter, the second input of which is connected to the multiplier clock input, the pulse output of which is connected to the second sum output and the third counter output. , the outputs of the bits of the second. counter are connected to the inputs of the bits of the third: counter, the recording input of which through the delay element is connected to the third input functionally The third converter, the outputs of the third counter, are the outputs of the functional converter. FIG. 1 shows a block diagram of the device; in fig. 2 - the same; in fig. 3 is a diagram of a functional transducer. The device contains angle register 1, registers 2 and 3, counters 4 and number-pulse multipliers 6 and 7, functional converter 8, adders 9 and 10, sine-cosine converter 11, control unit 12 and switch 13, inputs 14 - 1 block 12 control, output 17 of the first adder 9, output 18 of the second adder 10, inputs 19-21 of the control unit, outputs 22-30 of the control unit 12, outputs 31-32 of the first 2 5 second 3 registers, outputs 33 and 34 and inputs 35 and 36 sine cosine transformer 11, inputs 37-40 and outputs 41 and 42 of switch 13, outputs 43 pulse number multiplier 7, output 44 and .45 sine-sinus transducer characters 11, output 46 of control unit 12. The functional transducer 8 contains a number-pulse multiplier 47, a counter 48, a memory block 49, counters 50 and 51 a delay element 52. The control block 12 contains triggers 53-58, an element 2I-OR 59, an element OR 60, an element 2I-OR 61 , elements 62-67 AND, elements 2I-OR 68 and 69, and elements OR 70 and 71. The device can perform as the first calculation-transformation on the polar coordinates F and r (t) and the rectangular Y coordinates (t ) and X (t), as well as the second calculation-reproduction on the rectangular coordinates Y2 and X2 of the polar coordinates S 2 and r2. In time, the device operates cyclic so that for each cycle of its operation, the cycle of the first calculation and the first cycle of the second calculation are performed if it is enabled by the control unit 12. Each cycle of the second calculation is performed in two cycles, the first of which is performed: simultaneously with one of the cycles of the first calculation and in the other (subsequent) cycle of the first calculation, the second cycle of the second calculation is performed, i.e. The second cycle of the second calculation is performed directly using one of the cycles of the first calculation. Moreover, in the first cycle of the second calculation, the coordinate code F2 is determined; 9 The second is the coordinate code r2. In each cycle of the device operation, two cycles of the period TV and T ,, can be distinguished, which are interconnected so that in each period of the previous cycle the device is prepared for operation during the period T and the subsequent cycle. In the period T of the angle F of the previous cycle and the current coordinate r (t), the device calculates the current coordinates Y (t) and X (t), and also performs the first cycle of the second calculation if the execution of this cycle is enabled by control unit 12. The start of each cycle of operation and the start of the second calculation are performed from the inputs 14 and 15, respectively, using the cycle start pulse (RFP) 14, followed by the frequency K, and the second calculation start pulse (WPI) 15 ,. next with frequency fj f, / 2. The operation of the device is synchronized from input 16 according to clock pulses (TI) 16, followed by a frequency F. . At the same time, IZTs 14 and TI 16 are synchronized with each other so that IZTs 14 comes in and lasts in the period of time when the next TI 16 is absent. The device works as follows. Starting from that point in time before the arrival of the next IZZ 14, when the triggers of the control unit 12 then the trigger 53 is in the second computation, the state O directly or through other triggers sets the triggers 55-58 fixedly in O and prohibits the control unit 12 from producing the corresponding secondary computation signals (i.e. signals at outputs 24-30 and 46). The trigger 54 of the first computation prohibits the operation of element 64, and also outputs, at output 22 of control unit 12, a logic signal P22 1, which is fixed to O multiplier 7. The first and second input groups of multiplier 7 are received from output groups 23 and 34 of the function generator. t n-bit codes of functions and (n + 2) -discharge code of the argument (angle) of such, then 24 (1-2), and n 10. Suppose that in the period Tfr of the previous cycle P25 was also O. Consequently, the inputs of the multiplier 7 contain information for performing the first calculation on the angle Q . At this time, in other nodes of the device i. the registers 2 and 3, the counters 4 and 5, the multiplier 6, and the functional converter 8 contain information related to the previous cycles of operation of the device. The operation cycle of the device starts with the arrival of the next IZC 14 to the control unit 12, in which, according to the IZZ 14, the flip-flop 54 switches to, enables the operation of the element 64 and generates a logical signal I22-0 at the output 22 of the control unit 12, which enables the operation of the multiplier 7.

В некоторый момент времени после окончани ИЗЦ 14 на выход 23 блока 12 управлени через элемент 64 проход т ТИ 16 и, следовательно, поступают на тактовый вход умножител 7.At some point after the end of IZC 14, at output 23 of control unit 12, TI 16 passes through element 64 and, therefore, enters the clock input of multiplier 7.

Умножитель 7 реализует одновременное умножение параллельных кодов первого числа /з1пФ/и второго числа на общий мен ющийс сомножитель r(t), представленный .на тактовом входе умножител 7 число-импульсным кодом (ЧИК) последовательностью ТИ 16.The multiplier 7 realizes the simultaneous multiplication of the parallel codes of the first number (z1pF) and the second number by the common changing multiplier r (t) represented by the clock input of the multiplier 7 number-pulse code (CHIK) with the TI 16 sequence.

Умножитель 7 на входе 39 вырабатывает ЧИК /У/, а на выходе 40-ЧИК /X/ соответственно координат /У/ м /X/, определ емых выражени миThe multiplier 7 at the input 39 produces a CHIC / U /, and the output 40-CHICK / X /, respectively, of the coordinates / Y / m / X /, defined by the expressions

(ъ)./5шФ/(b) ./ 5shF /

(1)(one)

/X/-r,(4-/c°s ;i/ X / -r, (4- / c ° s; i

Знаковые разр ды координат /У/ и /X/ (т.е. ЗнУ и ЗнХ) снимаютс с выходов 44 и 45 генератора функций 11 так, чтоThe sign bits of the coordinates / V / and / X / (i.e., ZnU and ZnH) are removed from outputs 44 and 45 of the function generator 11 so that

П44 ЗнУ Зн 81пФ а,2 П45 ЗнХ Зн COBS 1, i где а,о и а - логические коэффициенты 12-го и 11-го старших разр дов кода угла.P44 ZnU Zn 81pF a, 2 P45 ZnH Zn COBS 1, i where a, o and a are the logical coefficients of the 12th and 11th most significant bits of the angle code.

Таким образом, устройство в первом вычислении по координатам Р и r(t) вырабатывает координаты У(Ъ). иХ(1) в число-импульсных кодах, (в дальнейшем первое вычисление процесса формировани число-импульсных кодов координат У (t) и X (t) по координатах Ч и r(t) называют формированием цифровой развертки по углу .)Thus, the device in the first calculation of the coordinates P and r (t) produces the coordinates Y (b). iX (1) in the number-pulse codes, (hereinafter, the first calculation of the formation of the number-pulse coordinate codes Y (t) and X (t) using the coordinates H and r (t) is called forming a digital sweep angle.)

Таким образом, с выходов 44,29 и 45,40 сигналы цифровой развертки по углуЧ (т.е. сигналы ЗнУ и ЧИК /У и ЗнХ и ЧИК /X/), вл ющиес результатом первого вычислени , могут сниматьс потребителем. В процессе формировани развертки по углуЧ на выходах 43 умножител 7, вл ющихс разр дными выходами текущего кода общего сомножител , вырабатываетс п-разр дный код текущей координаты г (t) .Thus, from the outputs 44, 29 and 45, 40, the digital sweep signals by angle (i.e., the signals ZnU and CHICK / U and ZnH and CHICK / X /), which are the result of the first calculation, can be removed by the consumer. In the process of forming an angle sweep at the outputs 43 of the multiplier 7, which are the bit outputs of the current common multiplier code, the n-bit code of the current coordinate r (t) is generated.

Работа умножител 7 обычно npoi- раммируетс так, что после разрешени его работы по ИЗЦ 14 он вырабатывает на входе 21 импульс конца развертки (И21) по импульсу 2 из .последовательности ТИ 16, поступающей на тактовый вход умножител 7The operation of multiplier 7 is usually npoi-framed so that after allowing it to work on IZZ 14, it produces at input 21 a pulse of the sweep end (I21) by pulse 2 from the TI 16 sequence fed to the clock input of the multiplier 7

в течение длительности развертки Тр Т1.during the duration of the sweep Tr T1.

р предлагаемом устройстве умножитель 7 запрограммирован так, чтоp the proposed device multiplier 7 is programmed so that

Т1 2T1 2

(2)(2)

тиti

с Такимобразом, умножитель 7 по импульсу два последовательности ТИ 16, поступающей на тактовый вход ум- ножител 7 после окончани ИЗЦ 14, вырабатывает И 21, вл ющийс импуль« сом конца периода Т1 и импульсом начала периода Тф . И 21 поступает на блок 12 управлени и генератор 11 функций. Каждый И 21 на блок 12 управлени воздействует так, что в некоторый момент времени после окончани И 21 триггер 54 устанавливает ,с в и запрещает выполнение первого вычислени . По каждому И 21 происходит также запуск генератора 11 функций.Thus, the multiplier 7 impulses two sequences of TI 16 arriving at the clock input of the multiplier 7 after the termination of IZZ 14 produces And 21, which is the impulse of the end of the period T1 and the impulse of the beginning of the period Tf. And 21 enters the control unit 12 and the generator 11 functions. Each AND 21 on the control unit 12 acts in such a way that at some point in time after the end of AND 21, the flip-flop 54 sets, c to and prohibits the execution of the first calculation. For each AND 21, the generator also starts 11 functions.

0 Генератор 11 функций содержит входной коммутатор кодов двух аргументов (углов), цифровой синуснокосинусный преобразователь и два выходных регистра, разр дные входы0 The generator of 11 functions contains an input switch of two argument codes (angles), a digital sine-sinus transducer and two output registers, bit inputs

5 которых и выходы записи соединены с соответствующими выходами синуснокосинусного преобразовател , у которого тактовый вход и выход запуска соединены соответственно с тактовым5 of which and the recording outputs are connected to the corresponding outputs of a sine-sinus transducer, in which the clock input and the start output are connected respectively to the clock

Q входом 16 устройства и с выходом 21 умножител , и входы аргумента подключены к выходам коммутатора кодов, разр дные входы первого и второго аргументов коммутатора кодов соединены соответственно с входами 35 регистра 1 угла и группой входов 36, а управл ющий вход коммутатора кодов подключен к выходу 25 блока 12 управлени , при этом вьоход 14 с группой выходов 33 и выход 45 с группойThe Q input 16 of the device and with the output 21 of the multiplier and the argument inputs are connected to the code switch outputs, the bit inputs of the first and second code switch arguments are connected respectively to the inputs 35 of the angle register 1 and the input group 36, and the control input of the code switch is connected to the output 25 control unit 12, while vyhod 14 with a group of outputs 33 and output 45 with a group

0 выходов 34 генератора 11 функций вл ютс выходами соответственно его первого и второго регистров. Работа генератора 11 функций программируетс по сигналу П25 так,The 0 outputs 34 of the function generator 11 are the outputs of its first and second registers, respectively. The operation of the generator 11 functions is programmed by the signal P25 so that

5 что по каждому И 21 он в течение Тф производит выработку на выходах 44 и 45 соответственно Зн sins и Зн созЧ, а на группах выходов 33 и 34 - соответственно кодов функций и5 that for each I 21, during TF it produces output at outputs 44 and 45, respectively, Zn sins and Zn are combined, and on groups of exits 33 and 34, respectively, function codes and

0 /созФ/.0 / soF /.

После окончани Тф цикл работы устройства, заканчиваетс , а следующий цикл начинаетс с приходом на устройство очередного ИЗЦ 14. После скончани рассмотренного цикла работы в устройстве содержитс информаци подобна той, котора была в устройстве перед началом этого цикла.After the termination of Tf, the cycle of operation of the device ends, and the next cycle begins with the arrival of another IZZ 14 on the device. After the end of the considered operation cycle, the device contains information similar to that which was in the device before the beginning of this cycle.

При выполнении второго вычислени (рассматриваютс лишь те процессы,When performing the second calculation (only those processes are considered

0 которые характерны именно дл второго вычислени , так как все, что описано выше имеет место и при выполнении этого вычислени ) устройство по (п+1)-разр дным кодам нормированных0 which is characteristic of the second computation, since everything that is described above also takes place when performing this computation) the device according to (n + 1) -discharge codes of the normalized

Claims

5 rectangular coordinates :: inat U2 and X2 Oi / y2 / or / X2 /: 61-2) generate (n + 2) the discharge code of the coordinate Oi4 2 / 2it () and the n-discharge code for the dinat 0 g2 1 -2 Codes U2 and X2 are respectively located in registers 2 and 3, the most significant bits of which are signed. Therefore, the 12th bit of the code two coincides with the sign bit of the U2 code. And the 11th bit of the two code is generated at the output 17 of the adder 9 as a sum modulo two logical values of the sign of the new bits of registers 2 and 3. The remaining n bits The codes of code II represent the reduced angle code i. , p (1-2) -. P / 2 and determined in the first cycle of the second calculation cycle, in the second cycle of which the coordinate code r2 is determined, I The launch of the second calculation is carried out according to the VFR 15, synchronized with respect to AND 21 so that each VFR 15 enters the device in the period And 21. Each / WPI 15 enters the control unit 12 and sets the triggers 53 and 56 c. Trigger 53 removes the fixed installation signal in O from flip-flops 56 and 58, and flip-flop 56 triggers from flip-flop 55. In addition, for each IZV 15, the control unit 12 at the output 24 generates an impulse 24 and the output 28 impulses the impulse 28. According to AND 24, counter 4 records the code / U2 / a into counter 5, code / X2 /, and according to AND 23, the functional converter 8 is set to O. After the next Tf period is completed, the device is prepared for the next cycle of the first calculation and the first cycle of the cycle second computation. Each of the two cycles of the second calculation starts at IZC 14, and accordingly, before each cycle of the second calculation, the device contains the information required to perform the corresponding cycle. Consider the operation of the device in the first cycle of the second calculation, in which the determination of the n-digit code of the angle 2. Before the start of this clock cycle, counters 4 and 5 contain the codes / Y2 / I / X2 /, respectively, the first and second groups of inputs of the multiplier 6, respectively, from registers 3 and 2 receive the codes / X2 / and / U2 /, the functional converter 8 is in O, in control block 12, triggers 53 and 56 are in, and the remaining triggers are in O, a logical signal is removed from output 25 of control block 12, which disables the switch 13 pulses from signals from outputs 39 and 40 of multiplier 7 The calculation clock begins with the arrival at the control unit 12 of the next IZC 14, according to which The rumble flip-flops 54 and 55 are installed in and which through element 62 from the output of the control unit enters the correction input of the multiplier 6, and through elements 62.67 and 70 from the output 29 of the control unit 12 to the clock input of the function converter 8. At some point after the IZC 14 terminations to the outputs 27 and 29 of the control unit 12 pass through the sequence of TI 16. From the outputs 26 and 27 of the control unit 12, first, respectively, AND 26 according to IZ.Ts 14, and then the sequence of pulses PI 27, 27 according to TI 1b is received respectively at the correction input and input multiplies l 6. From the output 29 of the control unit 29 a series of pulses PI is supplied to the clock input of the functional converter 8 (in the UI 29, the first pulse generated by IZTS 14, and all the rest - 16 TI). The multiplier 6 is first in & 26 ,. and then, according to PI 27, it functions so that, according to AND 26, multiplier 6 is set to O and simultaneously generates 37 and 38 impulse inputs by impulse, and by PI 27 multiplier 6 at inputs 37 and 38 produces a CHICK c (t} - / X2 / n 4HKc (t); Y2 /, where c (t) is some argument represented by the CHIC, i.e., by TI 16. Consequently, in the first clock cycle at inputs 37 and 38, multiplier 6 is generated by PI 37 and PI 38. In PI 37, the first impulse is generated by IZZ 14, and all the others are CHECK c (t) / X2 /. In PI 38, the first impulse is produced by IZZ 14, and all others are Chick c (t) - / y2 From inputs 37 and 38 multiplier 6, respectively, PI 37 and PI 38 are fed to one of the inputs of the switch 13. Pulses 13 are therefore outputted at 41 and 42 switches, 13 PI 41 and PI 42 are output, respectively, such that PI 41 PI 37 and PI 38. In this case, PI 41 is fed to the subtracting input of counter 4, and PI 42 to the subtracting input of counter 5. According to PI 41 and PI 42, the contents of counters 4 and 5 begin to decrease. This process continues until at least one of the counters 4 and 5 overflows. When overflow, counter 4 at input 19 generates an overflow pulse and 19, and counter 5 at input 20 generates an overflow pulse 20. Moreover, overflow of one of these counters or simultaneous overflow of both counters means solving one or both equations of the system t ") / -tg 2 // Y2 /// X2 /; o (t) / ctgP2 / - / X2 /// Y2 / Thus, the system equations (3) are solved in the first cycle. The solution is the value of c (t) such that when / Y2 // X2 / is produced first by AND 19, meaning that from (t) with (t.) (With) the first is produced by And 20, meaning that with (t ) c (tx). When And 19 and And 20 are produced simultaneously. meaning, that c (t) c (fc) () c The value of c (t) is conveniently expressed as tgc of the argument c, which can vary from up to. From this it follows that the mathematical model of the device operation in the first cycle of the secondary calculation can be written down by the equations Ф 2 р o6-ПЗ. + (1i / 2-cf.) From - P 17- AND 19 + P 17 and 20, (5 where the logical value of the 11th bit is Kodaf 2, P 30 is some logical variable, such that if B is the first clock At output 30 of control unit 12, an impulse I 30 is generated, then P 30 1, and if P 30 is not produced, then P 30 # 0. During the first clock cycle, tgiit is an argument of the functional converter 8 and is fed to it from the output of block 29 12 controls in the form of a PIC tgo, t in the form of PI 29, each impulse which has a weight of 2, the functional converter of And 28, PI 29 and And 30 generates at the end of the first cycle k6dF2 r. This is It is as follows. In the functional converter 8, before the start of the first clock cycle over AND 28, counters 48, 50 and 51 and multiplier 47 are set to O. During the first clock output from 29 bl 12 of control, the CHIC tgot goes to the clock input of the multiplier 47, on the parallel input the multiplier of which from the outputs of the memory block 49 is supplied with a 6-bit code of the angular coefficient K ;, the weight of the lower bit 2-. glad. Using the tgot tick AND parallel code Kj, the multiplier 47 produces a CHIC which simultaneously arrives at the summing input of the counter 50 and the subtracting input of the counter 51. The overflow pulse of the multiplier 47 changes the contents of the counter 48 approximation sections and thereby changes the code K at the outputs of memory block 49 which is programmed to output the angular coefficients of the K-function of the X arctgoi on 16 approximation areas. Thus, during the first clock cycle, the functional converter 8, according to the argument t, forms in the counter 50 a function code (Y, and in counter 51 - a function code (% / 2-oi,); CHIC generation process tgct and, therefore, playback of functions X and (tfc / 2-o -) continues until at least one of the pulses AND 19 or AND 20 arriving at the control is generated. In the first clock, control block 12 according to AND 19. And AND 20 at output 30 generates AND 30 in accordance with the expression (5), as well as with the help of element 60 generates a pulse arriving at the counting input trigger 55. Therefore, at some point after the completion of AND 19 or 20, the first cycle of the second calculation ends, since the trigger 55 switches to O. As follows from (5), the ISO is generated only when P 2p, p / T. -M and enters through the entry delay entry element 52 of the counter 51, the bit inputs of which from the bit outputs of the counter 50 arrive at the codec. After the first clock cycle has ended, the outputs of the function converter 8 (i.e. of the bit outputs of the counter 51) the angle code 2p | p. in full accordance with expression (4),. By the interaction of the control unit 12 with other nodes of the device, it can be seen that when 2, p O, AND 26 is formed in the first clock of IZZ 14; via AND 26 through multiplier 6 and the switch 13 pulses, counters 4 and 5 form I19 and II accordingly, and the control unit 12 for AND 19 and 20 (priP 2pr, 0) necessarily generates ISO and repeated AND 28, which prohibits the output from zero the states of all the triggers of the functional converter 8, besides, the first clock cycle, due to the correction pulse (i.e., 26 in IZZ 14), ends before the multiplier 7 produces And 11, since T1 2. T. It follows that if operation of the device is required at T, then an additional sequence of pulses (i.e. the device must have a second clock input) whose frequency is higher than the frequency TI should be applied to the device, namely one of the inputs of the element 65 of the control unit 12. 16, so that the first clock cycle ends before the multiplier / generates AND 21. After the first clock cycle ends, the next AND 21 passes through element 63 to the counting input of the trigger 56 and to the output 24 of the control unit and rewrites the count 4 codes / Y2 /, and in the bill 5 IR code / X2 /. At some point after the end of the AND 24 flip-flop 56, the flip-flop 58 switches to 1 and removes the signal, the fixed setting in O from the flip-flop 5 enables the operation of element 61 by AND and 19, enables the operation of element 69 by AND 21 and issues the output 25 of the 12-control unit is a logical signal P 25 1. According to this signal, the operation of the switch of 13 pulses is resolved accordingly, and the generator of 11 functions in the period Tfr calculates the functions of the argument P Φ 2. After finishing the device is prepared for operation in the second cycle of the second calculation. In the second cycle of the second calculation, a determination is made of the n-time of the normal code of the normalized coordinate r2 (i.e.). Before the start of this clock cycle, the information necessary for the first calculation of the angle Ч2 is supplied to the multiplier, and counters 4 and 5 contain codes (Y2) and / X2 /, respectively, a code is taken from input group 36, in the control unit there are three heres 53 and 58 are in H, and the rest of the triggers are in O, and from the output 25 of the control unit 12 the logical signal P 25-1 is removed, which the switch is allowed to use 13 pulses from the outputs 39 and 40 of the multiplier 7. The calculation clock starts with on the control unit 12 of the next IZZ 14, for which the trigger 54 switch It is sent to Q, and through element 62, multiplier 6 and switch 13 pulses are simultaneously fed to the subtractive inputs of counters 4 and 5. Since P 25 1, then at some point after expiry of SPV 14, from inputs 39 and 40 of multiplier 7 through switch 13 pulses to the subtractive input of the counter 4 arrive CHIK / U /, and to the subtractive input of the counter 5 - CHICK / X /. Thus, in the second cycle in PI 41, the first pulse is produced according to IZZ 14, and all the others represent the CHICK / U / angle 2 and variable r (t); in PI 42, the first pulse is produced by IZZ 14, and all the others are CHICK / X / angles of F 2 and variable r (t). According to PI 4 and PI 42, the contents of counters 5 and 4 begin to decrease until the counter of that rectangular coordinate is overflowed, the contents of which before the start of the second cycle were greater than or equal to the contents of the counter of the other rectangular coordinate. This means solving one or both equations of the system: r (t, / Sin4 i / / V2 / p (t.) - / COSV) 2 / / X2 / Obviously, the solution is the value of r (t) r2 such that at: / Y2 / / X2 / g2 g (ty) / X2 / - / Y2 / g2 g (tx) / Y2 / / X2 / g2 g (ty) r (tx) .1 Thus, in the second cycle. finding based on the use of a known position — a smaller relative error corresponds to a larger value — when solving the equations of system (6). A logical signal about the ratio of the contents of the counter 4 and 5 is generated at the output 18 of the adder 10 as a modulo two of the 11th and 10th cF2 bits. Moreover, the signal П 18 вИ®В 10 means that with П18 1, and with И. The signal P 18 is fed to the corresponding inputs of the element 61 and controls its operation so that the output of the element 61 produces a pulse of AND 19, if P18 is 1 and 20, if P 18 0. From the output of the element 61, the pulse goes to the counting input of the trigger 57, which some time after the end of this pulse switches to i and enables element 69 to operate through the next TI 16, which passes through element 69 to the counting input of the trigger 53 and to the output 46 of the control unit 12 and is a pulse I. 46 removal from the device F 2 and d2 , since exactly at the moment of action AND 46 From the outputs 43 of the multiplier 7, the code r (t) r2 is removed. However, all this will happen during T1 only under the condition that Y + +, which in principle may not be fulfilled. - The operation of the device when Y) + X | programmed so that AND 46 is generated by AND 21, i.e. In this case, at the moment of operation AND 4b, the code r (t) r2 1-2 is removed from the outputs 43 of the multiplier 7. Thus, code 46 for code 46 is removed from input group 36, and code r2 from group 43 of multiplier 7 outputs. some time after the end of AND 46, the trigger 53 switches to O and directly or through other triggers sets ixirovanno to O triggers 558, thereby prohibiting the generation of lock 12 control signals of the second computation. At this, the second calculation cycle ends, and the next cycle begins with the arrival of the next VIB 15 on the device. Thus, the duration of each second computation cycle is T2 2- (2. Comparing the expression and speed of the known device, we get T2 2 ../ (n + 1) (8) The proposed device in comparison with the known one has better performance both due to partial overlap in the execution time of the first and second calculations, and due to the fact that in the second calculation the speed of calculations of this device several times. The proposed device allows the first calculation (sweep in angle Ц 1) and the second calculation (sweep in angle Φ 2) to be carried out with the same frequency one after the other. Applying the invention will increase the speed of information processing. containing an angle register, two adders, a sine-cosine converter, a first pulse-multiplier number, two registers, and two counters, the outputs of the first and second registers are connected to the bit. the respective inputs of the respective counters, the outputs of the sign bits of the first and second registers are connected to the corresponding inputs of the first adder, the output of which is connected to the first input of the second adder, the inputs of the first sine-cosine converter group, the inputs of the first and second groups of the first the number-pulse multiplier is connected respectively to the outputs of the sine and cosine sine-cosine transducer, and with the fact that, in order to increase speed, a control unit, a second number-impulse multiplier, a switch and a functional converter are entered, the inputs of the second sine-cosine converter group are connected to the outputs of the functional converter, the sign output of the first register and the output of the first adder, the second input of the second adder is connected to the output of the older the bit of the functional converter, the outputs of the first and second groups of the second number-pulse multiplier are connected respectively to the outputs of the first and second registers, the outputs of the second the pulse number multiplier is connected to the first group of pulse inputs of the switch, the second group of pulse inputs of which are connected to the coordinate outputs of the first number pulse multiplier, the switch outputs are connected respectively to the subtraction inputs of the first and second counters, the inputs of the control unit of the first fifth are connected respectively, with the outputs of the first and second adders, the first and second counters and the output of the end of the sweep of the first number-pulse multiplier, the outputs of the control unit from the first to sixth d connected respectively to the inputs of the installation and the first clock-pulse converter Cielo trigger counters, and a control switch sine-cosine converter, input correction and clock input of the second pulse-number multiplier,

2. The coordinate transducer according to claim 1, characterized in that the control unit connects six triggers, four elements 2I-OR, six elements AND and three elements OR, the first input of the control unit connected to the first and second inputs of the first element 2I-OR, the third and fourth inputs are connected to the third and fourth inputs of the control unit, and its output is connected to the first input of the first element, the second input of which is connected to the first output of the first trigger, the first input of the second element I. and the clock input of the second trigger, inv The pc output of which is connected to the input of the third trigger, the output of which is connected to the first input of the second element 2I-2ILI, the second input of which is connected to the first input of the third and fourth element AND and the clock input of the control unit, the third input of the second element 2I-OR is connected to the first and the second inputs of the third element 2IILI, the direct output of the second trigger and the fourth output of the control unit, the fourth input of the second element 2I-OR is connected to the first input of the fifth element AND, the clock input of the fourth trigger and the fifth input The control unit, the output of the second element 2I-OR is connected to the tenth output of the control unit and the clock input of the fifth trigger, the input of which is connected to the start input of the second calculation of the control unit, the first inputs of the first trigger, the first OR element and the first and second, fourth inputs element 2I-OR, the third input of which is connected to the output of the first element I. and the ninth output of the block, control, the fourth input of the fourth element 2I-OR is connected to the output of the sixth element AND, the second input of the second element AND and the fifth output Lok control, an output of the fourth OR-2I is connected to the seventh

control unit, the third output of which is connected to the output of the first element OR, the second input of which is connected to the output of the fourth element AND and the clock input of the first trigger, the second input of which is connected to the inverse output of the fifth trigger and the input of the second trigger 2I-OR are connected to the second input of the control unit, the fifth and sixth inputs of the third element 2IILI are connected respectively to the first and second inputs of the second element OR, the output KOTppord is connected, to the clock input the sixth About the trigger, the first input of which is connected to the start input of the first decision control unit, the input of the fourth trigger and the first input of the sixth element I, the second input of which is connected to the second input of the fifth element I and the forward output of the fifth trigger, the third input of the sixth trigger is connected to the inverse output of the first trigger, the output of the third element 2I-OR is connected to the clock input of the third trigger, the direct output of the fourth trigger is connected to the second input of the fourth element And, the output of which is connected to the second output of the control, the first input of which is connected to the inverse output of the fourth trigger, the output of the sixth trigger is connected to the second input of the third element And, the output of which is connected to the sixth output

the control unit and the first input of the third element OR, the second of which is connected to the output of the second element AND, the output of the third element OR is connected to the eighth output of the control unit,

3. Converter on PP. 1 and 2. characterized in that the functional converter contains three counters, a multiplier, a memory unit and a delay element, wherein the multiplier overflow output is through the first counter and the 11si unit is connected to the information inputs of the multiplier, the installation inputs of the counters and the multiplier are connected to the 5 function input, the second input of which is connected to the clock input of the multiplier, the number-pulse output of which is connected to the output of the summation of the second

0 and subtraction of the third counter, the bit outputs of the second counter are connected to the bit inputs of the third counter, the recording input of which is connected to the third function through the delay element.

5, the outputs of the third counter are the outputs of the function converter.

Sources of information taken into account in the examination

0

1. USSR author's certificate No. 4536EO, cl. G 06 F 7/38, 1976.

2. USSR author's certificate for application No. 2513089, class C. 06 F 7/38, 1977 (prototype).

five

Bn.U2.