SU1325507A1 - Device for solving systems of linear algebraic equations - Google Patents

Abstract

The invention relates to computing and can be used autonomously or in combination with a digital computer to solve systems of linear algebraic equations. The purpose of the invention is to increase the accuracy of the solution. The goal is achieved in that the device contains the device start input 1, the initial value matrix generation unit 2, the switching unit 3, the intermediate result generating unit 4, the intermediate result storage registers 5-7, the constant memory block 8, the arithmetic unit 9, block 10 control, input 11 of the matrix of coefficient values, input 12 of the vector of values of the right, part of the system of equations, output 13 of the result of the device. An increase in tofusti is provided for cases where the elements of the matrix of the equation have values of different order. 11 il. with S (L oo you ate SP

Description

one

ten

The invention relates to computing and can be used in solving-systems of linear algebraic equations, for example, in systems for automatic control of dynamic objects.

The purpose of the invention is to improve the accuracy of the solution.

FIG. 1 shows a block diagram of the device; Fig. 2 shows a block forming the initial values of the matrix; in fig. 3 - switching unit; FIG 4 is a block for generating intermediate results; FIGS. 5-15; control unit; Fig. 6 shows the formation unit being reduced; Fig. 7 is the site of formation of the first factors; FIG. 8 shows a node for forming the second factors; FIG. 9 shows a node forming a mode feature; in fig. 10 - arithmetic unit; in fig. 11 is a timing diagram of the operation of the control unit.

The device contains a device startup input 1, a block 2 forming the initial matrix values, a switching unit 3, a projection generation unit 4 comprising p / multiplexers 55. A first multiplier forming unit 37 contains n multiplexers 55 о A second multiplier forming unit 55 contains multiplex multipliers 55. Node 54 forming a sign of re-mode contains elements NOT 565 where P riog.jn, element AND-NOT 57. Arithmetic unit 9 contains multiplier 58 and adders 59,

The device is designed to solve a system of linear algebraic equations of the form

20

25

AH B,

where A is the matrix of coefficients of the php dimension, consisting of the elements a.j (, a.,., n);

B is a column vector of dimension n composed of elements of the right-hand sides b;

X is a resolution vector of dimension n, composed of elements x-,

This system with det А 7 О has for each right-hand side of the equations a uniquely defined solution

interim results, from first to

X (x,,,., JX ,,), To find this - the third version of the 5–7 inter-vector storage, the vector-solution, we use the inverse of exact results, the memory block 8 by the terminator A, In this case, the vector-stant , the arithmetic unit 9, the decision-B block is computed by a simple 10 controls, the input I1 of the matrix of values of coefficients C: 1 st linear algebraic equations, the input 12 of the vector of values of the right-hand side of the system of linear algebraic equations.

multiplication of matrices.

To find the inverse matrix A 35, the matrix inversion algorithm is implemented, according to which, in order to calculate the matrix, it is necessary to perform matrix calculations: A -, ,,, ...., where AE, and E is the identity matrix and

output 13 of the device, internal information buses 14-27, outputs 28-31 of the control unit.

Unit 2 is formed: and the initial values contain delay elements 32 and adders, Switching unit 3 contains a switch 34, a multiplexer 35, a decrement forming unit 36, a first multiplier forming unit 37, a second multiplier forming unit 38, an internal information bus 39. Intermediate result generating unit 4 contains two adders 40 and 41, two multipliers 42 and 43, divider 44, Control unit 10 contains a generator of 45 clock pulses, waiting for a multivib

The device is based on the example of the decision sisrator 46, the first to the third triggers of linear algebraic equations 47–49, the element I 50, the element NOT 51, the third order operates the following counter 52, the node 53 elements in a comparable way

feature, feature formation node 54 |

mode. Node 36 of formation is reduced. Let the source system be

ten

15

3255072

Sewables contains semi-multiplexers 55. Node 37 of forming the first multipliers contains n multiplexers 55. The node of forming the second multipliers contains the multiplexers 55. Node 54 forming the sign of regimen contains HE elements 565 where Р riog.jn, AND-AND 57 element. The arithmetic unit 9 contains a multiplier 58 and adders 59,

The device is designed to solve a system of linear algebraic equations of the form

AH B,

where A is the matrix of coefficients of the php dimension, consisting of the elements a.j (, a.,., n);

B is a column vector of dimension n composed of elements of the right-hand sides b;

X is a resolution vector of dimension n, composed of elements x-,

This system with det А 7 О has for each right-hand side of the equations a uniquely defined solution

X (x,,,., JX ,,), For the vector-solution, use the matrix A, In this, the solution –B calculates

multiplication of matrices.

X (x,,,., JX ,,), To find this - the solution vector will be used by the inverse matrix A, In this case, the solution vector -B is computed by

To find the inverse matrix A, the matrix inversion algorithm is implemented, according to which, in order to calculate the matrix, it is necessary to perform matrix calculations: A -, ,,, ...., where AE, and E is the identity matrix and

sh

.

1 t.

cf (i

i

 . ten.

m j m 3 j

(i, j, in l, n).

The device, using the example of solving a linearly algebraic system, of the third-order equation, works as follows

  x b

2x + x, 2 + 3xj 2b2 X, + Xj + X, 2b

3

those. AX B,

/ 1 2 where А I 2 1 3 1 is the coefficient of the coefficient 1 1 1 / system elements;

B (1 22) - column vector

these parts

Topics.

The source column vector enters through input 12 to the arithmetic unit 9, and the initial matrix in view of the sequence of its elements obtained by decomposition in rows: 121213111 enters the input of block Z, where the unit of the first constant from bus 16 is subtracted from block 8 of memory constants. The output of block 2 formed a sequence of numbers

0212031 10,

The sequence of numbers from the output of the switch 34 is fed to the input of block 37, the output of which at the first step is formed by the following sequence of numbers

thirty

which bus 18 arrives at the information inputs of block 3, in particular at the inputs of the switch 34.

The operation of the device is synchronized by the control unit 10 and begins by applying a signal to the input 1 of the device. When this is set, the counter 52 is set to zero, the RS-flip-flop 49 is set to zero, and the RS-flip-flop 47 is turned into one state. The RS-flip-flop 48 is switched to the single state at the moment when a clock pulse appears at its counting input from the generator. 45 clock 40 to the input of the adder 40, where the folding pulses. As a result, from the output RS- with the unit coming through the bus, trigger 48, the unit enters one 14 second constants of block 8, transforming from the input elements of the 50, providing a return value, and multiplying

12.

In addition, the sequence of numbers on the bus 39 also enters the input of block 38, the output of which in the first step of the calculation appears the sequence of numbers

021.

On the bus 22 from the output of the multiplexer 35, the number O comes in the first step

passing the sync pulses arriving at its second input from the standby multivibrator 46. From the output of the element I 50, the sync pulses go to the counting input of counter 52. The period of the clock pulses is selected from the condition of complete completion of one calculation step.

In the first step, the calculation from the output of the counter 52 enters the binary code 1 to the control bus 19 and to the input of the block 54, in accordance with the law of operation of which O is formed at the first step of the O. At all subsequent steps, there is 1. At the exit 28 switch 34 is transferred

13255074

the sequence of numbers from the bus 18 at the signal at pin 28, the step O (first computation step), or the sequence of numbers from the bus 17 at the signal at pin 28 equal to 1, i.e. The first step at the output of the switch 34 is a sequence of numbers.

021203110,

which via the bus 39 is fed to the inputs of the multiplexer 35 and blocks 36 - 38.

A bus is connected to the output of the block 35, the diagonal element number of which coincides with the number of the calculation step transmitted via the control bus 19 from the control block 10. At the first step, the number 0 is transferred to the bus 22. The sequence of numbers over the bus 39 is fed to the input of the block 36, the output of which is formed on the first -step sequence of numbers

1002031 10.

The sequence of numbers from the output of the switch 34 is fed to the input of block 37, the output of which in the first step is the following sequence of numbers

to the input of the adder 40, where it is added to the unit coming through the bus 14 of the second constant of block 8, is converted into the reciprocal, and multiplying

12.

In addition, the sequence of numbers on the bus 39 also enters the input of block 38, the output of which in the first step of the calculation appears the sequence of numbers

021.

On the bus 22 from the output of the multiplexer 35, the number O comes in the first step

on 1, coming through the bus 16 of the first constant. As a result, the first step from the output of block 44 is the number -1. I

From the outputs of block 37 and block 38, the sequence of numbers goes through the buses 24 and 25 to the inputs of block 2, where their mutual multiplication takes place, as a result of which a sequence of numbers is formed at the output of the first step

021042021,

which from the output of block 42 enters the input of block 3, in which all numbers of the sequence are multiplied by

51325507

The number coming from the output of block 44,

in this ti s k x n t v s z g n high

as a result of this, in the first step from the output of block 43, a sequence of numbers is given

0-2-10-4-20-2-1,

which is added in accordance with the numbers with the sequence of numbers coming through the bus 23 in the superstore41, the output of which in the first step is the sequence of numbers

1-2-12-411-1-}.

This sequence of numbers from the bus 26 is fed to the inputs of the register 5 for storing intermediate results, which serves to store the separation of the computation steps and the elimination of the effect of races. During the computation at any step, the register 5 on pin 29 receives the control signal O from the input of the control unit element I 50, allowing the recording of information in this register,

021203110

021203110

100203110

t 2 I

About 2 t

- one

021042021

021203110 1-2 12-4 1-1-1

Ь2-10Ш1-1- 2 t - 1

2-41 1 3

-48-22-41-24 while the input 30 to the register 6 receives the control signal 1, allowing reading of information from this register. The clock cycle from the output of the standby multivibrator 46 is chosen in such a way that during the existence of a low voltage drop at its output, the calculations at this step are completely completed and the result is written to the register 5. register 5 enters 1, and the second - O, i.e. information is overwritten from the first register to the second. When the next sync pulse appears, the resolution to read the result from register 6 and write the result of the next calculation step to register 5 is given. The number of calculation steps is equal to the order of the inverted matrix.

The results of the calculations at the outputs of the individual blocks for each step are shown in the table.

021203110

5 5 20 I 1 411 4

5 5 20 I 1 4 ,. 3 3 C 3 3 s

-2-15Ш-П1-3 -2-1510-111-3 -2-11510-111-3

At each computation step, in node 53, the computation step number is compared, coming from the output of counter 52 and the number H (in the general case n + 1, where n is the matrix order), coming through bus 20 of the fourth constant from memory block 8,

As a result of the completion of the last third step of the calculation, a sequence of numbers is written in register 6

- 2 - 1 5 1 O - 1 1 1 - 3,

representing the elements of the inverted matrix A. At the time of the occurrence of the next fourth sync pulse at the output of the element 50, a read input signal arrives at the control input of the register 6. The number of the fourth clock pulse also enters the input of the node 53, as a result of which a control pulse is generated at the output, which translates trigger 49 into one state, and also triggers 47 and 48, which corresponds to the locking of control unit 10, to zero state.

The read signal 1 from the output of the RS flip-flop 49 through the first 31 is sent to the control input of the register 7, the information from the register 6 is overwritten to the register 7,

The information from register 7 goes through bus 27 to the inputs of multipliers 58 of the arithmetic unit, to the other inputs of which the vector of the right side of the equation arrives from input 12 from the outputs of the multipliers to the inputs of the corresponding adders 59, the output of which is represented by the desired vector the solution that arrives at the output 13 of the device result.

Claims (1)

Invention Formula A device for solving systems of linear algebraic equations containing an arithmetic unit and a control unit, characterized in that, in order to improve the accuracy of the solution, a unit for generating initial values of the matrix, a switching unit, a block of memory constants, a unit for generating intermediate results are introduced into it. The first, second and third registers of intermediate results storage, n inputs, where n five 0 five 0 five 0 five 0 five the order of the system of equations, the vector of values of the right-hand side of the system of equations of the device are connected to the information inputs of the first group of the arithmetic unit, the nJ inputs of the matrix of coefficients of the equations of the system of equations of the device are connected to the same inputs of the first group of the initial value matrix generation unit control and to the readout input of the memory block of constants, the i-and the output (,, .., п) of the first group of the memory block of constants is connected to the i-th input of the value of the mode of the control block In addition, the output of the second group of the memory block of constants is connected to the i-th input of the second group of the formation unit of the initial values of the matrix and to the 1st input of the first group of the intermediate result-generation unit, the 1st output of the third group of the memory block of the constants the information input of the first group of the switching unit and to the i-th input of the second group of the intermediate value generating unit, the i-th output of the fourth group of the constant memory block is connected to the i-th information input of the second group of the switching unit, first, second and third outputs control unit dyes are connected to the read inputs of the first, second and third intermediate result storage registers, the fourth output of the control unit is connected to the control input of the switching unit, the i-th output of the group of the control unit is connected to the i-th information input of the third group of the switching unit, j th exit where ,,,., n, of the formation unit. the initial values of the matrix are connected to the j-th information input of the fourth group of the switching unit, the j-th output of the intermediate results generating unit is connected to the information input of the j-ro bit of the first register of intermediate results, the j-ro bit of the first register of intermediate results is connected to the j-th information input) of the second storage register of intermediate results, the output of the j-ro discharge of the second storage register of intermediate results is connected to the j-th information the input of the fifth group of the switching unit and the information input j-ro bit of the third register of intermediate results, the output of the j-ro bit of the third register of intermediate results is connected to the information input of the second group of the arithmetic unit, the j-th output of the groups from the first to the fourth outputs of the switching unit is connected to the j-th input respectively of the groups with the third on the sixth inputs of the intermediate result formation unit; The outputs of the arithmetic unit are connected to the output outputs of the device, while the initial value matrix formation unit contains n totalizers and the delay elements of the first information input of the i-ro adder are connected to t (i-) inputs of the first group of the initial value matrix generation unit; the second information input of the i-ro adder is connected to the i-th input of the second group of the initial formation unit. from (kn + +) - th to (k + l) nth, where, l ,,,. ,,., p, delays are connected respectively to the inputs from (kn + k + 2) -ro to t (k + l) of the first group of the block forming the initial values of the matrix, the output i-ro of the adder is connected to the (i-1) output of the block forming the initial values of the matrix, and the outputs from (kn + k + 2) -ro to (k + l) n + 32550710 the second group of the node forming the first factors and the i-th input of the rjep group of the node forming the second factors, je the information inputs of the fourth and fifth groups of the switching unit are connected to the j-th information inputs of the first and second groups of the mutation unit switch, j the switch output of the switching unit is connected to the j-th information input of the multiplexer, switching unit, to the j-th input of the fourth group of the formation node diminished, 15 to the input of the third group of the node forming the first factors, to the j-th input of the second group of the node forming the second factors 5, the multiplexer outputs of the switching unit are connected to the outputs of the first group of the switching unit, the outputs of the generating unit of the reduced ones are connected to the outputs of the second group of the switching unit, outputs first factor formation node 25 are connected to the outputs of the third group of the switching unit, the outputs of the node forming the second factors are connected to the outputs of the fourth group of the switching unit, while the node for reducing 30 contains multiplexers n, the i-th input of the first group of the forming module is connected to the first information input t ( il) m} node shplexor  the formation unit of the initial 35 Formation decreasing, the i-th input of the matrix values are connected to the outputs of the second group of the formation node diminishable connected to the first information input of multiplexers Delay elements, respectively, from (kn + l) -ro to (k + l) are nth, and the switching unit contains a comm 1hator, a multiplexer, a forming unit, a forming unit of the first factors, a node forming the second: factors, controlling the input switch unit is connected to the control (iI) to (il) n + i-ll-40 and e C (il) n + is-1 -th in-th formation node being reduced, j-th input to the third the group of inputs of the node being reduced is connected to the control input of the j-ro multiplexer of the node to the input of the switch, the i-th information, the j-th input, the first group of the block of the fourth group of the node to tation. connected to the i-th input of the first group of the formation node to be reduced and to the i-My input of the first group of the formation node of the first co-generator, the i-th information input of the second group of the switching unit is connected to the i-th input of the second group of the formation node to be reduced, i-th information the input of the third group of the switching unit is connected to the i-th control) of the multiplexer input terminal of the co1-1mutation unit, to the 1st input of the third group of the forming node of the reduced, to the i-th input IN connected to the second information input of the j-ro multiplexer of the formation node diminished, the output of the j-ro multiplexer of the reducing node is connected to the j-th output of the forming node diminished, while forming the first factors of multiplex n multiplexer gg ditch, i-th input first node groups the formation of the first factors is connected to the first information input of the i-ro multiplexer of the node forming the first factors, the i-th input from (iI) to (il) p + i-llth and e C (il) n + is-1th to in-th formation node to be decremented, jth input of the third group of inputs to the decremented formation box is connected to the control j-ro input multiplexer node to ABOUT connected to the second information input of the j-ro multiplexer of the formation node diminished, the output of the j-ro multiplexer of the reducing node is connected to the j-th output of the forming node diminished, while forming the first multipliers of the multiplexers n the i-th input first node groups the formation of the first factors is connected to the first information input of the i-ro multiplexer of the node forming the first factors, the i-th input II1325507 2 the second group of the node forming the first results, the outputs of the second output multipliers is connected to the control - adder of the Prome formation unit. To the input of the i-ro multiplexer of the uzstanovnyh results are connected to the formation of the first factors, the 2nd named outputs of the forming unit information input i-ro multiplex-intermediate results, while crap, where,.,., n + l, of the node; the formuli-control unit contains a generator the vanities of the first factors of subdactactic pulses, three triggers, to the (i-l) input of the third group-waiting multivibrator, the node forming the first node of the formation of the first symptom of the Qvana mode feature, the node of elements , the i-ro output of the multiplexer of the comparison node, the counter, the AND element, the elution of the first factors, the NOT sub, the start input of the control unit is connected to the i-th output of the form node is connected to the installation input in 1 nor the first factors, with this first trigger of the control unit, to the node for the formation of the second multiplier, the input of the second trigger in O, contains n multiplexers, the i-th control unit block and the input for the input of the first group of the shaping unit in the counter of the control unit, the second factors are connected to the up-i-th input of the control unit mode by the modulating input of the i-ro multiplexer connected to the i-th input of the first group the node for the formation of the second multiply-Q Node of the elements of comparison of the control unit, the i-th information input of the gth, laziness, qth output, where ,,. ,, ,, where, ... n, the multiplexer of the node log. p, control unit counter the formation of the second factors is sub-connected to the qth input of the second group It is connected to (i-l) the input of the second node of the comparison elements, to the q-th input group of the node forming the second one of the 25 DN of the forming node; multipliers, the output of the i-ro multiplex-control unit and the q-th output of the group of the node forming the second component of the control unit, the output of the first teli is connected to the i-th output of the uzlatrigger of the control unit connected to forming second factors, setting up the third triggers block; forming intermediate DZ of the control block; output of the results contains two adders; pafopa clock pulses of the control multiplier; divider; the inputs of the twirl are connected to the input of the waiting multi group, the inputs of the second group, tweeter and control unit of the third group, inputs to the fourth input of the third trigger of the group unit, inputs of the fifth group and inputs., controls, output of the node of the elements of the sixth group of the formation unit pro-compared and the control unit is connected to inter-intermediate results connected to the installation input to the first trigger with the same information input of the control unit co-generator, to the input of the first divider group, the second trigger of the first group of the first accumulator, the second control and the input of the first adder, the first third trigger of the control unit, the group of the second adder, the first group output of the waiting multivibrator of the first multiplier unit and the second control group are connected to the first input p The first multiplier of the form-element block and the control unit, the output of intermediate results, the output of the third trigger of the control unit of the first czgmmator are connected to one-connected to the second input of the element And the same output information of the second control unit, the output of the divider group, outputs The control unit is connected to the counting unit connected to the information input of the counter of the control unit with the same name, the inputs of the first group of the second smart input to the input of the element NOT of the control unit, the knob of the forming unit the inter-output element of the HE unit does not control the exact results, the outputs are first connected to the first output of the block multiplier of the interval shaping unit, the output of the element AND of the initial results block are connected to the same direction and connected to the second output by the named information inputs of the second control unit, the output the second trigroup of the second multiplier, the outputs of the co-ger of the control unit are connected to which are connected to the same informational third output of the control unit, the output inputs of the second group are the second stroke of the formation unit PE feature of adder promo benching control unit is connected to the forming unit 13 the fourth output of the control unit, wherein the mode characteristic forming node contains NO elements, the AND-NOT element, the first input of the mode characteristic forming node is connected to the first input of the AND-NOT element of the mode characteristic forming node, the 8th input, where ,,. , tlogj p J, the node forming the sign of the mode of connection 1325507 -14 is connected to the input (sl) -ro of the HF element of the mode attribute forming node, the output (8-1) of the NOT element of the formation of the mode attribute sign is connected to the 8th input of the AND-NOT element of the formation of the mode attribute, and the output of -NOT the formation unit of the Sign of the mode is connected to the output of the node 10 of the formation of the mode prize. FIG. 2 Fi.3 1 16 34 in 25 And t g Hj, 39 fi e 391 7 3 Z5 Figz 2 gF31 55 56 9 55 57 and Fie.9 9U2.11 Compiled by V. Smirnov Editor N. Bobkova Tehred I.Popovich Proofreader T, Kolb    I "Illl AI I ( Order 3112/46 Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 1325507 27 fPuz. ten