SU840893A1 - Device for computing exponential functions - Google Patents

Description

The invention relates to computing. It is known a device for calculating, NIN of exponential functions, containing two counters, a group of elements AND, an element OR 1. However, the known device has limited functionality. The closest in technical terms to the present invention is a device for calculating exponential functions containing two dividers; frequencies, each of which contains a counter, a comparison unit, control counter-register, and the counting inputs of the frequency divider are input the pulse sequence of the device, the frequency output of each divider is connected to the input of the control counter-register of the other divider, with one of the control register counters working on addition and the second on subtracting 2} In the subtracting counter of the first binary frequency divider, the code of the number a (o) a is located in the summing counter of the second binary frequency divider (CO code of the number b (o) bfl. The same frequency, fw, is fed to the inputs of the binary frequency dividers. The frequency f ,, at the output of the first binary frequency divider is determined by the expression) yyyy and the frequency at the output of the second binary frequency divider is determined by the expression bllV where a (t) and b (t) are numbers corresponding to the code in the control of the first and second binary counters dividers are appropriate nno. Since the frequency f, (t) is fed to the summing input of the control counter, sec. the binary frequency divider and the frequency f (t) to the subtracting input of the control counter of the first binary frequency divider, then the known circuit is described by the following control system JQ (t) f o) (a L at f a) a (o) ao, b ( o) bft. Having transformed (3), ... we get Γ,,. aci (t) U (t). C, .-., By adding the equations in system (4), we get, "w.bw.ii" -, С5) a (ciib) whence it follows that either d (t)) C, on3t. (6} Determining from BW) b (t) and substituting in (4), we obtain c3a (i) aobo Щ SEShiva (7) by the separation method belt, we get about Doing the same way -with the second equation of system (4), we get i- Thus, when uplenii device clock frequency input for time t t, i.e. upon the arrival of Ny pulses of the frequency f I Nv in the control counter of binary frequency dividers, number codes () Ur "oE 4-V o are formed, in accordance with (8) and (9J) However, the known device RB gives excessive complexity and inadequate accuracy due to the maximum rounding error due to the use of a binary divider with a constant system time equal to, as follows from (8) and (9), ... (,,) The purpose of the invention is to simplify the device and increase its accuracy The goal is achieved by the fact that a device containing summing and subtracting counters ne In this case, pB3 Jo and the second group of elements control inputs of the first element I are connected, respectively, with the outputs of the first group of the receiving counter, and the inputs of the second group of elements I are connected to the outputs of the first group of the summing element; The IL, with the first inputs of the operation units, are connected to the input of the impulse sequence of the device, the second inputs of the first and second operating units are connected to the outputs of the first and second OR elements, respectively, the output of the first opera ion block is connected to counting input of the summing counter and the second output - to the counting input of the subtracter counter totaliser second group of outputs is connected to. information inputs of the first group of elements And, the second group of outputs of the detracting counter with information inputs of the second group of elements AND, the outputs of the first and second groups of elements AND are connected respectively to the inputs of the first and second elements OR. FIG. 1 schematically shows the proposed device; in fig. 2 operational unit, Device contains summing counter -1, subtractive counter 2, groups of elements AND 3 and 4, elements OR 5 and B, operational blocks 7 and 8. Each operational block contains trigger 9, element AND 10, element OR 11, element delays 12. At the same time, the first input of the OR element is the first input of the operational block, the second input of the OR element is connected to the output of the delay element, and the output of the OR element is connected to the first inputs of the AND element and the trigger and is the output of the operational block, the second trigger input the second entrance of the operas unit, the trigger output is connected to the second input element And the output of which is connected to the output of the delay element. The device works as follows. In the initial state in subtractive counter 2 there is the code of the number A / tx O and in the summing counter 1 there is the code of the number 3 / t o / b. The first inputs of the operating units 7 and 8 receive the clock frequency fp. From the output of block 7, the frequency fj is fed to the input of summing counter 1. Counter 1 with group 3 of coincidence circuits is a binary frequency multiplier controlled by the code of the number A (t) of the subtracting counter 2, therefore the frequency f at the output of the element OR 5 is determined by the expression fs-AW where N. „2 is the conversion factor for counters 1 and 2; n is the number of binary bits of counters 1 and 2; A (t) is the code of the number of the subtractive counter 2. Subtractive counter 2 with a group of 4 coincidence circuits is a binary frequency multiplier controlled by a code of the number B (t) of the summing counter 1, Therefore the frequency | at the output of the element, OR 6 defines with the expression π / 4. -tt, Dtt) where f, is the frequency at the output of block 8. Since the frequency fg arrives at the second input of block 7, in accordance with FIG. 2,. The frequency f at its output is determined by the expression or, taking into account (12),

. i, C15)

N

m

(From

(sixteen)

Similarly, since the frequency f is fed to the second input of block 8, then, in accordance with FIG. 2, the frequency f, at its output, is determined by the expression

 (

or, subject to (13),

ib-bC-t)

- ± ь

fn

IV

from where

o-Nm

(-(9)

f

 ftCtl

Since the frequency f is fed to the input of the detracting counter 2, and the frequency fj is to the input of the total of counter 1, the numbers A (t) and B (t) corresponding to the codes of the subtractive counter 2 and the summing counter 1 / are respectively t

A (t) N

(20)

dt

 fc B (t) f

(1-0

dt

where t is the current time.

To determine A (t) and B (t), it is necessary to solve equations (20) and (21), by differentiating (20) and (21), we obtain the following system of equations d La)

-V

a-fc

Saa) d SCfc)

 "five

dt

in (22) I poi (19)

Substituting (16) we get

o-hni

. B (-t)

{1r1

o-Nm

l {)

or

| 6W.Ai -foN «

(A4)

8408 5 10

or

aA (t)

  , SchG

Integrating (27). we receive. ChPL., (av)

where C is constant, integration. When t Oh, A (t) a-, therefore C zd and

enA (t) -% 4p -bendo,

from where

thirty

. loNm

 Att) aoe (ae)

Having solved the same method, the second 35 equation of the system (24) of equations, we get

-M "t.

8 (t) b ,, e

(thirty)

Thus, during the time t t, when the pulses of the frequency fp Ny (fl., According to (29) and (30) arrive at the input of the device Ny, in the subtractive counter 2 and summing counter 1 are formed, respectively, the codes of numbers

A A (t) J. adE

aotoo

.

(31).

and B

As follows from (29) and. (30), the time constant t of the system in the proposed device for calculating the exponential functions is

.,) o

Comparing expressions (11): and (12) Let us suppose that in the proposed device for calculating exponential functions the time constant t of the system is reduced, which allows increasing

Claims (2)

the accuracy of the outlining of functions (31) for 36 Add up the equations in system (24), we get M «., SU, -, from which it follows that d (A-, 6) g aG or A (t) B (t) Const ao bp where a, A (t) J b B (t) Having determined B (t) from (25) and substituting the system of equations (24) into the first equation, we get the decrease in the discretization error. In a known device, the content of the summing counter is changed by the unit after the number of pulses arriving at the device input is equal to the additional code of the number of pulses. N .. - A (t) reading counter. pulses, and the content of the counting counter is changed by one after the number of pulses arriving at the device input is equal to the additional code of the number of summing counter, i.e. - B (t) pulses. If these conditions are not met, the contents of the summing and subtracting counters do not change, i.e. the result of the calculation of the functions does not change, which characterizes the presence of a large rounding error in the calculation of the result. In the proposed device, each input pulse changes the contents of both the summing and subtracting counters, which significantly reduces the rounding error. Thus, in the proposed device, an increase in the calculation accuracy of the exponential functions is achieved. Consequently, the inclusion of a device for calculating the exponential functions of the two frequency addition schemes and changing the σ-coupling allows the device to be significantly simplified (the number of counters has decreased from four to two), and also to improve its accuracy (reduced rounding off). Apparatus of the Invention for calculating the expo nential functions containing summing and subtracting counters, the first and second groups of elements AND, and the control inputs of the elements AND of the first group are connected respectively to the outputs of the first group of the subtracting counter. with the outputs of the first group of the summing counter, characterized in that, in order to simplify the device, it contains two frequency adders and two III elements, the first inputs of the adders ca The frequencies are connected to the input of the pulse sequence of the device, the second inputs of the first and second frequency adders are connected to the outputs of the first and second OR elements, respectively, the output of the first, the frequency adder, is connected to the counting input of a summing counter, and the output of the second is counting input b1 the shtayushchy counter, the second group of outputs of the summing counter is connected to information inputs of elements I of the first group, the second group of Outputs of the subtractive counter - with-information inputs an element And the second group, the outputs of the elements And the first and second groups are connected respectively to the inputs of the first and second elements OR. . Sources of information taken into account during the examination 1. USSR Author's Certificate No. 369565, cl. G About F 7/38, 1970. 2. Dancheev V.P. Digital-frequency computing devices. M., Energie, 1976, p. 58, fig. 2-19 (prototype),. ./but J 1 11 Jb W you