SU839028A1 - Pulse generator - Google Patents

Description

(54) PULSE GENERATOR

one

The invention relates to a pulse technique and can be used in pulse generators with varying pulse durations and a period of their following.

A pulse generator is known that contains a trigger, a control circuit, a resistor, and thermo-dependent elements p. .

However, this generator has insufficient stability due to the fact that the elements included in it have a temperature variation, which also changes with the aging of the elements. .

The closest in technical essence and the achieved result to the proposed is a pulse generator containing a counter, two coincidence elements and a trigger, the direct output of which is connected to the input of the first coincidence element connected by other inputs to the corresponding low-order counter outputs with R-inputs are connected between one another and the corresponding outputs of the higher bits of the counter are connected to the inputs of the second match element, while the R inputs of the higher bits of the counter are connected

between themselves, and the counter input is connected to the bus clock pulses 2.

However, this device containing only digital elements has insufficient stability of the oscillation period, since the coincidence element connected to the outputs of the lower-order counter does not have their initial installation. After at least one of the triggers of the low-level bits has been installed, one of the units is removed from the output of this trigger at the input of the match element and the match element stops performing the initial installation of the triggers, the least fast of the triggers can remain in a single element; which leads to a decrease in the pulse repetition period of the generator. The shortening of the period of the generator pulses can also occur because if the RS trigger speed is high, it can be thrown and prohibit the initial installation of lower-order triggers to the zero state via the coincidence element. The aim of the invention is to increase the stability of the oscillation period. This goal is achieved by the fact that a pulse generator containing a counter, two coincidence elements and a trigger, whose direct output is connected to the input of the first element from a fall connected by other inputs to the corresponding outputs counter outputs, in which the R inputs are interconnected, and the corresponding outputs of the higher bits of the counter are connected to the inputs of the second coincidence element, while the R inputs of the higher bits of the counter are connected between fight and counter input connected to the bus clock pulses additionally introduced OR element whose output zyuchen Connectivity to the J and C. To the trigger inputs, the R-in of which is connected to the control signal bus, and the inverse output is connected to the auxiliary input. the second match element, the second auxiliary input of which is connected to the clock pulse bus and the auxiliary input of the first match element, the output of which is connected to the R inputs of the higher bits of the counter and to the input of the OR element, the second input of which is connected, to the R inputs of the lower bits of the counter and with the output of the second match item. . FIG. 1 is a functional diagram of the pulse generator in FIG. 2 - time diagram of his work. The pulse generator contains counter 1, trigger 2, elements 3 and 4 from the fall of NAND, element 5. Clock pulses go to bus 6, control signal to bus 7i The output signal is taken from bus 8. The generator works as follows. In the initial state, a zero signal appears on bus 7, which sets trigger 2 to zero, output 9 of trigger 2 produces a zero signal, and in its inverse output 10 it is single. A zero signal at output 9 prohibits the operation of elements. 3 matches and its output 11 is a single signal, and a single signal at output 10 permits the operation of element 4 matches. Until at least at one of the inputs of element 4 there is a zero signal, at its output 12 there is a single signal arriving at the R inputs of the least discharges of counter 1 and deciding their switching. A single signal at output 11 of matching element 3 permits the switching of the high bits of counter 1. At the moment when single signals appear at the corresponding high bits of counter 1, element 4 drops to the zero output signal, which is issued after arrival. the next clock pulse. The zero-signal HQ of the bypass 12 of the element 4 coincidence is set to zero by the R-BXO of the lower bits of the counter 1. At the output 13 of the element OR 5, a single signal appears that cannot switch the trigger 2, since its switching is prohibited by zero control signal on the bus 7. The generator is prepared for operation. After a single signal arrives at bus 7, the next single signal at output 13 of the element OR 5 triggers, trigger 2 in the counting mode switches to the single state and returns the zero signal to the coincidence element 4, and the single signal to the CO dips element 3. A single signal appears on the output bus 8. After the corresponding outputs of the lower bits of the counter 1 are in single-unit signals, the coincidence element 3 is prepared to issue a zero signal, which is output after the arrival of the next current pulse. Zero signal. The output 11 of the element 3 coincidence sets the bits CTapmiie of the counter 1 to the zero state, and through the element. OR 5 switches trigger 2 (in counting mode). To zero. A single signal on the output bus 8 is terminated. Its duration depends on the number of low-order bits of the counter 1 and the connection of the corresponding outputs (direct or inverse) of the lower-order triggers of the counter 1 to the inputs of the coincidence element 3. After the output pulse has been formed and the trigger 2 has returned to the initial zero state, from the inverse output 10 of the trigger 2 a single signal is fed to the input of the coincidence element 4, allowing its operation. After a predetermined number of clock pulses arrives at counter 1 and at the corresponding outputs of the high-order triggers of counter 1. single signals appear, a zero signal appears at the output 12 of coincidence element 4. Upon the decay of this signal, trigger 2 switches to the one state, and again a single signal begins to form at the generator output. The proposed generator, due to the introduction of links of elements 3 and 4 of the coincidence with the clock bus, unlike the known one, has a standard, equal to the duration of the clock pulses, the time when the low and high bits of the counter are reset. Connecting the output trigger to the control signal bus allows the output trigger to be reset to its original zero state, and the duration of the first and subsequent output pulses to be the same. In the known device, due to an arbitrary initial setup of the trigger, the first output pulse can be shortened. In the proposed generator, in addition, the connection of the output of the coincidence element controlled by the low-order bits to the inputs of the initial installation of the high-order bits and the output of the coincidence element controlled by the high-level bits to the inputs of the initial installation of the lower-order bits allows initial installation of each parts of the counter immediately before the start of the reference in this part of the counter, which increases the reliability of its work and reduces the possibility of its failures. Introducing the OR element with its corresponding connections and connecting the inverse output of the trigger to the input of the coincidence element allows the initial installation of the corresponding part of the counter after its next switching over the clock pulse and makes it independent of the speed of the applied elements, i.e. achieve reliable operation of the pulse generator as a whole.

When using a specific pulse generator, it should be noted that the duration of the output pulse is determined by the number of bits and the corresponding connection of the outputs of the lower bits of the counter to element 3 coincidence, and the time from the fall to the front of the output pulse is determined by the number of bits of the counter counter bits to match element 4. It follows from the above that the duration and period of the output pulses are equal to the determined numbers multiplied by the period of the clock pulses and can be highly stable when used as a generator of clock pulses of a quartz oscillator.

Due to the high stability, reliability and relative simplicity, the proposed pulse generator can be widely used in the pulsed technique.

Claims (1)

Invention Formula Pulse Generator 0 counter, two matching elements and a trigger whose direct output is connected to the input of the first match element connected by other inputs to the corresponding outputs 5 least significant bits of the counter, in which the R-inputs are interconnected, and the corresponding outputs of the higher-order bits of the counter are connected to the inputs of the second coincidence element, with This R-inputs of the higher bits of the counter are connected to me) (by myself, and the counter input is connected to the clock pulse bus, characterized in that, in order to increase the stability of the oscillation period, 5 an additional OR element is inputted, the output of which is connected to the J-, C to the Trigger inputs, R is the input of which is connected to the control signal bus, and the inverse output is connected to the additional input of the second coincidence element, the second additional input of which is connected with clock bus and an additional input of the first element 5 matches, the output of which is connected to the R-inputs of the high-order bits of the counter and to the input of the OR element, the second input of which is connected to the R-inputs of the lower-order bits of the counter and to the output 0 of the second match element. Sources of information taken into account in the examination . 1. USSR author's certificate 668066, cl. H 03 K 3/02, 12.04.73. 2, Japanese Application No. 52-26984, 5 cl. H 03 K 23/26, 1977. n p "five I I n n p n I I