SU834937A1 - Frequency multiplier - Google Patents

Description

one

The invention relates to a pulse technique.

A pulse frequency multiplier is known, comprising a reference oscillator, a voltage controlled oscillator, a frequency multiplier, a production detector, a frequency discriminator, a low-pass filter l.

The disadvantage of this generator is its complexity.

The closest in technical essence to the present invention is a frequency multiplier containing a -channel integrator, the output of which is connected to the first inputs of two amplitude comparators, the second inputs of which are connected to the busses of the reference voltage 2.

However, this frequency multiplier does not provide sufficient stability when changing the frequency of the input signal.

The purpose of the invention is to increase the stability of the multiplication factor with a change in the frequency of the input signal, and also to increase the multiplication factor, f

The goal is achieved by the fact that a frequency multiplier containing a controlled integral pore, the output of which is connected to the first inputs of two amplitude comparators, the second inputs of which are connected to the buses of the reference voltages, is entered

the detector and connected in series between the control input of the controlled integrator and the input bus the pulse shaper and the key, and the information input of the controlled

The integrator is connected via a frequency detector to the input bus.

In addition, a third amplitude comparator and two NAND elements are entered, the inputs of the first of which are connected

to the outputs of the first two amplitude comparators, and the output is connected to the first input of the second NAND element, the second input of which is connected to the output of the third amplitude comparator, the inputs of which are connected respectively to the output of the controlled integrator and the third reference voltage bus.

The drawing is structural

electrical circuit frequency multiplier.

The multiplier contains a pulse former 1, a frequency detector 2, a key 3, a controlled integrator 4, am. large comparator 5, amplitude

the comparators b and 7 and the AND-NE elements 8 and 9. The input signal is fed to the input bus 10. On the buses 11-13, reference voltages are given and the output signals from the outputs 14 and 15 are removed.

The device works in the following way.

 From the rectangular-shaped input pulses with a duty cycle equal to two, the short pulses corresponding to the front and rear edges of the input pulses are separated by the shaper 1 of the pulses. With these pulses, the key 3 opens, which sets the integrator 4 to zero, the rest of the time, the output voltage of the integrator linearly increases. Under the action of the frequency of the input pulses, the frequency detector 2 produces a constant voltage proportional to the frequency of the input pulses, which is used as the input control voltage for the integrator 4. As a result, when the frequency of the input signal changes, the amplitude of the output voltage of the integrator 4 does not change, Consequently, the comparator 5, on one of the inputs of which this voltage is applied, and on the other input of which the reference voltage is applied (double-frequency pulses with a duty cycle equal to d- two, regardless of the variation of frequency and signal amplitude at the input of the multiplier.

Compilers b and 7 added to the circuit, one of the inputs of which are connected to the output of the integrator 4, and the second are supplied by reference voltages, i can be obtained from their outputs pulses with a duty cycle of four, shifted in time relative to each other by a quarter of their period follow up. With the help of the elements AND-HE 8 and 9, to the inputs of which the output voltages of the comparators 5 and 7 are applied, it is possible to obtain pulses with a borehole network equal to two, and a follow-on frequency, four times the hour at the input of the device.

In this frequency multiplier, the stability of the zero level of the integrator 4 over time is significantly higher than that of the known devices due to the fact that every half period of the input signal the integrator 4 is set to zero. This also ensures accurate phase assignment of output pulses to input pulses.

Claims (2)

1. A frequency multiplier containing a controlled integrator whose output is connected to the first inputs of two amplitude comparators, the second inputs of which are connected to the reference voltage buses, characterized in that, in order to increase the stability of the multiplication factor when the frequency of the input signal changes, . there are a frequency detector and connected in series between the control input of the controlled integrator and the input bus the pulse shaper and the key, and the information input of the controlled integrator is connected via frequency detector with input bus. 2. The multiplier of claim 1, wherein, in order to increase the multiplication factor, a third amplitude comparator and two AND-NOT elements, the inputs of the first of which are connected to the outputs of the first two amplitude comparators, are entered into it, and the output is connected to the first the input of the second NAND element, the second input of which is connected to the output of the third amplitude comparator, the inputs of which are connected respectively to the output of the controlled integrator and the third reference voltage bus. Sources of information taken into account in the examination 1. US patent number 3706048, kl.331-5 21.12.72. 2. Electronics, 1974, No. 2, 43, S. 201-205.