SU572792A1 - Multiplying device - Google Patents

Description

The device works as follows.

The master oscillator 6 generates pulses that arrive at the input of the frequency division unit - on two 7 and simultaneously control the operation of the Width-pulse modulator 5. The signal from the output of the frequency division unit to two 7 sets the trigger to one state. The output voltage of the trigger 8 controls the operation of the two input modulators Y and 1, the information inputs of which receive input signals, respectively.

The first input signal, modulated by the first input modulator 1 and amplified by the first amplifier of alternating current 2, is fed to the input of the adder 3, to the second input of which a voltage is applied from the output of the constant voltage source 4, the value of which is greater modulo the maximum value of the first input signal. The output voltage of the adder is fed to the information input of the pulse-width modulator 5.

The output signal of the pulse-width modulator 5 is a sequence of pulses, the duration of which is proportional to the sum and difference of the first input signal and the voltage of source 4, respectively, and the period is determined by the period of the signals from the master oscillator.

This signal arrives at the counting input of trigger 8, which on each negative front of the pulses from the output of the pulse-width modulator 5 changes its state, and the pulse from the output of the frequency division unit by two 7 does not cause a change in the state of trigger 8 during normal operation only confirms the single state of the trigger 8 at the moments of arrival of these setting pulses.

If at some time a failure occurs and the trigger 8 spontaneously changes its state, then the pulse from the output of the frequency division unit by two 7 returns the whole device to the desired mode, i.e. the failure is automatically eliminated after a period of time exceeding the time equal to two periods of the frequency from the master oscillator 6.

As mentioned above, the output signal of the trigger 8 is fed to the control inputs of both input modulators 1 and 9.

The first input signal from the output of the first input modulator 1 is amplified by the first AC amplifier 2, the output of which produces a pulse signal with positive and negative pulses, the amplitude of which is proportional to the magnitude of the first input signal. From the output of the first AC amplifier 2, this signal goes to an additional output low-pass filter 12, the passband of which is chosen so that the signal at its output is the average

value for the period of the first input signal. It is assumed that the first input signal passes through an additional output low-pass filter 12 without distortion, i.e. the frequency of the first harmonic of the pulse signal is much higher than the maximum frequency of the first input signal.

.In this case, the output signal from the additional output low-pass filter

12 is proportional to the square of the value of the first input signal of the device.

The output signal of the second AC amplifier 1U is also a pulse signal with positive and negative pulses, the amplitude of which is proportional to the magnitude of the second input signal acting on the input of the second input modulator 9.

Output filter bandwidth

low pass 11 is selected from the same conditions as the additional output low pass filter 12.

In this case, the output signal from the output filter Bottom frequency 11 is proportional to

the product of the values of the first and second input signals.

The use of new blocks (trigger 8 and additional output low-pass filter 12} distinguishes the proposed

multiplying device from the specified prototype, because, firstly, the accuracy of the device is improved, by excluding the analog key from its scheme, the residual parameters of which introduced an error, secondly, the device’s functional capabilities were expanded almost without complicating the equipment, since the proposed device allows perform two mathematical operations on the input quantities — their multiplication and squaring one of them, without introducing additional complex functional blocks, into Thirdly, in comparison with the prototype, sensitivity is increased by 2 times through both channels.

Claims (2)

1. USSR author's certificate No. 524192, cl. G 06G 7/161, 1974. 2. USSR author's certificate №520599, cl. G 06G 7/161, 1974.