SU809144A1 - Device for interfacing computer with pulse transducers - Google Patents

Description

(54) DEVICE FOR PAIRING COMPUTATIONAL MACHINE WITH PULSE SENSORS

The invention relates to computing technology and can be used in automated process control systems having a large number of sensors to be monitored and it is required to ensure automatic collection and processing of information. A device for interfacing a computer with two-position impulse sensors is known, which comprises a forming unit connected to the first input of the device, a coding unit whose input is connected to the output of the forming unit, matching block, the input of which is connected to the output of the coding unit, an OR element that is connected with the first output of the matching unit, and the output with the first output of the device, the output register, the first input of which is connected to the second output of the matching unit, the output with the second output of the device VA, and the second input is from the control input of the device 1. The disadvantage of this device is the considerable hardware costs that are required with a large number of sensors. The closest to the proposed technical solution is a device for interfacing a computer with discrete sensors, which contains a group of drivers, two address encoders, outputs connected via communication lines to the switch inputs, the outputs of which are connected to the inputs of the OR register of the output register and the comparison circuit The outputs of which are connected to the inputs of the signaling node and the register of error 2. The disadvantage of this device is the large hardware costs. The purpose of the invention is to reduce hardware costs. The goal is achieved by the fact that in a device containing a group of drivers, the outputs of which are connected to the corresponding inputs of the address encoder, the outputs of which through the amplifier-driver are connected to the inputs of the OR element, the output of which is the control output of the device, and to the information inputs of the on-off register, the control input and information outputs of which are respectively a control input and a group of information, device outputs, a control register, a decoder, an element group are entered Commod OR, the group of elements And and the group of encoders, the inputs of the elements OR of the group are the corresponding information inputs of the device, the outputs are connected to the inputs of the corresponding, their formers group of inputs of the control register are the group of control inputs of the device, and the output is connected to the input of the decoder, the outputs of which are connected to the group of control outputs of the device and the first inputs of the AND elements of the group, the second inputs of which are connected to the output of the OR element, and the outputs to the inputs of the corresponding encryption group, the outputs of which are connected to the inputs of group of information inputs of the output register.

The drawing shows the block diagram of the device.

The device contains elements 1 OR groups providing isolation between the output circuits of the adjacent sensors, shapers of group 2 generating single pulses of the required shape at the signal of the corresponding sensor, the address encoder 3 forming the address code of the sensor that has been triggered, amplifier 4, element 5 OR Forwarding, based on the code bit pulses, a single pulse, which is a signal to the computing machine about the receipt of the next message and providing the formation of the base bits message addresses, the output register 6, which stores the code of the address of the message from the moment it arrives until it is issued to the computer by its command, the control register 7, the storage mode code of the device, issued by the computational mask, the decoder 8, elements 9 and groups that pass a single pulse from the output of the control circuit 5 OR only if there is a resolving potential from the output of the decoder 8, group 10 encoders forming the required additional bits of the address code of the triggering sensor, inputs 11 of the inf group rmatsionnyh input device 12 outputs a group of information outputs of the device, input group 13 actuating device inputs, outputs 14 groups actuating device outputs, control inputs 15 and the output 16 of the device.

The device works as follows.

A computational computing interface, writing the required code to the control register 7 via inputs 13, sets the device operation mode. This is done with the help of a decoder 8, which, analyzing the contents of the bits of the control register 7, generates a signal which, via the corresponding output 14, activates

the corresponding group of matched sensors opens one of the elements 9 I. In each separate period of time only one group of sensors works, namely the one that received a signal from the decimator 8. Each of these sensors is connected to the corresponding input of the element of the same name OR, output which shapers 2 signals are triggered sensors. From the output of the formers 2 at the time of the sensors

a voltage pulse of desired amplitude and short duration is output. This pulse arriving at the corresponding input of the recorder 3 causes the parallel binary code of the address of element 1 to be output from the output of the encoder 3. The bits of this code are transmitted through the communication channel through the amplifier-shaper 4 to the information input of the output register 6 and element 5 OR. In output register 6, the signal code is memorized by the first part of its triggers, and element 5 OR forms a single impulse, coming through output 16 to the input of the computer, signaling the receipt of the next message about the operation of one of the sensors, as well as to the second inputs of elements 9 I. However This impulse can pass only through that element 9 I, at the first input of which the permitting signal of the decipher 8 is fed. From the output of this element 9 I, a single impulse goes to the input corresponding 10 encoder 10, which forms the code address of the sensor that worked. From the output of the encoder 10, the code for the address of the sensor enters the output register 6 and is memorized by the second part of the triggers of this register. Thus, the full parallel binary code of the address of the triggered sensor appears in the output register 6. At the command of the computer transmitted through the input:. the control input of the output perncTj of the incoming message, the capturing of Cc1 :: ms, into the memory of the associated calculate /. machine.

Claims (2)

Invention Formula A device for interfacing a computer with pulse sensors, which contains a group of drivers, whose outputs are connected to the corresponding inputs of the address tuner, the outputs of which are connected through the amplifier-driver to the inputs of the OR element, whose output is the control output of the device, and to the information inputs of the output register The control input and information outputs of which are respectively a control input and a group of information outputs of the device, characterized in that, for the purpose of intelligent hardware costs, the control register, the decoder, the group of elements OR, the group of elements AND and the group of encoders are entered into the device, the inputs of the elements of OR group are the corresponding information inputs of the device, and the outputs are connected to the inputs of the corresponding drivers of the group, the inputs of the control register are The group of control inputs of the device and the output are connected to the input of the decoder, the outputs of which are connected to the control group ftUlU JUlu.; - l of the device's OUTPUTS AND the first inputs of the elements And the groups, the second inputs of which are connected to the output of the element OR, and the outputs - to the inputs of the corresponding encoder groups, the outputs of which are connected to the inputs from the group of information inputs of the output register. Sources of information taken into account in the examination 1. USSR author's certificate number 371574, cl. G 06 F 3/04, 1970. 2. The USSR author's certificate for. n hl / - .g, -t / 1 o r, xg- PS with Vk. No. 2658987 / 18-24, cl. About Ob h d / 04, 1978 (prototype).