SU976463A1 - Device for remote indication with time division of channels - Google Patents

Description

(5) DEVICE FOR TELESIGNALIZATION WITH TEMPORARY SEPARATION OF CHANNELS

&

The invention relates to automation and telemechanics and can be used to remotely monitor the states of dispersed objects.

The known system tepesignalization with time division channels, containing N serially connected peripheral devices, each of which contains a clock receiving unit and a clock receiving unit, the inputs of which are connected to the first input of the peripheral device, the second input of which is connected to the first input of the shift register, peripheral signal inputs devices are connected to the corresponding second inputs of the shift register, the third input of which is connected to the output of the clock receiving unit, output Shift Registers connected to the first input of the peripheral device, and when. A mobile device, the input of which is connected to a communication line, contains a synchronization unit, drivers of clock pulses and sync pulses, and a shift register, the output of which is attached to the first input of the And element, the output of which is connected to the input of the terminal transformation unit 11.

The disadvantage of the system is its complexity due to the need to organize direct addressing when accessing each of the peripheral devices.

This deficiency is particularly pronounced in cases where

The connection of peripheral devices to the communication line is strictly sequential, i.e. the communication line has a filamentary structure, without branches.

 The closest in technical essence to the proposed is a time-divided video signaling device. This device, 3, E7, contains N serially connected monitored points, each of which contains a clock pulse receiver and a clock pulse receiver, whose inputs are connected to the first input of the monitored point whose second input is connected to the first input of the shift register. The signal inputs of the controlled points are connected to the corresponding second inputs of the shift register, the third input of which is connected to the output of the clock pulse receiver, the output of the shift register is connected to the first input of the monitored switch on the second input of the device, the first output of the receiver of clock pulses is connected to the fourth input of the shift register, and the second output of this block is NOT connected to the fifth input of the shift register, and the control point whose input is connected to zi containing a synchronization unit, a clock generator, a clock pulse generator and a shift register, the output of which is connected to the first input of the AND element whose output is connected to the input of the terminal transformation unit, The second and second outputs of the synchronization unit are connected, respectively, through the synchronization pulse shaper and through the pulse shaper generator to the control point input and the first input of the shift register; the first output of the synchronization unit is connected to the second input of the And2 element. The disadvantage of this device is the inability -, nor information about the health of the sensors connected to the signal inputs of the monitored points and ensuring the generation of signals about the state of the corresponding monitored objects This leads to a decrease in the reliability of information received by the receiving device on the state of the controlled objects. The aim of the invention is to increase the reliability of information transfer. The goal is achieved by the fact that in a device for remote signaling with a time division of channels consisting of controlled points, each of which contains a shift register, the first outputs of which are connected to the signal inputs of the controlled point, a pulse selector, the output of which is connected to the clock receiver inputs and to the input of the receiver of clock pulses, the output of the receiver of clock pulses is connected to the second input of the shift register, the output of the receiver of clock pulses is connected to the third input of the shift register and via ele ENT to the fourth input of the shift register, the first output of which is connected to the input-output of the controlled point, the input-output of each of its previous controlled points is connected through the pulse selector to the fifth input of the shift register of each subsequent controlled point, the control point containing the synchronization unit , the first output of which is connected to the input of the sync pulse generator and to the first input of the AND element, the second output of the synchronization unit is connected to the input of the clock pulse generator and to the first one One shift register, the output of which is connected to the second input of element 11, the outputs of the sync pulse and clock pulses are connected to the second input of the shift register and the output of the control point, which is connected through the communication line to the output-input of the first controlled point, and the signal converter, the shaper is entered control pulses, the address driver of which input is connected to the third output of the synchronization unit, and the output is connected to the first input of the signal processing unit and to the input of the driver con pulse pulses, the output of which is connected to the second input of the shift register and the input-output of the control point, the output of the element I is connected to the second input of the signal processing unit, the output of which is connected to the input of the signal converter; the first inputs of which are connected to the output of the receiver of clock pulses, the second inputs are connected to the second outputs of the shift register, the outputs of the group of elements I are connected to the control outputs of the controlled point, the last controlled by kt further comprises a control pulse receiver, whose output is connected to a fifth input of a shift register control pulse input of the receiver

connected to the pulse selector output.

The drawing shows a diagram of the device.

The scheme includes groups of controlled points 1 and the last controlled point 2, connected via line 3 to point t of control. Each controlled item 1 contains a receiver of 5 clock pulses, a receiver of 6 clock pulses, a shift register 7, a selector 8, an element of HE 9 and elements of AND 10.

The signal inputs 11 of the device are connected to the write inputs of the shift register 7. The input and output of the shift register are connected to link 3, to which the inputs of receivers .5 and 6, respectively, of clock pulses and sync pulses are also connected. The output of the receiver 5 clock pulses is connected to the clock input of the shift register 7, the output of the receiver 6 clock pulses is connected to the write input of the write register 7 of the shift and through the element 9 to the input of the shift resolution of this register. The selector 8 is connected to the line 3 between the points of connection to the nets of the shift register 7, on the one hand, and the inputs of the receivers 5 and 6, respectively, of clock pulses and sync pulses and the output of the shift register 7.

The bit outputs of the shift register 7 through the elements And 10 are connected to the control outputs 12 of the controlled point 1. The control inputs of the elements And 10 are connected to the output of the receiver 6 clock pulses.

The last monitored item 2 contains the same elements connected to each other in the same way as any of the controlled items, except for the fact that an additional 13 control pulses were added to it.

Control point k contains a synchronization block k, formers 15, .16 and 17, respectively, of clock pulses, sync pulses and KOHT pulses.

a roll, a control address generator 18, a shift register 19, a processing unit 20, a signal converter 21 and an AND 22 element. When the device is operated by a synchronization unit, a clock pulse sequence is constantly generated at its output 23. and the output 25 of the sequence of pulses, clocking the work of the former 18 address control.

The operation of the device is organized according to a cyclic principle, the cycle being set by the interval between two successive sync pulses. Consideration of the operation of the device is convenient to begin from the moment when a synchronous pulse and a clock pulse are simultaneously output to the communication line 3, and there is no signal at the output of the driver 18. Shapers 15 and 1b, respectively, of clock pulses and sync pulses, when outputting to link 3, provide a representation of these pulses, which allows them to be reliably separated in controlled points 1 and 2 (for example, using frequency modulation with different carriers).

When the receiver receives 6 synchronized pulses of controlled points at its output, a signal is generated that arrives at the register recording enable input. 7 shift. The same signal through the element NOT 9 enters the shift enable input of the same register, causing the shift ban. A clock pulse selected simultaneously by the receiver of 5 clock pulses arrives at the clock input of the shift register 7, ensuring that signals from the signal inputs of the 11 monitored points are written to it, indicating the current state of the monitored points connected to it.

Later, within one cycle, only clock pulses continue to arrive at the inputs of the controlled points, and at the moment each of them arrives at the output of the 6 sync pulses there is a signal that prohibits parallel writing to the shift register 7, and, due to the presence of the HE element 9, allows this register. In this case, the signal from the output of the shift register 7 of one controlled point 1 (or 2) goes through link 3 to the input of the shift register 7 of the controlled point 1, which is closest to the first in the direction towards point 4 of the control. The output from the output of the shift register 7 of the controlled point 1, which is closest to control point k, is fed through the link 3 to the control register register 19, the clock input of which is nocTynaviT clock pulses from the output of the synchronization unit, thereby in the shift register 19 to the end of the cycle It turns out that the state of all controlled points connected to the device is written in a positional form. Let us accept for one-to-one correspondence the numbers of each of the bits of the register 19 by shifting one of the signal inputs 11 of one of the controls. Claimed points 1 (or 2). In addition, due to the presence of a zero signal at the receiver output O of the control pulses of the controlled point 2 in the absence of the control pulses at the output of the driver 17 of the control pulses, the shift registers 7 of all peripheral devices of the controlled points are shown to be zeroed by the end of the cycle. The arrival of signals from the output of any of the shift registers 7, at its own input and at the inputs of other shift registers 7, besides the shift register 7 of the nearest controlled point 1, is excluded due to the presence of a selector 8 that prohibits the passage of signals in the view corresponding to the signal the output of the shift register 7 and allowing the passage of the signal in a representation corresponding to the representation of clock pulses, clock pulses. When the synchronization block 1k forms a synchronization clock at its output bca otpiraets AND gate 22 and the data from the shift register 19 in block 20 perepisyvayuts processing. In the absence of signals at the second input of this block from the output of the former 18, the monitoring addresses received by the processing unit 20 are transmitted unchanged in the converter 21, where they are converted into a form convenient for the operator to perceive or to transfer to other devices. Next, the operation of the device proceeds according to the cycle described above. The control address generator 18, based on a sequence of pulses arriving at its input from the output of synchronization unit 1, in accordance with the program embedded in it, periodically generates control pulses at its output, which are output by means of the pulse former 17 3 connections in a representation other than the representation of clock pulses and sync pulses. For practical reasons, the period of formation and (5 control pulses are chosen substantially (by many orders) longer than the sync pulse generation period. The formation of each control pulse is synchronized with one of the clock pulses. The appearance of a counter pulse in the link 3 link causes a time equal to its duration, the significant signal at the output of the receiver is 13 pulses of control of the last controlled point, therefore, the recording of G to the initial discharge of register 7 of the shift of this controlled point in yes Due to the continued generation of clock pulses, this 1 moves along the chain of shift registers 7 towards the control point C, providing by the time of the next sync pulse recorded in the cell of one of the shift registers 7 of one of the controlled points, the number of which is read from the beginning the chain of shift registers 7 on the side of the control point is equal to the number of the clock pulse counted from the beginning of the cycle, synchronously with which a control pulse is formed at the output of the generator 18 of the counter address l When this monitored item 1 or 2 arrives at the input of the next sync pulse, a signal is generated at the output of the sync pulse generator, causing "10 unlocking the AND 10 elements and passing the control signal to the corresponding output 12 of the monitored point. This signal, arriving at the control circuit of the sensor, providing the necessary representation of the signal about the state of the corresponding monitored object for input into the monitored item 1 (or 2) causes (with a certain allowable delay, a change in the signal at the output of this sensor and the recording of this change in one of the subsequent cycles in the shift register 7 of this controlled point, after which this information is entered as described above into the corresponding bit of the shift control register 19, it goes further to the processing unit 20 heel. Block 20 processing is carried out the following operations.

On the basis of a comparison with the signal received earlier from the output of the pulse control address setting block, it is determined whether there is a recorded change in the state of the monitored object that reacts to the control signal or it corresponds to a real change in the state of this object.

Based on a comparison of the interval between the arrival of the corresponding control pulse and the response information to the processing unit with the permissible value of this interval, it is determined whether the sensor parameters correspond to its requirements.

As a result of the block

20, the analysis of the state of the monitored object is extinguished and is not transmitted to the converter 21, if it is determined that this signal is a response to the monitoring pulse and the delay in its formation lies within acceptable limits. Otherwise, the converter

21 displays information about the detection of a malfunction of the corresponding sensor.

The order of checking various sensors is determined by the program included in the control address setting block. Thus, in the proposed system, it is possible to periodically check the technical state of the sensors, which ensure the conversion of signals about the state of monitored objects into a form that allows them to be entered into the system, thus increasing the reliability of information about the state of monitored objects entering the system output.

Claims (2)

1. USSR author's certificate No. UB b, cl. G 08 C 19/28, 197. 2. USSR author's certificate as per Vf 282882t / l8-2t, 05.10.79 (prototype).