SU877422A1 - Decoder for multi-channel acoustic emission instruments - Google Patents

Description

The invention relates to indisputable control and can be used in devices for monitoring the quality of products using acoustic emission. A decoder is known that identifies the correspondence between the structure of received signals and the fl message code. The disadvantage of this decoder is that it cannot used in the control of a random process. Closest to the proposed is a decoder for multichannel acoustic emission instruments containing the first AND-OR scheme, the first differentiating circuit and the first, AND circuit, connected in series the first OR circuit, the first key and the first trigger, connected in series, the second circuit AND - OR, the second differentiating circuit and the second AND circuit, connected in series, the second OR circuit, the second key and the second trigger, connected in series as well as the third OR circuit, the output of which is the decoder output, and the inputs Connected to the outputs of the first and second AND circuits, the second inputs of which are connected together and form the controlling input of the decoder, the output of the first trigger is connected to the first control inputs of the second AND-OR circuit and the second key, and the second trigger output inputs of the first AND-OR scheme and the first key, triggers are covered by a common bus. Resetting the first inputs of the first AND-OR scheme and the first OR circuit, together with their second inputs, form the first pair of decoder inputs, and the first key s second OR-AND circuit and a second OR circuit, and also connected with their second inputs constitute a second pair of inputs of the decoder 2. The disadvantage of the known decoder is limited applicability devices for determining the coordinates of two acoustic emission sources. The purpose of the invention is to expand the scope. The postshched goal is achieved by the fact that the decoder is equipped with a third AND-OR circuit, a third differentiating circuit and a third AND circuit connected in series, a fourth OR circuit, a third key and a third

a trigger connected in series, a fourth circuit and-OR, a fourth differential circuit and a fourth circuit AND connected in series, and a fifth OR circuit, four keys and a fourth trigger sequentially connected, with the first trigger connected to the first control the inputs of the third and fourth circuits AND-OR, as well as the third and fourth keys, the output of the second trigger with the second control inputs of the third and fourth circuits AND-OR, as well as the third and fourth keys, the output of the third trigger - with the second control inputs of the first and second AND-OR circuits, as well as the first and second keys, and with the third control inputs of the fourth AND-OR circuit and the fourth key, the output of the fourth trigger with the third control inputs of the first second and third circuits AND-OR and the first, second and third keys, the second inputs of the third and fourth circuits AND connected to the bus. The input of the decoder outputs of these circuits AND are respectively connected to the third and fourth inputs of the third OR circuit, connected together the first inputs of the third AND circuit. OR a fourth OR circuit, and also connected to second inputs and H together form a third pair of inputs of the decoder, and coupled together first inputs of the fourth AND-OR circuits, and the fifth OR gate, and connected by their second inputs together form a fourth pair of decoder inputs.

The block diagram of the decoder shown in the drawing.

The decoder consists of the following nodes and connections. The first circuit 1 is the first differentiating circuit 2 and the first circuit 3 is connected in series. The first circuit 4 OR, the first KEY 5 and the first trigger b are connected in series. The second circuit 7 ORI, the second differentiating circuit 8 and the second circuit 9 I are connected in series. The second circuit 10 OR, the second key 11 and the second trigger 12 are connected in series. The third circuit 13 OR inputs are connected to the outputs of all AND circuits, and its output is the decoder output, the second inputs of all AND circuits are connected together and the control input of the decoder is selected. The third is a 14 AND-OR circuit, a third of the differentiating circuit 15 and a third of the 16 AND circuit are connected in series. The fourth circuit 17 OR, the third key 18 and the third trigger 19 are connected in series, the fourth circuit 20 Y – OR, the fourth differentiating circuit 21 and the fourth circuit 22 I are connected in series. The circuit 23 OR, the fourth key 24 and the fourth trigger 25 are connected in series. The output of the first trigger 6 is connected to the first control inputs of the second 7, third 14 and fourth 20 AND-OR circuits, second 11. third 18 and fourth 24 keys. The output of the second trigger 12 is connected to the first control inputs of the first AND-OR circuit 1 and the first key 5, as well as to the second control inputs of the third 14 and fourth 20 AND-OR circuits and the third 18 and fourth 24 keys. The output of the third trigger 19 is connected to the second control inputs of the first 1 and second 7 AND-OR circuits and the first 5 and second 11 keys, as well as to the third control inputs of the fourth AND-OR circuit 20 and the fourth key 24. The output of the fourth trigger 25 is connected to the third control inputs of the first 1, second 7 and third 14 AND-OR schemes and the first 5, second 11 and third 18 keys. The first inputs of the first scheme 1 AND-OR and the first scheme 4 OR, together with their second entrances together, form the first pair (in Fig. 1 - IV and VI) of the decoder inputs. Together, the first inputs of the second circuit 7 are AND-OR and the second circuit 10 OR, and the second inputs connected together their second inputs form the second pair (IK and V) of the decoder inputs. Together the first inputs of the third circuit 14 ORI and the fourth circuit 17 OR, as well (the second inputs connected together form the third pair (II and V / M) of the decoder inputs. The first inputs of the fourth circuit 20 ORI and the fifth circuit 23 OR connected together as well as their second inputs connected together form the fourth pair (I and MI) of the decoder inputs All triggers are covered by a common bus Reset.

The decoder works in the following way.

The signals to the inputs I - VI / I of the decoder come from the outputs of the receiving channels and amplifying the acoustic emission signals of a multichannel device to determine the three coordinates of their sources.

The signals on the inputs appear in different sequences over time; of these, permissible (i.e., corresponding to the same SOURCE of the signals) are those in which the first and last signals appear on one pair of inputs, and the time on between the other events appear on all the other inputs.

Therefore, the functionally decoder consists of the schemes for detecting the first of the signals on one pair of inputs (for example, the first 4 OR circuit, the first key 5 and the first trigger b) and the schemes for detecting the last of the signals on that pair of inputs (for example, the first 1 AND-OR circuit , the first differentiating circuit 2 and the first scheme 3 I). The pairs of those and other circuits each contain a decoder of 4. Let the input signal I appear first. Through the fifth circuit 23 OR and the open fourth key 24, this signal overturns the fourth trigger 25. The signal of the latter closes the first 5, second 11 and third 18 keys so that the appearance of signals on the remaining inputs of the decoder could not cause the first 6, TWO 12 or the third 19 triggers, and also locks the first 1, second 7, and third 14 AND-OR schemes so that the appearance of signals at the inputs (inputs of the decoder) cannot cause the appearance of signals at the outputs. At the moment of the occurrence of the last (in time) signal at the inputs of the decoder (in this case, it should be the input of the same pair, i.e. a signal (coincidence of the signals on the inputs), from which the fourth differentiating circuit 21 forms a short pulse arriving at the first input of the fourth circuit 22 I. Simultaneously with it, the decoder control input, i.e. To the second input of the fourth circuit 22 And a signal is received (from external DEVICES) to receive the last acoustic emission signal by the last of the channels of this group. Such a signal in multi-channel instruments for determining coordinates is always generated. In this case, a signal appears on it, which through the third circuit 13 OR arrives at the output of the decoder and is used in a multichannel device as a signal of the correct (according to the sequence of events) reception of acoustic emission signals. At this, the operation of the decoder ends, after which its triggers (in this case, the fourth trigger 25) are reset to the initial state by issuing the Reset command

Claims (2)

1. Automation of production and industrial electronics. Ed. A.I. Berga, M., Sovetsk Encyclopedia, 1962, p. 323. 2. USSR author's certificate for application 2700529/28, cl. G 01 N 29/04, 1978 (according to type). . 8lo9 and dewuippamopa Lunge tt