SU797078A1 - Pulse counting device - Google Patents

Description

(54) DEVICE FOR PULSE ACCOUNT

The invention relates to a pulse technique, in particular to counters of electric pulses, and can be used in code converters, in devices for counting and recording the number of pulses, in devices for program-time control, etc. A device for counting pulses is known, which contains triggers and logic elements l. A disadvantage of the known device is the relatively low noise immunity. A pulse counter is known that contains an input bus, main triggers, a null organ, sovpadeNIN elements, an additional trigger, a NO element and a reversible counter, and a single bus is connected to the input of the first trigger through the first match element with the second trigger input and through the second match element and through the NO element , the second inputs of the coincidence elements are connected appropriately with the inverse and zero outputs of the additional trigger; the output of the element NO is connected to the subtraction input of the versatile counter, the input of which is the third coincident element is connected to the input bus; the zero input of the additional trigger is connected to the output of the zero-organ whose input is connected to the output of the reversible counter, the blocking input of which is connected to the control input of the NO element, to the second input of the third coincident element and to the zero output of the additional trigger 2. A disadvantage of the known device is the possibility of the occurrence of failures both in the main and in the reverse meters due to external interference, which leads to any large error; sc-this. The purpose of the invention is to improve the noise immunity of the device for: pulse counting. To achieve the stated purpose, a pulse counting device containing an input bus, a main counter, a null organ, two coincidence elements, and an additional trigger were entered into a register, a combination adder, a fixation block, a code change, two delay elements, two groups of valve elements,. the element NOT and the element OR, the outputs of the main counter are connected to the code change block, the inputs of the first group of valve elements and the first inputs of the combinational adder, the second inputs of which are connected to the inputs of the second group of valve elements and memory register outputs, which connected to the outputs of the first group of valve elements, the installation inputs of the main counter are connected to the outputs of the second group of valve elements, the output of the combinational adder through the zero-org is connected to the input one element of the NOT and with the first input of the first element of coincidence, the output of which is connected to the control input of the first group of valve elements and with the first input of the OR element, the second input of which is connected to the control input of the second group, valve elements and with the output of the second element of the first input which is connected to the output of the NOT element, the second input is connected to the second input of the first matching element and to the output of the first delay element, the third inputs of the first and second matching elements are additionally connected with the output About the trigger, the installation input to the unit of which is connected to the input of the first delay element and to the output of the fixing unit of the code change, the installation input to zero of the additional trigger is connected to the output of the second delay element, whose input is connected to the output of the OR element, the input bus is connected to the clock the input of the main counter.

FIG. 11 is a block diagram of a pulse counting device; in fig. 2 - functional - block code fixing circuit diagram.

The device contains the main counter 1, group 2 of valve elements, memory register 3, combinational adder 4, block 5 for fixing code changes, delay element b, elements of coincidence 7 and 8, additional trigger 9, element OR 10, group 11 of valve elements, null organ 12, the element is NOT 13, the element. Of the delay 14 and the input bus 15 (FIG. 1), the differentiating elements 1 - 16s4 and the element OR 17 (FIG. 2).

The outputs of the main counter 1 are connected to the inputs of a group 2 of valve elements, with the inputs of the code change fixing unit 5 and the first inputs of the combinational adder 4, the second inputs of which are connected to the outputs of memory register 3 and to the inputs of the group 11 of valve elements whose outputs are connected to the installation inputs The main counter 1, the clock input of which is connected to the input bus 15, the output of the combinational adder 4 is connected through the null-body 12 to the input

an HE element 13 and the first input of the coincidence element 7, the second input of which is connected to the output of the delay element 6 and the first input of the coincidence element 8, the second input of which is connected to the output of the HE element 13, and the third input to the output of the additional trigger 9 the third input of the coincidence element 7, the output of which is connected to the control input of the house of group 2 valve elements and the first input of the element OR 10, the second input of which is connected to the control input of the group 11 of the ventilation elements and with the output of the coincidence element 8 10 soedinencherez delay element 14 with the zero setting input of the additional flip-flop 9, a set input which is connected to unit delay element .The inputs bis output fixing unit 5 changing code. The outputs of the differentiating elements 16s4 are connected to the inputs of the element OR 17 (FIG. 2). The inputs of the differentiating elements - and the output of the element OR 17 are respectively the inputs and the output of the block 5 for fixing the code change.

The device works as follows.

In the initial state, the groups of valve elements .2 and 11 are locked, the additional trigger 9 is in the zero state. In the main counter 1 and register 3, the same. Codes are recorded.

With the input from the input bus 15 to the counting input of the main counter 1 of the next read signal, the counter changes its state and its code (under the condition of normal non-failure operation) is changed by one. In this case, a change in the code causes a change in the potentials at the outputs of one or several bits of the counter. These potential changes are differentiated in the corresponding differentiating elements — and through the OR element 17 they arrive at the output of the fixing unit 5, the code change, to the input of the delay element 6 and to the installation input to the unit of additional trigger 9. The trigger goes to one state and to one of the inputs coincidence 7 and 8 appears resolving potential. In the first delay element b, the signal is delayed by the time required for triggering the flip-flop 9, after which a matching potential appears at the second inputs of the coincidence elements 7 and 8.

The adder 4 is supplied with a direct code from the bits of the main counter 1 and a reverse code from the bits of the register 3 memory. There are two possible variants of the adder's output code for such a signal. If the code

If the counter is one greater than the code in the memory register, then all outputs of the bits of the adder have zeros. An exception is the output of n + 1 bit, on which there is a unit, but this output of the adder is not used (n is the number of bits in the main counter 1) and in memory register 3). If the codes of the main counter and the memory register differ by any other number, then a single potential is established at the output of one of the n bits of the adder.

During normal operation, under the influence of each counting pulse, the main counter 1 increases its code by one. As a result, at the outputs of the adder 4, the potentials are absent, at the output of the null organ 12 a signal appears that passes through the coincidence element 7 to the control input of the group of valve elements 2, opens it, and the changed code from the main counter 1 is written to . register

3 Mom tees After this, the codes of the main counter and the memory register are again identical. To return the device to the initial state, the code rewriting signal from the output of the element of coincidence 7 through the element OR 10 and the second delay element

14 is fed to the input of setting zero an additional trigger 9, which is returned by it. to the initial (zero) state.

If, due to interference, the main counter 1 changes its state, while the code in it changes, as a rule, by more than one, then on some outputs of the bits the adder

4 single potentials are present. At the output of the zero-organ 12, the signal has a level of zero, but on the other hand, a single potential is established at the output of the element NOT 13. After the signals arrive at the second and third inputs of the coincidence element 8, it passes to the control input of the group of valve elements 11, opens it, and the code from memory register 3 goes to the installation inputs of the main counter 1, restoring the code

has been changed by interference.

Since the recovery of the code of the main counter 1 is accompanied by a change in the potentials at the output of some of its bits, an additional signal appears at the output of the block 5 for fixing the code change, which should not cause any change in the state of the main counter 1 and memory register 3. This is achieved by the fact that the delay time of the delay element 14 is selected greater than the sum of the delay time of the delay element 6 and the transient time in all other blocks of the device. Thus, the delayed rewrite pulse from memory register 3 to the main counter 1 is fed to the input of the installation zero of the additional trigger 9 and transfers it to J the initial zero state prohibiting the passage of signals from the matching elements 7 and 8 to the groups of valve elements 2 and 11 .

Due to the automatic correction of failures, the accuracy of the counting is significantly increased. The use of the proposed device for counting pulses in code-analogue converters, for example, in digital measuring devices under conditions of strong industrial and natural interference (for example, in workshop and field conditions), significantly reduces the likelihood of incorrect measurements, and therefore increases their accuracy. In addition, the application of the proposed device in

different} software drivers, for example, real-time, for automatic control systems

5 makes it possible to significantly increase the accuracy and reliability of the device due to the absence of failures in the software-time setting devices.

thirty

Invention Formula

Pulse counting device containing input bus, main

5 counter, n, ul-organ, two elements, coincidence, and additional trigger, characterized in that, in order to improve noise immunity, a memory register, a combinational adder, a code change fixation unit, two delay elements, two groups of valve elements are entered into it , the element and the element OR, the outputs of the main counter are connected to the inputs of the code change fixation block, to the inputs of the first group of valve elements and to the first inputs of the combinational adder, the second inputs of which are connected to the inputs of the second group of valves the individual elements and with the outputs of the memory register, the inputs of which are connected to the outputs of the first group of valve elements, the installation inputs of the main counter are connected to the outputs of the second group

5 valve elements, the output of the combinational, adder through the nullorgan is connected to the input of the element NOT and to the first input of the first element of coincidence, the output of which is connected to the control input –first

groups of valve elements and with the first input of the OR element, the second input of which is connected to the control input of the second group of valve elements and to the output of the second element ow-J f, (., t ;, ,,., t, - drops, the first input of which connected to the output of the NOT element, the second input to the second input of the first matching element and the output of the first delay element; the third inputs of the first and second matching elements are connected to the output of an additional trigger, the installation input of which is connected to the input of the first delay element and The unit for fixing the code change, the input of the setting to zero of the additional trigger, is connected to the output of the second delay element, whose input is connected to the output of the OR element, the input bus is connected to the clock input of the main counter. Sources of information taken into account in the examination 1 . USSR author's certificate No. 463235, class H 03 K 29/00, 1974. 2. Author's certificate USSR No. 307524, class H 03 K 23./00, 1970 (prototype).

Claims (2)

Claim A device for counting pulses, containing an input bus, a main counter, a pulse organ, two elements, matches and an additional trigger, characterized in that, in order to increase noise immunity, a memory register, a combinational adder, a code change fixation block, two elements are introduced into it delays, two groups of valve elements, the element NOT and the OR element, the outputs of the main counter are connected. with the inputs of the block for fixing the code change, with the inputs of the first group of valve elements and with the first inputs of the combination combiner, second whose inputs are connected to the inputs of the second group of valve elements and to the outputs of the memory register, the inputs of which are connected to the outputs of the first group of valve elements, the installation inputs of the main counter are connected to the outputs of the second group of valve elements, the combination output. the adder through a null organ is connected to the input of the element NOT 'and to the first input of the first coincidence element, the output of which is connected to the control input of the first group of valve elements and the first input of the OR element, the second input of which is connected to the control input of the second group of valve elements and the output of the second coincidence element, the first input of which is connected to the output of the element NOT, the second input - with the second input of the first ele * * ... ’·’ 7 yag 'if * v z-i "·· 1 ' - ·, ·. * * ’ the coincidence moment and with the output of the first delay element, the third inputs of the first and second coincidence elements are connected to the output of the additional trigger, the unit input of which is connected to the input of the first delay element and to the output of the code change fixing unit, the installation input is in the zero of the additional trigger *, ·· 79.7078 8 " pa is connected to the output of the second delay element, the input of which is connected to the output of the OR element, the input bus is connected to the clock input of the bases. counter. - Sources of information taken into account during the examination 1. USSR Copyright Certificate No. 463235, cl. H 03 K 29/00, 1974. 2. Copyright certificate of the USSR No. 307524, cl. H 03 K 23/00, 1970 (prototype). Figure 2